1read_verilog <<EOT 2module top(input a, b, output [5:0] y); 3and (y[0], a, b); 4nand (y[1], a, b); 5or (y[2], a, b); 6nor (y[3], a, b); 7xor (y[4], a, b); 8xnor (y[5], a, b); 9endmodule 10EOT 11select -assert-count 1 t:$and a:src=<<EOT:2.4-2.17 %i 12select -assert-count 1 t:$and a:src=<<EOT:3.5-3.18 %i 13select -assert-count 1 t:$or a:src=<<EOT:4.3-4.16 %i 14select -assert-count 1 t:$or a:src=<<EOT:5.4-5.17 %i 15select -assert-count 1 t:$xor a:src=<<EOT:6.4-6.17 %i 16select -assert-count 1 t:$xor a:src=<<EOT:7.5-7.18 %i 17