1# SV LRM A2.2.1 2 3read_verilog -sv <<EOT 4module test_signed(); 5parameter integer signed a = 0; 6parameter integer unsigned b = 0; 7 8endmodule 9EOT 10 11design -reset 12read_verilog -sv <<EOT 13module test_signed(); 14parameter logic signed [7:0] a = 0; 15parameter logic unsigned [7:0] b = 0; 16 17endmodule 18EOT 19 20design -reset 21logger -expect error "syntax error, unexpected TOK_INTEGER" 1 22read_verilog -sv <<EOT 23module test_signed(); 24parameter signed integer a = 0; 25parameter unsigned integer b = 0; 26 27endmodule 28EOT 29