1// 2// Copyright 2011 Ettus Research LLC 3// 4// This program is free software: you can redistribute it and/or modify 5// it under the terms of the GNU General Public License as published by 6// the Free Software Foundation, either version 3 of the License, or 7// (at your option) any later version. 8// 9// This program is distributed in the hope that it will be useful, 10// but WITHOUT ANY WARRANTY; without even the implied warranty of 11// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12// GNU General Public License for more details. 13// 14// You should have received a copy of the GNU General Public License 15// along with this program. If not, see <http://www.gnu.org/licenses/>. 16// 17 18 19 20// Dual ported, Harvard architecture, cached ram 21 22module ram_harv_cache 23 #(parameter AWIDTH=15,parameter RAM_SIZE=16384,parameter ICWIDTH=6,parameter DCWIDTH=6) 24 (input wb_clk_i, input wb_rst_i, 25 26 input [AWIDTH-1:0] ram_loader_adr_i, 27 input [31:0] ram_loader_dat_i, 28 input ram_loader_stb_i, 29 input [3:0] ram_loader_sel_i, 30 input ram_loader_we_i, 31 output ram_loader_ack_o, 32 input ram_loader_done_i, 33 34 input [AWIDTH-1:0] iwb_adr_i, 35 input iwb_stb_i, 36 output [31:0] iwb_dat_o, 37 output iwb_ack_o, 38 39 input [AWIDTH-1:0] dwb_adr_i, 40 input [31:0] dwb_dat_i, 41 output [31:0] dwb_dat_o, 42 input dwb_we_i, 43 output dwb_ack_o, 44 input dwb_stb_i, 45 input [3:0] dwb_sel_i, 46 47 input flush_icache ); 48 49 wire [31:0] iram_dat, dram_dat_i, dram_dat_o; 50 wire [AWIDTH-1:0] iram_adr, dram_adr; 51 wire iram_en, dram_en, dram_we; 52 wire [3:0] dram_sel; 53 54 dpram32 #(.AWIDTH(AWIDTH),.RAM_SIZE(RAM_SIZE)) sys_ram 55 (.clk(wb_clk_i), 56 57 .adr1_i(ram_loader_done_i ? iram_adr : ram_loader_adr_i), 58 .dat1_i(ram_loader_dat_i), 59 .dat1_o(iram_dat), 60 .we1_i(ram_loader_done_i ? 1'b0 : ram_loader_we_i), 61 .en1_i(ram_loader_done_i ? iram_en : ram_loader_stb_i), 62 .sel1_i(ram_loader_done_i ? 4'hF : ram_loader_sel_i), 63 64 .adr2_i(dram_adr),.dat2_i(dram_dat_i),.dat2_o(dram_dat_o), 65 .we2_i(dram_we),.en2_i(dram_en),.sel2_i(dram_sel) ); 66 67 // Data bus side 68 dcache #(.AWIDTH(AWIDTH),.CWIDTH(DCWIDTH)) 69 dcache(.wb_clk_i(wb_clk_i),.wb_rst_i(wb_rst_i), 70 .dwb_adr_i(dwb_adr_i),.dwb_stb_i(dwb_stb_i), 71 .dwb_we_i(dwb_we_i),.dwb_sel_i(dwb_sel_i), 72 .dwb_dat_i(dwb_dat_i),.dwb_dat_o(dwb_dat_o), 73 .dwb_ack_o(dwb_ack_o), 74 .dram_dat_i(dram_dat_o),.dram_dat_o(dram_dat_i),.dram_adr_o(dram_adr), 75 .dram_we_o(dram_we),.dram_en_o(dram_en), .dram_sel_o(dram_sel) ); 76 77 // Instruction bus side 78 icache #(.AWIDTH(AWIDTH),.CWIDTH(ICWIDTH)) 79 icache(.wb_clk_i(wb_clk_i),.wb_rst_i(wb_rst_i), 80 .iwb_adr_i(iwb_adr_i),.iwb_stb_i(iwb_stb_i), 81 .iwb_dat_o(iwb_dat_o),.iwb_ack_o(iwb_ack_o), 82 .iram_dat_i(iram_dat),.iram_adr_o(iram_adr),.iram_en_o(iram_en), 83 .flush(flush_icache)); 84 85 // RAM loader 86 assign ram_loader_ack_o = ram_loader_stb_i; 87 88 // Performance Monitoring 89 wire i_wait = iwb_stb_i & ~iwb_ack_o; 90 wire d_wait = dwb_stb_i & ~dwb_ack_o; 91 92endmodule // ram_harv_cache 93