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28*******************************************************************************/
29// The synthesis directives "translate_off/translate_on" specified below are
30// supported by Xilinx, Mentor Graphics and Synplicity synthesis
31// tools. Ensure they are correct for your synthesis tool(s).
32
33// You must compile the wrapper file fifo_s6_512x36_2clk.v when simulating
34// the core, fifo_s6_512x36_2clk. When compiling the wrapper file, be sure to
35// reference the XilinxCoreLib Verilog simulation library. For detailed
36// instructions, please refer to the "CORE Generator Help".
37
38`timescale 1ns/1ps
39
40module fifo_s6_512x36_2clk(
41	rst,
42	wr_clk,
43	rd_clk,
44	din,
45	wr_en,
46	rd_en,
47	dout,
48	full,
49	empty,
50	rd_data_count,
51	wr_data_count);
52
53
54input rst;
55input wr_clk;
56input rd_clk;
57input [35 : 0] din;
58input wr_en;
59input rd_en;
60output [35 : 0] dout;
61output full;
62output empty;
63output [9 : 0] rd_data_count;
64output [9 : 0] wr_data_count;
65
66// synthesis translate_off
67
68      FIFO_GENERATOR_V6_1 #(
69		.C_COMMON_CLOCK(0),
70		.C_COUNT_TYPE(0),
71		.C_DATA_COUNT_WIDTH(9),
72		.C_DEFAULT_VALUE("BlankString"),
73		.C_DIN_WIDTH(36),
74		.C_DOUT_RST_VAL("0"),
75		.C_DOUT_WIDTH(36),
76		.C_ENABLE_RLOCS(0),
77		.C_ENABLE_RST_SYNC(1),
78		.C_ERROR_INJECTION_TYPE(0),
79		.C_FAMILY("spartan6"),
80		.C_FULL_FLAGS_RST_VAL(1),
81		.C_HAS_ALMOST_EMPTY(0),
82		.C_HAS_ALMOST_FULL(0),
83		.C_HAS_BACKUP(0),
84		.C_HAS_DATA_COUNT(0),
85		.C_HAS_INT_CLK(0),
86		.C_HAS_MEMINIT_FILE(0),
87		.C_HAS_OVERFLOW(0),
88		.C_HAS_RD_DATA_COUNT(1),
89		.C_HAS_RD_RST(0),
90		.C_HAS_RST(1),
91		.C_HAS_SRST(0),
92		.C_HAS_UNDERFLOW(0),
93		.C_HAS_VALID(0),
94		.C_HAS_WR_ACK(0),
95		.C_HAS_WR_DATA_COUNT(1),
96		.C_HAS_WR_RST(0),
97		.C_IMPLEMENTATION_TYPE(2),
98		.C_INIT_WR_PNTR_VAL(0),
99		.C_MEMORY_TYPE(1),
100		.C_MIF_FILE_NAME("BlankString"),
101		.C_MSGON_VAL(1),
102		.C_OPTIMIZATION_MODE(0),
103		.C_OVERFLOW_LOW(0),
104		.C_PRELOAD_LATENCY(0),
105		.C_PRELOAD_REGS(1),
106		.C_PRIM_FIFO_TYPE("512x36"),
107		.C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
108		.C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
109		.C_PROG_EMPTY_TYPE(0),
110		.C_PROG_FULL_THRESH_ASSERT_VAL(511),
111		.C_PROG_FULL_THRESH_NEGATE_VAL(510),
112		.C_PROG_FULL_TYPE(0),
113		.C_RD_DATA_COUNT_WIDTH(10),
114		.C_RD_DEPTH(512),
115		.C_RD_FREQ(1),
116		.C_RD_PNTR_WIDTH(9),
117		.C_UNDERFLOW_LOW(0),
118		.C_USE_DOUT_RST(1),
119		.C_USE_ECC(0),
120		.C_USE_EMBEDDED_REG(0),
121		.C_USE_FIFO16_FLAGS(0),
122		.C_USE_FWFT_DATA_COUNT(1),
123		.C_VALID_LOW(0),
124		.C_WR_ACK_LOW(0),
125		.C_WR_DATA_COUNT_WIDTH(10),
126		.C_WR_DEPTH(512),
127		.C_WR_FREQ(1),
128		.C_WR_PNTR_WIDTH(9),
129		.C_WR_RESPONSE_LATENCY(1))
130	inst (
131		.RST(rst),
132		.WR_CLK(wr_clk),
133		.RD_CLK(rd_clk),
134		.DIN(din),
135		.WR_EN(wr_en),
136		.RD_EN(rd_en),
137		.DOUT(dout),
138		.FULL(full),
139		.EMPTY(empty),
140		.RD_DATA_COUNT(rd_data_count),
141		.WR_DATA_COUNT(wr_data_count),
142		.BACKUP(),
143		.BACKUP_MARKER(),
144		.CLK(),
145		.SRST(),
146		.WR_RST(),
147		.RD_RST(),
148		.PROG_EMPTY_THRESH(),
149		.PROG_EMPTY_THRESH_ASSERT(),
150		.PROG_EMPTY_THRESH_NEGATE(),
151		.PROG_FULL_THRESH(),
152		.PROG_FULL_THRESH_ASSERT(),
153		.PROG_FULL_THRESH_NEGATE(),
154		.INT_CLK(),
155		.INJECTDBITERR(),
156		.INJECTSBITERR(),
157		.ALMOST_FULL(),
158		.WR_ACK(),
159		.OVERFLOW(),
160		.ALMOST_EMPTY(),
161		.VALID(),
162		.UNDERFLOW(),
163		.DATA_COUNT(),
164		.PROG_FULL(),
165		.PROG_EMPTY(),
166		.SBITERR(),
167		.DBITERR());
168
169
170// synthesis translate_on
171
172endmodule
173
174