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XILINX EXPRESSLY DISCLAIMS ANY -- 16-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- 17-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- 18-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- 19-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- 20-- FOR A PARTICULAR PURPOSE. -- 21-- -- 22-- Xilinx products are not intended for use in life support -- 23-- appliances, devices, or systems. Use in such applications are -- 24-- expressly prohibited. -- 25-- -- 26-- (c) Copyright 1995-2007 Xilinx, Inc. -- 27-- All rights reserved. -- 28-------------------------------------------------------------------------------- 29-- You must compile the wrapper file fifo_xlnx_2Kx36_2clk.vhd when simulating 30-- the core, fifo_xlnx_2Kx36_2clk. When compiling the wrapper file, be sure to 31-- reference the XilinxCoreLib VHDL simulation library. For detailed 32-- instructions, please refer to the "CORE Generator Help". 33 34-- The synthesis directives "translate_off/translate_on" specified 35-- below are supported by Xilinx, Mentor Graphics and Synplicity 36-- synthesis tools. Ensure they are correct for your synthesis tool(s). 37 38LIBRARY ieee; 39USE ieee.std_logic_1164.ALL; 40-- synthesis translate_off 41Library XilinxCoreLib; 42-- synthesis translate_on 43ENTITY fifo_xlnx_2Kx36_2clk IS 44 port ( 45 din: IN std_logic_VECTOR(35 downto 0); 46 rd_clk: IN std_logic; 47 rd_en: IN std_logic; 48 rst: IN std_logic; 49 wr_clk: IN std_logic; 50 wr_en: IN std_logic; 51 dout: OUT std_logic_VECTOR(35 downto 0); 52 empty: OUT std_logic; 53 full: OUT std_logic; 54 rd_data_count: OUT std_logic_VECTOR(11 downto 0); 55 wr_data_count: OUT std_logic_VECTOR(11 downto 0)); 56END fifo_xlnx_2Kx36_2clk; 57 58ARCHITECTURE fifo_xlnx_2Kx36_2clk_a OF fifo_xlnx_2Kx36_2clk IS 59-- synthesis translate_off 60component wrapped_fifo_xlnx_2Kx36_2clk 61 port ( 62 din: IN std_logic_VECTOR(35 downto 0); 63 rd_clk: IN std_logic; 64 rd_en: IN std_logic; 65 rst: IN std_logic; 66 wr_clk: IN std_logic; 67 wr_en: IN std_logic; 68 dout: OUT std_logic_VECTOR(35 downto 0); 69 empty: OUT std_logic; 70 full: OUT std_logic; 71 rd_data_count: OUT std_logic_VECTOR(11 downto 0); 72 wr_data_count: OUT std_logic_VECTOR(11 downto 0)); 73end component; 74 75-- Configuration specification 76 for all : wrapped_fifo_xlnx_2Kx36_2clk use entity XilinxCoreLib.fifo_generator_v4_3(behavioral) 77 generic map( 78 c_has_int_clk => 0, 79 c_rd_freq => 1, 80 c_wr_response_latency => 1, 81 c_has_srst => 0, 82 c_has_rd_data_count => 1, 83 c_din_width => 36, 84 c_has_wr_data_count => 1, 85 c_full_flags_rst_val => 1, 86 c_implementation_type => 2, 87 c_family => "spartan3", 88 c_use_embedded_reg => 0, 89 c_has_wr_rst => 0, 90 c_wr_freq => 1, 91 c_use_dout_rst => 1, 92 c_underflow_low => 0, 93 c_has_meminit_file => 0, 94 c_has_overflow => 0, 95 c_preload_latency => 0, 96 c_dout_width => 36, 97 c_msgon_val => 1, 98 c_rd_depth => 2048, 99 c_default_value => "BlankString", 100 c_mif_file_name => "BlankString", 101 c_has_underflow => 0, 102 c_has_rd_rst => 0, 103 c_has_almost_full => 0, 104 c_has_rst => 1, 105 c_data_count_width => 12, 106 c_has_wr_ack => 0, 107 c_use_ecc => 0, 108 c_wr_ack_low => 0, 109 c_common_clock => 0, 110 c_rd_pntr_width => 11, 111 c_use_fwft_data_count => 1, 112 c_has_almost_empty => 0, 113 c_rd_data_count_width => 12, 114 c_enable_rlocs => 0, 115 c_wr_pntr_width => 11, 116 c_overflow_low => 0, 117 c_prog_empty_type => 0, 118 c_optimization_mode => 0, 119 c_wr_data_count_width => 12, 120 c_preload_regs => 1, 121 c_dout_rst_val => "0", 122 c_has_data_count => 0, 123 c_prog_full_thresh_negate_val => 2046, 124 c_wr_depth => 2048, 125 c_prog_empty_thresh_negate_val => 5, 126 c_prog_empty_thresh_assert_val => 4, 127 c_has_valid => 0, 128 c_init_wr_pntr_val => 0, 129 c_prog_full_thresh_assert_val => 2047, 130 c_use_fifo16_flags => 0, 131 c_has_backup => 0, 132 c_valid_low => 0, 133 c_prim_fifo_type => "2kx18", 134 c_count_type => 0, 135 c_prog_full_type => 0, 136 c_memory_type => 1); 137-- synthesis translate_on 138BEGIN 139-- synthesis translate_off 140U0 : wrapped_fifo_xlnx_2Kx36_2clk 141 port map ( 142 din => din, 143 rd_clk => rd_clk, 144 rd_en => rd_en, 145 rst => rst, 146 wr_clk => wr_clk, 147 wr_en => wr_en, 148 dout => dout, 149 empty => empty, 150 full => full, 151 rd_data_count => rd_data_count, 152 wr_data_count => wr_data_count); 153-- synthesis translate_on 154 155END fifo_xlnx_2Kx36_2clk_a; 156 157