1// 2// Copyright 2011 Ettus Research LLC 3// 4// This program is free software: you can redistribute it and/or modify 5// it under the terms of the GNU General Public License as published by 6// the Free Software Foundation, either version 3 of the License, or 7// (at your option) any later version. 8// 9// This program is distributed in the hope that it will be useful, 10// but WITHOUT ANY WARRANTY; without even the implied warranty of 11// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12// GNU General Public License for more details. 13// 14// You should have received a copy of the GNU General Public License 15// along with this program. If not, see <http://www.gnu.org/licenses/>. 16// 17 18 19module hb_tb(); 20 21 localparam SWIDTH = 17; 22 localparam CWIDTH = 18; 23 localparam TWIDTH = 20; 24 localparam ACC_WIDTH = 40; 25 26 reg clk = 0, rst = 1; 27 wire strobe_in, strobe_out; 28 reg [SWIDTH-1:0] sample_in; 29 wire signed [SWIDTH:0] sample_out; 30 31 reg set_stb; 32 reg [7:0] set_addr; 33 reg [31:0] set_data; 34 35 localparam DECIM = 3; 36 37 initial $dumpfile("hb_tb.vcd"); 38 initial $dumpvars(0,hb_tb); 39 40 always #5 clk <= ~clk; 41 initial 42 begin 43 @(posedge clk); 44 @(negedge clk); 45 rst <= 0; 46 end 47 48 reg [7:0] stb_counter; 49 always @(posedge clk) 50 if(rst) 51 stb_counter <= 0; 52 else 53 if(stb_counter == 0) 54 stb_counter <= DECIM; 55 else 56 stb_counter <= stb_counter - 1; 57 assign strobe_in = (stb_counter == 0); 58 59 hb_decim #(.SWIDTH(SWIDTH),.CWIDTH(CWIDTH), 60 .TWIDTH(TWIDTH),.ACC_WIDTH(ACC_WIDTH)) hb_decim 61 (.clk(clk), .rst(rst), 62 .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), 63 .sample_in(sample_in), 64 .strobe_in(strobe_in), 65 .sample_out(sample_out), 66 .strobe_out(strobe_out) 67 ); 68 69 initial 70 begin : load_coeffs 71 @(negedge rst); 72 @(posedge clk); 73 set_addr <= 124; // load coeffs 74 set_stb <= 1; 75 set_data <= -18'd49; 76 @(posedge clk); 77 set_data <= 18'd165; 78 @(posedge clk); 79 set_data <= -18'd412; 80 @(posedge clk); 81 set_data <= 18'd873; 82 @(posedge clk); 83 set_data <= -18'd1681; 84 @(posedge clk); 85 set_data <= 18'd3135; 86 @(posedge clk); 87 set_data <= -18'd6282; 88 @(posedge clk); 89 set_data <= 18'd20628; 90 @(posedge clk); 91 set_addr <=125; // load table 92 // { stb_out, accum, load_accum, done, even_addr, odd_addr_a, odd_addr_b, coeff_addr } 93 set_data <= {1'b1,1'b1,1'b0,1'b1,4'd15,4'd15,4'd0,4'd0}; // Phase 8 94 @(posedge clk); 95 set_data <= {1'b0,1'b1,1'b0,1'b0,4'd15,4'd14,4'd1,4'd1}; // Phase 7 96 @(posedge clk); 97 set_data <= {1'b0,1'b1,1'b0,1'b0,4'd15,4'd13,4'd2,4'd2}; // Phase 6 98 @(posedge clk); 99 set_data <= {1'b0,1'b1,1'b0,1'b0,4'd15,4'd12,4'd3,4'd3}; // Phase 5 100 @(posedge clk); 101 set_data <= {1'b0,1'b1,1'b0,1'b0,4'd15,4'd11,4'd4,4'd4}; // Phase 4 102 @(posedge clk); 103 set_data <= {1'b0,1'b1,1'b0,1'b0,4'd15,4'd10,4'd5,4'd5}; // Phase 3 104 @(posedge clk); 105 set_data <= {1'b0,1'b1,1'b0,1'b0,4'd15,4'd9,4'd6,4'd6}; // Phase 2 106 @(posedge clk); 107 set_data <= {1'b0,1'b0,1'b1,1'b0,4'd15,4'd8,4'd7,4'd7}; // Phase 1 108 @(posedge clk); 109 set_data <= {1'b0,1'b0,1'b0,1'b0,4'd15,4'd8,4'd7,4'd7}; // Phase 0 110 @(posedge clk); 111 set_stb <= 0; 112 end // block: load_coeffs 113 114 initial 115 begin 116 sample_in <= 0; 117 repeat(40) 118 @(posedge strobe_in); 119 $display("EVEN"); 120 sample_in <= 0; 121 repeat(10) 122 @(posedge strobe_in); 123 sample_in <= 1; 124 @(posedge strobe_in); 125 sample_in <= 0; 126 repeat(40) 127 @(posedge strobe_in); 128 sample_in <= 1; 129 repeat(40) 130 @(posedge strobe_in); 131 sample_in <= 0; 132 repeat(60) 133 @(posedge strobe_in); 134 sample_in <= 1; 135 repeat(2) 136 @(posedge strobe_in); 137 sample_in <= 0; 138 repeat(60) 139 @(posedge strobe_in); 140 $display("ODD"); 141 sample_in <= 0; 142 repeat(10) 143 @(posedge strobe_in); 144 sample_in <= 1; 145 @(posedge strobe_in); 146 sample_in <= 0; 147 repeat(40) 148 @(posedge strobe_in); 149 sample_in <= 1; 150 repeat(40) 151 @(posedge strobe_in); 152 sample_in <= 0; 153 repeat(60) 154 @(posedge strobe_in); 155 sample_in <= 1; 156 repeat(2) 157 @(posedge strobe_in); 158 sample_in <= 0; 159 repeat(60) 160 @(posedge strobe_in); 161 $finish; 162 end 163 164 always @(posedge clk) 165 if(strobe_in) 166 $display(sample_in); 167 168 always @(posedge clk) 169 if(strobe_out) 170 $display("\t",sample_out); 171 172endmodule // hb_tb 173