1
2module rx_frontend
3  #(parameter BASE = 0,
4    parameter IQCOMP_EN = 1)
5   (input clk, input rst,
6    input set_stb, input [7:0] set_addr, input [31:0] set_data,
7
8    input [15:0] adc_a, input adc_ovf_a,
9    input [15:0] adc_b, input adc_ovf_b,
10
11    output [23:0] i_out, output [23:0] q_out,
12    input run,
13    output [31:0] debug
14    );
15
16   reg [15:0] 	  adc_i, adc_q;
17   wire [17:0] 	  adc_i_ofs, adc_q_ofs;
18   wire [35:0] 	  corr_i, corr_q; wire [17:0] 	  mag_corr,phase_corr;
19   wire 	  swap_iq;
20
21   setting_reg #(.my_addr(BASE), .width(1)) sr_8
22     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
23      .in(set_data),.out(swap_iq),.changed());
24
25   always @(posedge clk)
26     if(swap_iq) // Swap
27       {adc_i,adc_q} <= {adc_b,adc_a};
28     else
29       {adc_i,adc_q} <= {adc_a,adc_b};
30
31   setting_reg #(.my_addr(BASE+1),.width(18)) sr_1
32     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
33      .in(set_data),.out(mag_corr),.changed());
34
35   setting_reg #(.my_addr(BASE+2),.width(18)) sr_2
36     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
37      .in(set_data),.out(phase_corr),.changed());
38
39   generate
40      if(IQCOMP_EN == 1)
41	begin
42	   reg [17:0] adc_i_ofs_dly, adc_q_ofs_dly;
43	   always @(posedge clk) begin
44	     adc_i_ofs_dly <= adc_i_ofs;
45	     adc_q_ofs_dly <= adc_q_ofs;
46	   end
47
48	   rx_dcoffset #(.WIDTH(18),.ADDR(BASE+3)) rx_dcoffset_i
49	     (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
50	      .in({adc_i,2'b00}),.out(adc_i_ofs));
51
52	   rx_dcoffset #(.WIDTH(18),.ADDR(BASE+4)) rx_dcoffset_q
53	     (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
54	      .in({adc_q,2'b00}),.out(adc_q_ofs));
55
56	   MULT18X18S mult_mag_corr
57	     (.P(corr_i), .A(adc_i_ofs), .B(mag_corr), .C(clk), .CE(1), .R(rst) );
58
59	   MULT18X18S mult_phase_corr
60	     (.P(corr_q), .A(adc_i_ofs), .B(phase_corr), .C(clk), .CE(1), .R(rst) );
61
62	   add2_and_clip_reg #(.WIDTH(24)) add_clip_i
63	     (.clk(clk), .rst(rst),
64	      .in1({adc_i_ofs_dly,6'd0}), .in2(corr_i[35:12]), .strobe_in(1'b1),
65	      .sum(i_out), .strobe_out());
66
67	   add2_and_clip_reg #(.WIDTH(24)) add_clip_q
68	     (.clk(clk), .rst(rst),
69	      .in1({adc_q_ofs_dly,6'd0}), .in2(corr_q[35:12]), .strobe_in(1'b1),
70	      .sum(q_out), .strobe_out());
71	end // if (IQCOMP_EN == 1)
72      else
73	begin
74	   rx_dcoffset #(.WIDTH(24),.ADDR(BASE+3)) rx_dcoffset_i
75	     (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
76	      .in({adc_i,8'b00}),.out(i_out));
77
78	   rx_dcoffset #(.WIDTH(24),.ADDR(BASE+4)) rx_dcoffset_q
79	     (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
80	      .in({adc_q,8'b00}),.out(q_out));
81	end // else: !if(IQCOMP_EN == 1)
82      endgenerate
83
84endmodule // rx_frontend
85