1// 2// Copyright 2011 Ettus Research LLC 3// 4// This program is free software: you can redistribute it and/or modify 5// it under the terms of the GNU General Public License as published by 6// the Free Software Foundation, either version 3 of the License, or 7// (at your option) any later version. 8// 9// This program is distributed in the hope that it will be useful, 10// but WITHOUT ANY WARRANTY; without even the implied warranty of 11// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12// GNU General Public License for more details. 13// 14// You should have received a copy of the GNU General Public License 15// along with this program. If not, see <http://www.gnu.org/licenses/>. 16// 17 18// Short halfband decimator (intended to be followed by another stage) 19// Implements impulse responses of the form [A 0 B 0.5 B 0 A] 20// 21// These taps designed by halfgen4 from ldoolittle: 22// 2 * 131072 * halfgen4(.75/8,2) 23 24module small_hb_int 25 #(parameter WIDTH=18) 26 (input clk, 27 input rst, 28 input bypass, 29 input stb_in, 30 input [WIDTH-1:0] data_in, 31 input [7:0] output_rate, 32 input stb_out, 33 output reg [WIDTH-1:0] data_out); 34 35 reg phase; 36 reg [WIDTH-1:0] d1, d2, d3, d4, d5, d6; 37 38 localparam MWIDTH = 36; 39 wire [MWIDTH-1:0] prod; 40 41 reg [6:0] stbin_d; 42 43 always @(posedge clk) 44 stbin_d <= {stbin_d[5:0],stb_in}; 45 46 always @(posedge clk) 47 if(stb_in) 48 begin 49 d1 <= data_in; 50 d2 <= d1; 51 d3 <= d2; 52 d4 <= d3; 53 d5 <= d4; 54 d6 <= d5; 55 end 56 57 wire [WIDTH-1:0] sum_outer, sum_inner; 58 add2_and_round_reg #(.WIDTH(WIDTH)) add_outer (.clk(clk),.in1(d1),.in2(d4),.sum(sum_outer)); 59 add2_and_round_reg #(.WIDTH(WIDTH)) add_inner (.clk(clk),.in1(d2),.in2(d3),.sum(sum_inner)); 60 61 wire [17:0] coeff_outer = -10690; 62 wire [17:0] coeff_inner = 75809; 63 64 MULT18X18S mult(.C(clk), .CE(1), .R(rst), .P(prod), .A(stbin_d[1] ? coeff_outer : coeff_inner), 65 .B(stbin_d[1] ? sum_outer : sum_inner) ); 66 67 wire [MWIDTH:0] accum; 68 acc #(.IWIDTH(MWIDTH),.OWIDTH(MWIDTH+1)) 69 acc (.clk(clk),.clear(stbin_d[2]),.acc(|stbin_d[3:2]),.in(prod),.out(accum)); 70 71 wire [WIDTH+2:0] accum_rnd; 72 round_reg #(.bits_in(MWIDTH+1),.bits_out(WIDTH+3)) 73 final_round (.clk(clk),.in(accum),.out(accum_rnd)); 74 75 wire [WIDTH-1:0] clipped; 76 clip_reg #(.bits_in(WIDTH+3),.bits_out(WIDTH)) final_clip 77 (.clk(clk),.in(accum_rnd),.strobe_in(1'b1), .out(clipped)); 78 79 reg [WIDTH-1:0] saved, saved_d3; 80 always @(posedge clk) 81 if(stbin_d[6]) 82 saved <= clipped; 83 84 always @(posedge clk) 85 if(stbin_d[3]) 86 saved_d3 <= d3; 87 88 always @(posedge clk) 89 if(bypass) 90 data_out <= data_in; 91 else if(stb_in & stb_out) 92 case(output_rate) 93 1 : data_out <= d6; 94 2 : data_out <= d4; 95 3, 4, 5, 6, 7 : data_out <= d3; 96 default : data_out <= d2; 97 endcase // case(output_rate) 98 else if(stb_out) 99 data_out <= saved; 100 101endmodule // small_hb_int 102 103