1// 2// Copyright 2014 Ettus Research LLC 3// Copyright 2018 Ettus Research, a National Instruments Company 4// 5// SPDX-License-Identifier: LGPL-3.0-or-later 6// 7 8module add2_and_clip_reg 9 #(parameter WIDTH=16) 10 (input clk, 11 input rst, 12 input [WIDTH-1:0] in1, 13 input [WIDTH-1:0] in2, 14 input strobe_in, 15 output reg [WIDTH-1:0] sum, 16 output reg strobe_out); 17 18 wire [WIDTH-1:0] sum_int; 19 20 add2_and_clip #(.WIDTH(WIDTH)) add2_and_clip (.in1(in1),.in2(in2),.sum(sum_int)); 21 22 always @(posedge clk) 23 if(rst) 24 sum <= 0; 25 else if(strobe_in) 26 sum <= sum_int; 27 28 always @(posedge clk) strobe_out <= rst ? 1'b0 : strobe_in; 29 30endmodule // add2_and_clip_reg 31