1// 2// Copyright 2011 Ettus Research LLC 3// Copyright 2018 Ettus Research, a National Instruments Company 4// 5// SPDX-License-Identifier: LGPL-3.0-or-later 6// 7// This program is free software: you can redistribute it and/or modify 8// it under the terms of the GNU General Public License as published by 9// the Free Software Foundation, either version 3 of the License, or 10// (at your option) any later version. 11// 12// This program is distributed in the hope that it will be useful, 13// but WITHOUT ANY WARRANTY; without even the implied warranty of 14// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15// GNU General Public License for more details. 16// 17// You should have received a copy of the GNU General Public License 18// along with this program. If not, see <http://www.gnu.org/licenses/>. 19// 20 21// 22// EMI mitigation. 23// Process FULL flag from FIFO so that de-assertion 24// (FIFO now not FULL) is delayed by a pseudo random 25// value, but assertion is passed straight through. 26// 27 28 29module refill_randomizer 30 #(parameter BITS=7) 31 ( 32 input clk, 33 input rst, 34 input full_in, 35 output full_out 36 ); 37 38 wire feedback; 39 reg full_last; 40 wire full_deasserts; 41 reg [6:0] shift_reg; 42 reg [6:0] count; 43 reg delayed_fall; 44 45 46 always @(posedge clk) 47 full_last <= full_in; 48 49 assign full_deasserts = full_last & ~full_in; 50 51 // 7 bit LFSR 52 always @(posedge clk) 53 if (rst) 54 shift_reg <= 7'b1; 55 else 56 if (full_deasserts) 57 shift_reg <= {shift_reg[5:0],feedback}; 58 59 assign feedback = ^(shift_reg & 7'h41); 60 61 always @(posedge clk) 62 if (rst) 63 begin 64 count <= 1; 65 delayed_fall <= 1; 66 end 67 else if (full_deasserts) 68 begin 69 count <= shift_reg; 70 delayed_fall <= 1; 71 end 72 else if (count == 1) 73 begin 74 count <= 1; 75 delayed_fall <= 0; 76 end 77 else 78 begin 79 count <= count - 1; 80 delayed_fall <= 1; 81 end 82 83 // Full_out goes instantly high if full_in does. However its fall is delayed. 84 assign full_out = (full_in == 1) || (full_last == 1) || delayed_fall; 85 86endmodule