1///////////////////////////////////////////////////////////////////// 2// 3// Copyright 2016-2017 Ettus Research 4// Copyright 2018 Ettus Research, a National Instruments Company 5// 6// SPDX-License-Identifier: LGPL-3.0-or-later 7// 8////////////////////////////////////////////////////////////////////// 9 10module fifo64_to_axi4lite 11( 12 input s_axi_aclk, 13 input s_axi_areset, 14 15 input [31:0] s_axi_awaddr, 16 input s_axi_awvalid, 17 output s_axi_awready, 18 input [31:0] s_axi_wdata, 19 input [3:0] s_axi_wstrb, 20 input s_axi_wvalid, 21 output s_axi_wready, 22 output [1:0] s_axi_bresp, 23 output s_axi_bvalid, 24 input s_axi_bready, 25 input [31:0] s_axi_araddr, 26 input s_axi_arvalid, 27 output s_axi_arready, 28 output [31:0] s_axi_rdata, 29 output [1:0] s_axi_rresp, 30 output s_axi_rvalid, 31 input s_axi_rready, 32 33 output m_axis_tvalid, 34 output m_axis_tlast, 35 output [63:0] m_axis_tdata, 36 input m_axis_tready, 37 output [3:0] m_axis_tuser, 38 39 input s_axis_tvalid, 40 input s_axis_tlast, 41 input [63:0] s_axis_tdata, 42 output s_axis_tready, 43 input [3:0] s_axis_tuser, 44 output irq 45); 46 47 wire clear_txn; 48 wire [31:0] tx_tdata; 49 wire tx_tlast; 50 wire tx_tvalid; 51 wire tx_tready; 52 wire [3:0] tx_tkeep; 53 wire [1:0] tx_tuser = (tx_tkeep == 4'b1111) ? 2'd0 : 54 (tx_tkeep == 4'b0001) ? 2'd1 : 55 (tx_tkeep == 4'b0011) ? 2'd2 : 56 (tx_tkeep == 4'b0111) ? 2'd3 : 2'd0; 57 58 axi_fifo32_to_fifo64 inst_axi_fifo32_to_fifo64 59 ( 60 .clk(s_axi_aclk), 61 .reset(s_axi_areset | ~clear_txn), 62 .i_tdata({tx_tdata[7:0], tx_tdata[15:8], tx_tdata[23:16], tx_tdata[31:24]}), // endian swap 63 .i_tuser(tx_tuser), 64 .i_tlast(tx_tlast), 65 .i_tvalid(tx_tvalid), 66 .i_tready(tx_tready), 67 .o_tdata(m_axis_tdata), 68 .o_tuser(m_axis_tuser), 69 .o_tlast(m_axis_tlast), 70 .o_tvalid(m_axis_tvalid), 71 .o_tready(m_axis_tready) 72 ); 73 74 75 wire clear_rxn; 76 wire [31:0] rx_tdata; 77 wire rx_tlast; 78 wire rx_tvalid; 79 wire rx_tready; 80 wire [1:0] rx_tuser; 81 82 axi_fifo64_to_fifo32 inst_axi_fifo64_to_fifo32 83 ( 84 .clk(s_axi_aclk), 85 .reset(s_axi_areset || ~clear_rxn), 86 .i_tdata(s_axis_tdata), 87 .i_tuser(s_axis_tuser[2:0]), 88 .i_tlast(s_axis_tlast), 89 .i_tvalid(s_axis_tvalid), 90 .i_tready(s_axis_tready), 91 .o_tdata({rx_tdata[7:0], rx_tdata[15:8], rx_tdata[23:16], rx_tdata[31:24]}), // endian swap 92 .o_tuser(rx_tuser), 93 .o_tlast(rx_tlast), 94 .o_tvalid(rx_tvalid), 95 .o_tready(rx_tready) 96 ); 97 98 wire [3:0] rx_tkeep = ~rx_tlast ? 4'b1111 : (rx_tuser == 2'd0) ? 4'b1111 : 99 (rx_tuser == 2'd1) ? 4'b0001 : 100 (rx_tuser == 2'd2) ? 4'b0011 : 101 (rx_tuser == 2'd3) ? 4'b0111 : 102 4'b1111; 103 104 axis_fifo_to_axi4lite inst_axis_fifo_to_axi4lite0 105 ( 106 .interrupt(irq), 107 .s_axi_aclk(s_axi_aclk), 108 .s_axi_aresetn(~s_axi_areset), 109 .s_axi_awaddr({16'h0000, s_axi_awaddr}), 110 .s_axi_awvalid(s_axi_awvalid), 111 .s_axi_awready(s_axi_awready), 112 .s_axi_wdata(s_axi_wdata), 113 .s_axi_wstrb(s_axi_wstrb), 114 .s_axi_wvalid(s_axi_wvalid), 115 .s_axi_wready(s_axi_wready), 116 .s_axi_bresp(s_axi_bresp), 117 .s_axi_bvalid(s_axi_bvalid), 118 .s_axi_bready(s_axi_bready), 119 .s_axi_araddr({16'h0000, s_axi_araddr}), 120 .s_axi_arvalid(s_axi_arvalid), 121 .s_axi_arready(s_axi_arready), 122 .s_axi_rdata(s_axi_rdata), 123 .s_axi_rresp(s_axi_rresp), 124 .s_axi_rvalid(s_axi_rvalid), 125 .s_axi_rready(s_axi_rready), 126 .mm2s_prmry_reset_out_n(clear_txn), 127 .axi_str_txd_tvalid(tx_tvalid), 128 .axi_str_txd_tready(tx_tready), 129 .axi_str_txd_tlast(tx_tlast), 130 .axi_str_txd_tdata(tx_tdata), 131 .axi_str_txd_tkeep(tx_tkeep), 132 .s2mm_prmry_reset_out_n(clear_rxn), 133 .axi_str_rxd_tvalid(rx_tvalid), 134 .axi_str_rxd_tready(rx_tready), 135 .axi_str_rxd_tlast(rx_tlast), 136 .axi_str_rxd_tdata(rx_tdata), 137 .axi_str_rxd_tkeep(rx_tkeep) 138); 139 140endmodule 141