1// 2// Copyright 2014 Ettus Research LLC 3// Copyright 2018 Ettus Research, a National Instruments Company 4// 5// SPDX-License-Identifier: LGPL-3.0-or-later 6// 7// This delay doesn't use a fifo, and solves pipeline bubble issues. 8// FIXME -- issues are that it will generate output without input, and you can't reduce delay, only increase 9 10module delay_type2 11 #(parameter MAX_LEN_LOG2=10, 12 parameter WIDTH=16, 13 parameter DELAY_VAL=0) 14 (input clk, input reset, input clear, 15 input [MAX_LEN_LOG2-1:0] len, 16 input [WIDTH-1:0] i_tdata, input i_tlast, input i_tvalid, output i_tready, 17 output [WIDTH-1:0] o_tdata, output o_tlast, output o_tvalid, input o_tready); 18 19 reg [MAX_LEN_LOG2-1:0] delay_count; 20 21 wire delay_done = delay_count >= len; 22 23 always @(posedge clk) 24 if(reset) 25 delay_count <= 0; 26 else 27 if(~delay_done & o_tvalid & o_tready) 28 delay_count <= delay_count + 1; 29 30 assign o_tdata = delay_done ? i_tdata : DELAY_VAL; 31 assign o_tlast = delay_done ? i_tlast : 1'b0; // FIXME think about this more, no answer is perfect in all situations 32 assign o_tvalid = delay_done ? i_tvalid : 1'b1; 33 assign i_tready = delay_done ? o_tready : 1'b0; 34 35endmodule // delay_type2 36