1/* 2 * f15_avg.v 3 * 4 * Applies the y(t+1) = alpha * y(t) + (1 - alpha) * x(t) 5 * to compute an IIR average 6 * 7 * Copyright (C) 2015 Ettus Corporation LLC 8 * Copyright 2018 Ettus Research, a National Instruments Company 9 * 10 * SPDX-License-Identifier: LGPL-3.0-or-later 11 * 12 * vim: ts=4 sw=4 13 */ 14 15`ifdef SIM 16`default_nettype none 17`endif 18 19module f15_avg #( 20 parameter integer Y_WIDTH = 12, 21 parameter integer X_WIDTH = 16 22)( 23 input wire [Y_WIDTH-1:0] yin_0, 24 input wire [X_WIDTH-1:0] x_0, 25 input wire [15:0] rng_0, 26 input wire [15:0] alpha_0, 27 input wire clear_0, 28 output wire [Y_WIDTH-1:0] yout_4, 29 input wire clk, 30 input wire rst 31); 32 33 // Signals 34 wire [X_WIDTH-1:0] x_2; 35 wire clear_3; 36 wire [47:0] pout_4; 37 38 // Main DSP Instance 39 DSP48E1 #( 40 .A_INPUT("DIRECT"), 41 .B_INPUT("DIRECT"), 42 .USE_DPORT("TRUE"), 43 .USE_MULT("MULTIPLY"), 44 .AUTORESET_PATDET("NO_RESET"), 45 .MASK(48'h3fffffffffff), 46 .PATTERN(48'h000000000000), 47 .SEL_MASK("MASK"), 48 .SEL_PATTERN("PATTERN"), 49 .USE_PATTERN_DETECT("PATDET"), 50 .ACASCREG(1), 51 .ADREG(1), 52 .ALUMODEREG(1), 53 .AREG(1), 54 .BCASCREG(1), 55 .BREG(2), 56 .CARRYINREG(1), 57 .CARRYINSELREG(1), 58 .CREG(1), 59 .DREG(1), 60 .INMODEREG(1), 61 .MREG(1), 62 .OPMODEREG(1), 63 .PREG(1), 64 .USE_SIMD("ONE48") 65 ) 66 dsp_avg_I ( 67 .P(pout_4), 68 .ACIN(30'h0), 69 .BCIN(18'h0), 70 .CARRYCASCIN(1'h0), 71 .MULTSIGNIN(1'h0), 72 .PCIN(48'h000000000000), 73 .ALUMODE(4'b0000), // Z + X + Y + CIN 74 .CARRYINSEL(3'h0), 75 .CEINMODE(1'b1), 76 .CLK(clk), 77 .INMODE(5'b01100), // B=B2, A=D-A2 78 .OPMODE(7'b0110101), // X=M1, Y=M2, Z=C 79 .RSTINMODE(rst), 80 .A({{(30-X_WIDTH){1'b0}}, x_0}), 81 .B({2'h0, alpha_0}), 82 .C({{(32-X_WIDTH){1'b0}}, x_2, 16'h8000}), 83 .CARRYIN(1'b0), 84 .D({{(25-X_WIDTH){1'b0}}, yin_0, rng_0[X_WIDTH-Y_WIDTH-1:0]}), 85 .CEA1(1'b0), 86 .CEA2(1'b1), 87 .CEAD(1'b1), 88 .CEALUMODE(1'b1), 89 .CEB1(1'b1), 90 .CEB2(1'b1), 91 .CEC(1'b1), 92 .CECARRYIN(1'b1), 93 .CECTRL(1'b1), 94 .CED(1'b1), 95 .CEM(1'b1), 96 .CEP(1'b1), 97 .RSTA(rst), 98 .RSTALLCARRYIN(rst), 99 .RSTALUMODE(rst), 100 .RSTB(rst), 101 .RSTC(rst), 102 .RSTCTRL(rst), 103 .RSTD(rst), 104 .RSTM(rst), 105 .RSTP(clear_3) 106 ); 107 108 // Delay x for the C input 109 delay_bus #(2, X_WIDTH) dl_x (x_0, x_2, clk); 110 111 // Delay clear to use as reset for P 112 delay_bit #(3) dl_clear (clear_0, clear_3, clk); 113 114 // Map the output 115 assign yout_4 = pout_4[X_WIDTH+15:X_WIDTH-Y_WIDTH+16]; 116 117endmodule // f15_avg 118