1// 2// Copyright 2011-2012 Ettus Research LLC 3// Copyright 2018 Ettus Research, a National Instruments Company 4// 5// SPDX-License-Identifier: LGPL-3.0-or-later 6// 7 8 9// 10// Use this module in conjunction with settings_bus.v to add stateful reads 11// to the settings bis. This enables you to do things like have registers reset atomicly 12// as they are read. It also pipelines the address path to ease timing. 13// 14 15module settings_readback 16 #(parameter AWIDTH=16, parameter DWIDTH=32, parameter RB_ADDRW=2) 17 ( 18 input wb_clk, 19 input wb_rst, 20 input [AWIDTH-1:0] wb_adr_i, 21 input wb_stb_i, 22 input wb_we_i, 23 input [DWIDTH-1:0] rb_data, 24 output reg [RB_ADDRW-1:0] rb_addr, 25 output [DWIDTH-1:0] wb_dat_o, 26 output reg rb_rd_stb 27 ); 28 29 always @(posedge wb_clk) 30 if (wb_stb_i && ~wb_we_i) begin 31 rb_addr <= wb_adr_i[RB_ADDRW+1:2]; 32 rb_rd_stb <= 1'b1; 33 end else begin 34 rb_rd_stb <= 1'b0; 35 end 36 37 assign wb_dat_o = rb_data; 38 39 40 41endmodule // settings_readback 42 43