1//////////////////////////////////////////////////////////////////////
2////                                                              ////
3////  File name "generic_fifo.v"                                  ////
4////                                                              ////
5////  This file is part of the "10GE MAC" project                 ////
6////  http://www.opencores.org/cores/xge_mac/                     ////
7////                                                              ////
8////  Author(s):                                                  ////
9////      - A. Tanguay (antanguay@opencores.org)                  ////
10////                                                              ////
11//////////////////////////////////////////////////////////////////////
12////                                                              ////
13//// Copyright (C) 2008 AUTHORS. All rights reserved.             ////
14////                                                              ////
15//// This source file may be used and distributed without         ////
16//// restriction provided that this copyright statement is not    ////
17//// removed from the file and that any derivative work contains  ////
18//// the original copyright notice and the associated disclaimer. ////
19////                                                              ////
20//// This source file is free software; you can redistribute it   ////
21//// and/or modify it under the terms of the GNU Lesser General   ////
22//// Public License as published by the Free Software Foundation; ////
23//// either version 2.1 of the License, or (at your option) any   ////
24//// later version.                                               ////
25////                                                              ////
26//// This source is distributed in the hope that it will be       ////
27//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
28//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
29//// PURPOSE.  See the GNU Lesser General Public License for more ////
30//// details.                                                     ////
31////                                                              ////
32//// You should have received a copy of the GNU Lesser General    ////
33//// Public License along with this source; if not, download it   ////
34//// from http://www.opencores.org/lgpl.shtml                     ////
35////                                                              ////
36//////////////////////////////////////////////////////////////////////
37
38`include "defines.v"
39
40module generic_fifo(
41
42    wclk,
43    wrst_n,
44    wen,
45    wdata,
46    wfull,
47    walmost_full,
48
49    rclk,
50    rrst_n,
51    ren,
52    rdata,
53    rempty,
54    ralmost_empty
55);
56
57//---
58// Parameters
59
60parameter DWIDTH = 32;
61parameter AWIDTH = 3;
62parameter RAM_DEPTH = (1 << AWIDTH);
63parameter SYNC_WRITE = 1;
64parameter SYNC_READ = 1;
65parameter REGISTER_READ = 0;
66parameter EARLY_READ = 0;
67parameter CLOCK_CROSSING = 1;
68parameter ALMOST_EMPTY_THRESH = 1;
69parameter ALMOST_FULL_THRESH = RAM_DEPTH-2;
70parameter MEM_TYPE = `MEM_AUTO_SMALL;
71
72//---
73// Ports
74
75input          wclk;
76input          wrst_n;
77input          wen;
78input  [DWIDTH-1:0] wdata;
79output         wfull;
80output         walmost_full;
81
82input          rclk;
83input          rrst_n;
84input          ren;
85output [DWIDTH-1:0] rdata;
86output         rempty;
87output         ralmost_empty;
88
89// Wires
90
91wire             mem_wen;
92wire [AWIDTH:0]  mem_waddr;
93
94wire             mem_ren;
95wire [AWIDTH:0]  mem_raddr;
96
97
98generic_fifo_ctrl #(.AWIDTH (AWIDTH),
99                    .RAM_DEPTH (RAM_DEPTH),
100                    .EARLY_READ (EARLY_READ),
101                    .CLOCK_CROSSING (CLOCK_CROSSING),
102                    .ALMOST_EMPTY_THRESH (ALMOST_EMPTY_THRESH),
103                    .ALMOST_FULL_THRESH (ALMOST_FULL_THRESH)
104                    )
105  ctrl0(.wclk (wclk),
106        .wrst_n (wrst_n),
107        .wen (wen),
108        .wfull (wfull),
109        .walmost_full (walmost_full),
110
111        .mem_wen (mem_wen),
112        .mem_waddr (mem_waddr),
113
114        .rclk (rclk),
115        .rrst_n (rrst_n),
116        .ren (ren),
117        .rempty (rempty),
118        .ralmost_empty (ralmost_empty),
119
120        .mem_ren (mem_ren),
121        .mem_raddr (mem_raddr)
122        );
123
124
125   generate
126      if (MEM_TYPE == `MEM_AUTO_SMALL) begin
127
128         generic_mem_small #(.DWIDTH (DWIDTH),
129                             .AWIDTH (AWIDTH),
130                             .RAM_DEPTH (RAM_DEPTH),
131                             .SYNC_WRITE (SYNC_WRITE),
132                             .SYNC_READ (SYNC_READ),
133                             .REGISTER_READ (REGISTER_READ)
134                             )
135           mem0(.wclk (wclk),
136		.wrst_n (wrst_n),
137		.wen (mem_wen),
138		.waddr (mem_waddr),
139		.wdata (wdata),
140
141		.rclk (rclk),
142		.rrst_n (rrst_n),
143		.ren (mem_ren),
144		.roen (ren),
145		.raddr (mem_raddr),
146		.rdata (rdata)
147		);
148
149      end
150
151      if (MEM_TYPE == `MEM_AUTO_MEDIUM) begin
152
153         generic_mem_medium #(.DWIDTH (DWIDTH),
154                              .AWIDTH (AWIDTH),
155                              .RAM_DEPTH (RAM_DEPTH),
156                              .SYNC_WRITE (SYNC_WRITE),
157                              .SYNC_READ (SYNC_READ),
158                              .REGISTER_READ (REGISTER_READ)
159                              )
160           mem0(.wclk (wclk),
161		.wrst_n (wrst_n),
162		.wen (mem_wen),
163		.waddr (mem_waddr),
164		.wdata (wdata),
165
166		.rclk (rclk),
167		.rrst_n (rrst_n),
168		.ren (mem_ren),
169		.roen (ren),
170		.raddr (mem_raddr),
171		.rdata (rdata)
172		);
173
174      end // if (MEM_TYPE == `MEM_AUTO_MEDIUM)
175
176      if (MEM_TYPE == `MEM_AUTO_XILINX) begin
177
178
179	 generic_mem_xilinx_block #(.DWIDTH (DWIDTH),
180				    .AWIDTH (AWIDTH),
181				    .RAM_DEPTH (RAM_DEPTH),
182				    .SYNC_WRITE (SYNC_WRITE),
183				    .SYNC_READ (SYNC_READ),
184				    .REGISTER_READ (REGISTER_READ)
185				    )
186           mem0(.wclk (wclk),
187		.wrst_n (wrst_n),
188		.wen (mem_wen),
189		.waddr (mem_waddr),
190		.wdata (wdata),
191
192		.rclk (rclk),
193		.rrst_n (rrst_n),
194		.ren (mem_ren),
195		.roen (ren),
196		.raddr (mem_raddr),
197		.rdata (rdata)
198		);
199      end
200
201   endgenerate
202
203endmodule
204
205