1////////////////////////////////////////////////////////////////////// 2//// //// 3//// File name "xge_mac_wb.v" //// 4//// //// 5//// This file is part of the "10GE MAC" project //// 6//// http://www.opencores.org/cores/xge_mac/ //// 7//// //// 8//// Author(s): //// 9//// - A. Tanguay (antanguay@opencores.org) //// 10//// //// 11////////////////////////////////////////////////////////////////////// 12//// //// 13//// Copyright (C) 2008 AUTHORS. All rights reserved. //// 14//// //// 15//// This source file may be used and distributed without //// 16//// restriction provided that this copyright statement is not //// 17//// removed from the file and that any derivative work contains //// 18//// the original copyright notice and the associated disclaimer. //// 19//// //// 20//// This source file is free software; you can redistribute it //// 21//// and/or modify it under the terms of the GNU Lesser General //// 22//// Public License as published by the Free Software Foundation; //// 23//// either version 2.1 of the License, or (at your option) any //// 24//// later version. //// 25//// //// 26//// This source is distributed in the hope that it will be //// 27//// useful, but WITHOUT ANY WARRANTY; without even the implied //// 28//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 29//// PURPOSE. See the GNU Lesser General Public License for more //// 30//// details. //// 31//// //// 32//// You should have received a copy of the GNU Lesser General //// 33//// Public License along with this source; if not, download it //// 34//// from http://www.opencores.org/lgpl.shtml //// 35//// //// 36////////////////////////////////////////////////////////////////////// 37 38 39module xge_mac_wb ( 40 // Outputs 41 xgmii_txd, xgmii_txc, pkt_tx_full, 42 pkt_rx_val, pkt_rx_sop, pkt_rx_mod, pkt_rx_err, pkt_rx_eop, 43 pkt_rx_data, pkt_rx_avail, 44 wb_int_o, wb_dat_o, wb_ack_o, 45 mdc, mdio_out, mdio_tri, xge_gpo, 46 47 // Inputs 48 xgmii_rxd, xgmii_rxc, 49 wb_we_i, wb_stb_i, wb_rst_i, wb_dat_i, 50 wb_cyc_i, wb_clk_i, wb_adr_i, 51 reset_xgmii_tx_n, reset_xgmii_rx_n, reset_156m25_n, 52 pkt_tx_val, pkt_tx_sop, pkt_tx_mod, pkt_tx_eop, 53 pkt_tx_data, pkt_rx_ren, 54 clk_xgmii_tx, clk_xgmii_rx, clk_156m25, 55 mdio_in, xge_gpi 56); 57 58 input clk_156m25; // To rx_dq0 of rx_dequeue.v, ... 59 input clk_xgmii_rx; // To rx_eq0 of rx_enqueue.v, ... 60 input clk_xgmii_tx; // To tx_dq0 of tx_dequeue.v, ... 61 input pkt_rx_ren; // To rx_dq0 of rx_dequeue.v 62 input [63:0] pkt_tx_data; // To tx_eq0 of tx_enqueue.v 63 input pkt_tx_eop; // To tx_eq0 of tx_enqueue.v 64 input [2:0] pkt_tx_mod; // To tx_eq0 of tx_enqueue.v 65 input pkt_tx_sop; // To tx_eq0 of tx_enqueue.v 66 input pkt_tx_val; // To tx_eq0 of tx_enqueue.v 67 input reset_156m25_n; // To rx_dq0 of rx_dequeue.v, ... 68 input reset_xgmii_rx_n; // To rx_eq0 of rx_enqueue.v, ... 69 input reset_xgmii_tx_n; // To tx_dq0 of tx_dequeue.v, ... 70 input [7:0] wb_adr_i; // To wishbone_if0 of wishbone_if.v 71 input wb_clk_i; // To sync_clk_wb0 of sync_clk_wb.v, ... 72 input wb_cyc_i; // To wishbone_if0 of wishbone_if.v 73 input [31:0] wb_dat_i; // To wishbone_if0 of wishbone_if.v 74 input wb_rst_i; // To sync_clk_wb0 of sync_clk_wb.v, ... 75 input wb_stb_i; // To wishbone_if0 of wishbone_if.v 76 input wb_we_i; // To wishbone_if0 of wishbone_if.v 77 input [7:0] xgmii_rxc; // To rx_eq0 of rx_enqueue.v 78 input [63:0] xgmii_rxd; // To rx_eq0 of rx_enqueue.v 79 input mdio_in; 80 input [7:0] xge_gpi; 81 82 output pkt_rx_avail; // From rx_dq0 of rx_dequeue.v 83 output [63:0] pkt_rx_data; // From rx_dq0 of rx_dequeue.v 84 output pkt_rx_eop; // From rx_dq0 of rx_dequeue.v 85 output pkt_rx_err; // From rx_dq0 of rx_dequeue.v 86 output [2:0] pkt_rx_mod; // From rx_dq0 of rx_dequeue.v 87 output pkt_rx_sop; // From rx_dq0 of rx_dequeue.v 88 output pkt_rx_val; // From rx_dq0 of rx_dequeue.v 89 output pkt_tx_full; // From tx_eq0 of tx_enqueue.v 90 output wb_ack_o; // From wishbone_if0 of wishbone_if.v 91 output [31:0] wb_dat_o; // From wishbone_if0 of wishbone_if.v 92 output wb_int_o; // From wishbone_if0 of wishbone_if.v 93 output [7:0] xgmii_txc; // From tx_dq0 of tx_dequeue.v 94 output [63:0] xgmii_txd; // From tx_dq0 of tx_dequeue.v 95 output mdc; 96 output mdio_out; 97 output mdio_tri; // Assert to tristate driver. 98 output [7:0] xge_gpo; 99 100 wire ctrl_tx_enable; // From wishbone_if0 of wishbone_if.v 101 wire ctrl_tx_enable_ctx; // From sync_clk_xgmii_tx0 of sync_clk_xgmii_tx.v 102 wire status_local_fault_ctx; // From sync_clk_xgmii_tx0 of sync_clk_xgmii_tx.v 103 wire status_remote_fault_ctx;// From sync_clk_xgmii_tx0 of sync_clk_xgmii_tx.v 104 wire status_crc_error; // From sync_clk_wb0 of sync_clk_wb.v 105 wire status_crc_error_tog; // From rx_eq0 of rx_enqueue.v 106 wire status_fragment_error; // From sync_clk_wb0 of sync_clk_wb.v 107 wire status_fragment_error_tog;// From rx_eq0 of rx_enqueue.v 108 wire status_local_fault; // From sync_clk_wb0 of sync_clk_wb.v 109 wire status_local_fault_crx; // From fault_sm0 of fault_sm.v 110 wire status_pause_frame_rx; // From sync_clk_wb0 of sync_clk_wb.v 111 wire status_pause_frame_rx_tog;// From rx_eq0 of rx_enqueue.v 112 wire status_remote_fault; // From sync_clk_wb0 of sync_clk_wb.v 113 wire status_remote_fault_crx;// From fault_sm0 of fault_sm.v 114 wire status_rxdfifo_ovflow; // From sync_clk_wb0 of sync_clk_wb.v 115 wire status_rxdfifo_ovflow_tog;// From rx_eq0 of rx_enqueue.v 116 wire status_rxdfifo_udflow; // From sync_clk_wb0 of sync_clk_wb.v 117 wire status_rxdfifo_udflow_tog;// From rx_dq0 of rx_dequeue.v 118 wire status_txdfifo_ovflow; // From sync_clk_wb0 of sync_clk_wb.v 119 wire status_txdfifo_ovflow_tog;// From tx_eq0 of tx_enqueue.v 120 wire status_txdfifo_udflow; // From sync_clk_wb0 of sync_clk_wb.v 121 wire status_txdfifo_udflow_tog;// From tx_dq0 of tx_dequeue.v 122 123 xge_mac xge_mac ( 124 // Clocks and Resets 125 .clk_156m25 (clk_156m25), 126 .clk_xgmii_rx (clk_xgmii_rx), 127 .clk_xgmii_tx (clk_xgmii_tx), 128 .reset_156m25_n (reset_156m25_n), 129 .reset_xgmii_rx_n (reset_xgmii_rx_n), 130 .reset_xgmii_tx_n (reset_xgmii_tx_n), 131 // XGMII 132 .xgmii_txc (xgmii_txc[7:0]), 133 .xgmii_txd (xgmii_txd[63:0]), 134 .xgmii_rxc (xgmii_rxc[7:0]), 135 .xgmii_rxd (xgmii_rxd[63:0]), 136 // Packet interface 137 .pkt_rx_avail (pkt_rx_avail), 138 .pkt_rx_data (pkt_rx_data), 139 .pkt_rx_eop (pkt_rx_eop), 140 .pkt_rx_err (pkt_rx_err), 141 .pkt_rx_mod (pkt_rx_mod), 142 .pkt_rx_sop (pkt_rx_sop), 143 .pkt_rx_val (pkt_rx_val), 144 .pkt_tx_full (pkt_tx_full), 145 // Inputs 146 .pkt_rx_ren (pkt_rx_ren), 147 .pkt_tx_data (pkt_tx_data), 148 .pkt_tx_eop (pkt_tx_eop), 149 .pkt_tx_mod (pkt_tx_mod), 150 .pkt_tx_sop (pkt_tx_sop), 151 .pkt_tx_val (pkt_tx_val), 152 // Control and Status 153 .ctrl_tx_enable (ctrl_tx_enable), 154 .status_crc_error (status_crc_error_tog), 155 .status_fragment_error (status_fragment_error_tog), 156 .status_txdfifo_ovflow (status_txdfifo_ovflow_tog), 157 .status_txdfifo_udflow (status_txdfifo_udflow_tog), 158 .status_rxdfifo_ovflow (status_rxdfifo_ovflow_tog), 159 .status_rxdfifo_udflow (status_rxdfifo_udflow_tog), 160 .status_pause_frame_rx (status_pause_frame_rx_tog), 161 .status_local_fault (status_local_fault_crx), 162 .status_remote_fault (status_remote_fault_crx) 163 ); 164 165 sync_clk_wb sync_clk_wb0 ( 166 // Outputs 167 .status_crc_error (status_crc_error), 168 .status_fragment_error (status_fragment_error), 169 .status_txdfifo_ovflow (status_txdfifo_ovflow), 170 .status_txdfifo_udflow (status_txdfifo_udflow), 171 .status_rxdfifo_ovflow (status_rxdfifo_ovflow), 172 .status_rxdfifo_udflow (status_rxdfifo_udflow), 173 .status_pause_frame_rx (status_pause_frame_rx), 174 .status_local_fault (status_local_fault), 175 .status_remote_fault (status_remote_fault), 176 // Inputs 177 .wb_clk_i (wb_clk_i), 178 .wb_rst_i (wb_rst_i), 179 .status_crc_error_tog (status_crc_error_tog), 180 .status_fragment_error_tog(status_fragment_error_tog), 181 .status_txdfifo_ovflow_tog(status_txdfifo_ovflow_tog), 182 .status_txdfifo_udflow_tog(status_txdfifo_udflow_tog), 183 .status_rxdfifo_ovflow_tog(status_rxdfifo_ovflow_tog), 184 .status_rxdfifo_udflow_tog(status_rxdfifo_udflow_tog), 185 .status_pause_frame_rx_tog(status_pause_frame_rx_tog), 186 .status_local_fault_crx(status_local_fault_crx), 187 .status_remote_fault_crx(status_remote_fault_crx) 188 ); 189 190 191// IJB. This module has only inputs and is treated as a black box by XST which causes a fatal error. 192// Commented out. Original pupose/intent unknown. 193//sync_clk_core sync_clk_core0(/*AUTOINST*/ 194// // Inputs 195// .clk_xgmii_tx (clk_xgmii_tx), 196// .reset_xgmii_tx_n (reset_xgmii_tx_n)); 197 wishbone_if wishbone_if0 ( 198 // Outputs 199 .wb_dat_o (wb_dat_o[31:0]), 200 .wb_ack_o (wb_ack_o), 201 .wb_int_o (wb_int_o), 202 .ctrl_tx_enable (ctrl_tx_enable), 203 // Inputs 204 .wb_clk_i (wb_clk_i), 205 .wb_rst_i (wb_rst_i), 206 .wb_adr_i (wb_adr_i[7:0]), 207 .wb_dat_i (wb_dat_i[31:0]), 208 .wb_we_i (wb_we_i), 209 .wb_stb_i (wb_stb_i), 210 .wb_cyc_i (wb_cyc_i), 211 .status_crc_error (status_crc_error), 212 .status_fragment_error (status_fragment_error), 213 .status_txdfifo_ovflow (status_txdfifo_ovflow), 214 .status_txdfifo_udflow (status_txdfifo_udflow), 215 .status_rxdfifo_ovflow (status_rxdfifo_ovflow), 216 .status_rxdfifo_udflow (status_rxdfifo_udflow), 217 .status_pause_frame_rx (status_pause_frame_rx), 218 .status_local_fault (status_local_fault), 219 .status_remote_fault (status_remote_fault), 220 // MDIO 221 .mdc(mdc), 222 .mdio_in(mdio_in), 223 .mdio_out(mdio_out), 224 .mdio_tri(mdio_tri), 225 .xge_gpo(xge_gpo), 226 .xge_gpi(xge_gpi) 227 ); 228 229endmodule 230