1# 2# Copyright 2012-2013 Ettus Research LLC 3# 4 5################################################## 6# Project Setup 7################################################## 8TOP_MODULE := b205 9BUILD_DIR := build-$(NAME)/ 10export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise 11 12# set me in a custom makefile 13CUSTOM_SRCS = 14CUSTOM_DEFS = 15 16include ../Makefile.common 17include ../../lib/gpif2/Makefile.srcs 18include ../../lib/fifo/Makefile.srcs 19include ../../lib/fifo_200/Makefile.srcs 20include ../../lib/dsp/Makefile.srcs 21include ../../lib/control/Makefile.srcs 22include ../../lib/control_200/Makefile.srcs 23include ../../lib/packet_proc/Makefile.srcs 24include ../../lib/packet_proc_200/Makefile.srcs 25include ../../lib/timing/Makefile.srcs 26include ../../lib/vita_200/Makefile.srcs 27include ../../lib/wishbone/Makefile.srcs 28include ../../lib/axi/Makefile.srcs 29include ../../lib/radio_200/Makefile.srcs 30include coregen_dsp/Makefile.srcs 31 32 33B205_COREGEN_SRCS = \ 34coregen/b205_clk_gen.v \ 35coregen/fifo_4k_2clk.xco \ 36coregen/fifo_short_2clk.xco \ 37coregen/chipscope_icon.xco \ 38coregen/chipscope_ila.xco 39 40################################################## 41# Project Properties 42################################################## 43export PROJECT_PROPERTIES := \ 44family "Spartan6" \ 45device $(DEVICE) \ 46package csg484 \ 47speed -3 \ 48top_level_module_type "HDL" \ 49synthesis_tool "XST (VHDL/Verilog)" \ 50simulator "ISE Simulator (VHDL/Verilog)" \ 51"Preferred Language" "Verilog" \ 52"Enable Message Filtering" FALSE \ 53"Display Incremental Messages" FALSE 54 55################################################## 56# Sources 57################################################## 58TOP_SRCS = \ 59b205.v \ 60b205_ref_pll.v \ 61b205_core.v \ 62b205_io.v \ 63b205.ucf \ 64timing.ucf \ 65../b200/S6CLK2PIN.v \ 66$(B205_COREGEN_SRCS) 67 68SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) $(FIFO_200_SRCS) \ 69$(CONTROL_LIB_SRCS) $(CONTROL_LIB_200_SRCS) $(SDR_LIB_SRCS) \ 70$(TIMING_SRCS) $(OPENCORES_SRCS) \ 71$(VRT_SRCS) \ 72$(GPIF2_SRCS) $(PACKET_PROC_SRCS) $(PACKET_PROC_200_SRCS) \ 73$(WISHBONE_SRCS) \ 74$(TIMING_SRCS) \ 75$(DSP_SRCS) \ 76$(VITA_200_SRCS) \ 77$(AXI_SRCS) \ 78$(RADIO_200_SRCS) \ 79$(CAT_CAP_GEN_SRCS) \ 80$(COREGEN_DSP_SRCS) 81 82################################################## 83# Process Properties 84################################################## 85SYNTHESIZE_PROPERTIES = \ 86"Pack I/O Registers into IOBs" Yes \ 87"Optimization Effort" High \ 88"Optimize Instantiated Primitives" TRUE \ 89"Register Balancing" Yes \ 90"Use Clock Enable" Auto \ 91"Use Synchronous Reset" Auto \ 92"Use Synchronous Set" Auto \ 93"Verilog Macros" "SPARTAN6=1 $(EXTRA_DEFS) $(CUSTOM_DEFS)" \ 94"Other XST Command Line Options" "-loop_iteration_limit 16385" 95 96#"Number of Clock Buffers" 8 \ 97 98TRANSLATE_PROPERTIES = \ 99"Macro Search Path" "$(shell pwd)/../../coregen/" 100 101MAP_PROPERTIES = \ 102"Generate Detailed MAP Report" TRUE \ 103"Allow Logic Optimization Across Hierarchy" TRUE \ 104"Map to Input Functions" 4 \ 105"Optimization Strategy (Cover Mode)" Speed \ 106"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ 107"Perform Timing-Driven Packing and Placement" TRUE \ 108"Map Effort Level" High \ 109"Extra Effort" Normal \ 110"Combinatorial Logic Optimization" TRUE \ 111"Register Duplication" TRUE 112 113PLACE_ROUTE_PROPERTIES = \ 114"Place & Route Effort Level (Overall)" High 115 116STATIC_TIMING_PROPERTIES = \ 117"Number of Paths in Error/Verbose Report" 10 \ 118"Report Type" "Error Report" 119 120GEN_PROG_FILE_PROPERTIES = \ 121"Create Binary Configuration File" TRUE \ 122"Done (Output Events)" 5 \ 123"Enable Bitstream Compression" TRUE \ 124"Unused IOB Pins" "Pull Up" 125 126#"Configuration Rate" 6 \ 127#"Enable Outputs (Output Events)" 6 \ 128 129SIM_MODEL_PROPERTIES = "" 130