1#
2# Copyright 2017 Ettus Research, A National Instruments Company
3# SPDX-License-Identifier: LGPL-3.0
4#
5# Daughterboard Pin Definitions for the N310.
6#
7
8## TDC : ################################################################################
9## Bank 11, 2.5V (DB B)
10#########################################################################################
11
12set_property PACKAGE_PIN   W21              [get_ports {UNUSED_PIN_TDCB_0}]
13set_property PACKAGE_PIN   Y21              [get_ports {UNUSED_PIN_TDCB_1}]
14set_property PACKAGE_PIN   Y22              [get_ports {UNUSED_PIN_TDCB_2}]
15set_property PACKAGE_PIN   Y23              [get_ports {UNUSED_PIN_TDCB_3}]
16set_property IOSTANDARD    LVCMOS25         [get_ports {UNUSED_PIN_TDCB_*}]
17set_property IOB           TRUE             [get_ports {UNUSED_PIN_TDCB_*}]
18
19### USRP IO B : #########################################################################
20## Bank 11/33
21#########################################################################################
22
23## HP GPIO, Bank 33, 1.8V
24
25set_property PACKAGE_PIN   J4               [get_ports {DBB_CPLD_PS_SPI_LE}]
26set_property PACKAGE_PIN   J3               [get_ports {DBB_CPLD_PS_SPI_SCLK}]
27set_property PACKAGE_PIN   D4               [get_ports {DBB_CH1_TX_DSA_DATA[5]}]
28# set_property PACKAGE_PIN   D3               [get_ports {nc}]
29set_property PACKAGE_PIN   K2               [get_ports {DBB_CPLD_PS_SPI_ADDR[0]}]
30set_property PACKAGE_PIN   K3               [get_ports {DBB_CPLD_PS_SPI_ADDR[1]}]
31set_property PACKAGE_PIN   B5               [get_ports {DBB_CH1_TX_DSA_DATA[3]}]
32set_property PACKAGE_PIN   B4               [get_ports {DBB_CH1_TX_DSA_DATA[4]}]
33set_property PACKAGE_PIN   G5               [get_ports {DBB_CPLD_PS_SPI_SDO}]
34set_property PACKAGE_PIN   G4               [get_ports {DBB_CPLD_PS_SPI_SDI}]
35set_property PACKAGE_PIN   J5               [get_ports {DBB_CH1_RX_DSA_DATA[0]}]
36set_property PACKAGE_PIN   K5               [get_ports {DBB_CH1_RX_DSA_DATA[1]}]
37set_property PACKAGE_PIN   D5               [get_ports {DBB_CH1_TX_DSA_DATA[2]}]
38set_property PACKAGE_PIN   E6               [get_ports {DBB_CH1_TX_DSA_DATA[1]}]
39set_property PACKAGE_PIN   L3               [get_ports {DBB_ATR_RX_1}]
40set_property PACKAGE_PIN   L2               [get_ports {DBB_ATR_TX_2}]
41set_property PACKAGE_PIN   G6               [get_ports {DBB_CH1_TX_DSA_DATA[0]}]
42set_property PACKAGE_PIN   H6               [get_ports {DBB_CH1_RX_DSA_DATA[5]}]
43set_property PACKAGE_PIN   H4               [get_ports {DBB_ATR_TX_1}]
44set_property PACKAGE_PIN   H3               [get_ports {DBB_ATR_RX_2}]
45# set_property PACKAGE_PIN   F2               [get_ports {nc}]
46set_property PACKAGE_PIN   G2               [get_ports {DBB_CH1_RX_DSA_DATA[3]}]
47set_property PACKAGE_PIN   J6               [get_ports {DBB_CH1_RX_DSA_DATA[4]}]
48set_property PACKAGE_PIN   K6               [get_ports {DBB_CH1_RX_DSA_DATA[2]}]
49
50## HR GPIO, Bank 10, 2.5V
51
52set_property PACKAGE_PIN   AK17             [get_ports {DBB_MYK_SYNC_IN_n}]
53set_property PACKAGE_PIN   AK18             [get_ports {DBB_CPLD_PL_SPI_ADDR[0]}]
54set_property PACKAGE_PIN   AK21             [get_ports {DBB_MYK_SPI_SDO}]
55set_property PACKAGE_PIN   AJ21             [get_ports {DBB_MYK_SPI_SDIO}]
56set_property PACKAGE_PIN   AF19             [get_ports {DBB_CPLD_PL_SPI_ADDR[1]}]
57set_property PACKAGE_PIN   AG19             [get_ports {DBB_CH2_TX_DSA_DATA[5]}]
58set_property PACKAGE_PIN   AH19             [get_ports {DBB_CPLD_JTAG_TDI}]
59set_property PACKAGE_PIN   AJ19             [get_ports {DBB_CPLD_JTAG_TDO}]
60set_property PACKAGE_PIN   AK22             [get_ports {DBB_MYK_GPIO_1}]
61set_property PACKAGE_PIN   AK23             [get_ports {DBB_MYK_GPIO_4}]
62set_property PACKAGE_PIN   AF20             [get_ports {DBB_CH2_TX_DSA_DATA[4]}]
63set_property PACKAGE_PIN   AG20             [get_ports {DBB_CH2_TX_DSA_DATA[3]}]
64set_property PACKAGE_PIN   AF23             [get_ports {DBB_MYK_SYNC_OUT_n}]
65set_property PACKAGE_PIN   AF24             [get_ports {DBB_CPLD_PL_SPI_SDO}]
66set_property PACKAGE_PIN   AK20             [get_ports {DBB_MYK_GPIO_13}]
67set_property PACKAGE_PIN   AJ20             [get_ports {DBB_MYK_GPIO_0}]
68set_property PACKAGE_PIN   AJ23             [get_ports {DBB_MYK_INTRQ}]
69set_property PACKAGE_PIN   AJ24             [get_ports {DBB_CH2_TX_DSA_DATA[2]}]
70set_property PACKAGE_PIN   AG24             [get_ports {DBB_CH2_TX_DSA_DATA[0]}]
71set_property PACKAGE_PIN   AG25             [get_ports {DBB_CH2_TX_DSA_DATA[1]}]
72set_property PACKAGE_PIN   AG21             [get_ports {DBB_FPGA_CLK_P}]
73set_property PACKAGE_PIN   AH21             [get_ports {DBB_FPGA_CLK_N}]
74set_property PACKAGE_PIN   AE22             [get_ports {DBB_FPGA_SYSREF_P}]
75set_property PACKAGE_PIN   AF22             [get_ports {DBB_FPGA_SYSREF_N}]
76set_property PACKAGE_PIN   AJ25             [get_ports {DBB_CH2_RX_DSA_DATA[3]}]
77set_property PACKAGE_PIN   AK25             [get_ports {DBB_CH2_RX_DSA_DATA[5]}]
78set_property PACKAGE_PIN   AB21             [get_ports {DBB_CPLD_JTAG_TMS}]
79set_property PACKAGE_PIN   AB22             [get_ports {DBB_CPLD_JTAG_TCK}]
80set_property PACKAGE_PIN   AD23             [get_ports {DBB_MYK_GPIO_15}]
81set_property PACKAGE_PIN   AE23             [get_ports {DBB_MYK_SPI_CS_n}]
82set_property PACKAGE_PIN   AB24             [get_ports {DBB_CH2_RX_DSA_DATA[1]}]
83set_property PACKAGE_PIN   AA24             [get_ports {DBB_CH2_RX_DSA_DATA[2]}]
84set_property PACKAGE_PIN   AG22             [get_ports {DBB_CPLD_PL_SPI_LE}]
85set_property PACKAGE_PIN   AH22             [get_ports {DBB_CPLD_PL_SPI_SDI}]
86set_property PACKAGE_PIN   AD21             [get_ports {DBB_MYK_GPIO_12}]
87set_property PACKAGE_PIN   AE21             [get_ports {DBB_MYK_GPIO_14}]
88set_property PACKAGE_PIN   AC22             [get_ports {DBB_MYK_SPI_SCLK}]
89set_property PACKAGE_PIN   AC23             [get_ports {DBB_MYK_GPIO_3}]
90set_property PACKAGE_PIN   AC24             [get_ports {DBB_CH2_RX_DSA_DATA[0]}]
91set_property PACKAGE_PIN   AD24             [get_ports {DBB_CH2_RX_DSA_DATA[4]}]
92set_property PACKAGE_PIN   AH23             [get_ports {DBB_CPLD_PL_SPI_ADDR[2]}]
93set_property PACKAGE_PIN   AH24             [get_ports {DBB_CPLD_PL_SPI_SCLK}]
94
95# set_property PACKAGE_PIN   AA25             [get_ports DBB_SWITCHER_CLOCK]
96# set_property IOSTANDARD    LVCMOS33         [get_ports DBB_SWITCHER_CLOCK]
97# set_property DRIVE         4                [get_ports DBB_SWITCHER_CLOCK]
98# set_property SLEW          SLOW             [get_ports DBB_SWITCHER_CLOCK]
99
100# During SI measurements with default drive strength, many of the FPGA-driven lines to
101# the DB were showing high over/undershoot. Therefore for single-ended lines to the DBs
102# we are decreasing the drive strength to the minimum value (4mA) and explicitly
103# declaring the (default) slew rate as SLOW.
104
105set UsrpIoBHpPinsSe [get_ports {DBB_CPLD_PS_* \
106                                DBB_CH1_* \
107                                DBB_ATR*}]
108set_property IOSTANDARD    LVCMOS18         $UsrpIoBHpPinsSe
109set_property DRIVE         4                $UsrpIoBHpPinsSe
110set_property SLEW          SLOW             $UsrpIoBHpPinsSe
111
112set UsrpIoBHrPinsSe [get_ports {DBB_MYK_SPI_* \
113                                DBB_MYK_INTRQ \
114                                DBB_MYK_SYNC* \
115                                DBB_MYK_GPIO* \
116                                DBB_CPLD_PL_* \
117                                DBB_CPLD_JTAG_* \
118                                DBB_CH2*}]
119set_property IOSTANDARD    LVCMOS25         $UsrpIoBHrPinsSe
120set_property DRIVE         4                $UsrpIoBHrPinsSe
121set_property SLEW          SLOW             $UsrpIoBHrPinsSe
122
123set UsrpIoBHrPinsDiff [get_ports {DBB_FPGA_CLK_* \
124                                  DBB_FPGA_SYSREF_*}]
125set_property IOSTANDARD    LVDS_25          $UsrpIoBHrPinsDiff
126set_property DIFF_TERM     TRUE             $UsrpIoBHrPinsDiff
127
128# Do not allow the DSA lines to float... give them a weak pull if undriven.
129set_property PULLUP TRUE [get_ports {DBB_CH*_*X_DSA_DATA[*]}]
130
131
132### MGTs, Bank 112
133
134set_property PACKAGE_PIN   W8               [get_ports {USRPIO_B_MGTCLK_P}]
135set_property PACKAGE_PIN   W7               [get_ports {USRPIO_B_MGTCLK_N}]
136
137# This mapping uses the TX pins as the "master" and mimics RX off of them so Vivado
138# places the transceivers in the correct places. The mixup in lanes is accounted for
139# in the Mykonos lane crossbar settings.
140set_property PACKAGE_PIN   AC4              [get_ports {USRPIO_B_RX_P[0]}]
141set_property PACKAGE_PIN   AC3              [get_ports {USRPIO_B_RX_N[0]}]
142set_property PACKAGE_PIN   AB6              [get_ports {USRPIO_B_RX_P[1]}]
143set_property PACKAGE_PIN   AB5              [get_ports {USRPIO_B_RX_N[1]}]
144set_property PACKAGE_PIN   Y6               [get_ports {USRPIO_B_RX_P[2]}]
145set_property PACKAGE_PIN   Y5               [get_ports {USRPIO_B_RX_N[2]}]
146set_property PACKAGE_PIN   AA4              [get_ports {USRPIO_B_RX_P[3]}]
147set_property PACKAGE_PIN   AA3              [get_ports {USRPIO_B_RX_N[3]}]
148
149set_property PACKAGE_PIN   AB2              [get_ports {USRPIO_B_TX_P[0]}]
150set_property PACKAGE_PIN   AB1              [get_ports {USRPIO_B_TX_N[0]}]
151set_property PACKAGE_PIN   Y2               [get_ports {USRPIO_B_TX_P[1]}]
152set_property PACKAGE_PIN   Y1               [get_ports {USRPIO_B_TX_N[1]}]
153set_property PACKAGE_PIN   W4               [get_ports {USRPIO_B_TX_P[2]}]
154set_property PACKAGE_PIN   W3               [get_ports {USRPIO_B_TX_N[2]}]
155set_property PACKAGE_PIN   V2               [get_ports {USRPIO_B_TX_P[3]}]
156set_property PACKAGE_PIN   V1               [get_ports {USRPIO_B_TX_N[3]}]
157