1// 2// Copyright 2019 Ettus Research, A National Instruments Brand 3// 4// SPDX-License-Identifier: LGPL-3.0-or-later 5// 6// Module: nirio_chdr64_adapter 7// 8// Description: A transport adapter specific to connecting an NI-RIO streaming 9// interface to CHDR. It assumes to be connected to x300_pcie_int. 10// See also chdr_xport_adapter_generic. 11// 12// The tuser inputs/outputs used for routing are the index of the DMA channel. 13// Because we have 6 DMA channels on NI-RIO on the X300, these are always 3 14// bits wide. 15// 16// Parameters: 17// - PROTOVER: RFNoC protocol version {8'd<major>, 8'd<minor>} 18// - MTU: Log2 of the MTU of the packet in 64-bit words 19// - RT_TBL_SIZE: Log2 of the depth of the return-address routing table 20// - NODE_INST: The node type to return for a node-info discovery 21// 22// Signals: 23// - device_id : The ID of the device that has instantiated this module 24// - s_dma_*: The input Ethernet stream from the MAC (plus tuser for source DMA engine ID) 25// - m_dma_*: The output Ethernet stream to the MAC (plus tuser for dest DMA engine ID) 26// - s_chdr_*: The input CHDR stream from the rfnoc infrastructure 27// - m_chdr_*: The output CHDR stream to the rfnoc infrastructure 28// 29 30module nirio_chdr64_adapter #( 31 parameter [15:0] PROTOVER = {8'd1, 8'd0}, 32 parameter MTU = 10, 33 parameter RT_TBL_SIZE = 6, 34 parameter NODE_INST = 0, 35 parameter DMA_ID_WIDTH = 3 36)( 37 // Clocking and reset interface 38 input wire clk, 39 input wire rst, 40 // Device info 41 input wire [15:0] device_id, 42 // AXI-Stream interface to/from DMA engines 43 input wire [63:0] s_dma_tdata, 44 input wire [DMA_ID_WIDTH-1:0] s_dma_tuser, 45 input wire s_dma_tlast, 46 input wire s_dma_tvalid, 47 output wire s_dma_tready, 48 output wire [63:0] m_dma_tdata, 49 output wire [DMA_ID_WIDTH-1:0] m_dma_tuser, 50 output wire m_dma_tlast, 51 output wire m_dma_tvalid, 52 input wire m_dma_tready, 53 // AXI-Stream interface to/from CHDR infrastructure 54 input wire [63:0] s_chdr_tdata, 55 input wire s_chdr_tlast, 56 input wire s_chdr_tvalid, 57 output wire s_chdr_tready, 58 output wire [63:0] m_chdr_tdata, 59 output wire m_chdr_tlast, 60 output wire m_chdr_tvalid, 61 input wire m_chdr_tready 62); 63 64 `include "../../lib/rfnoc/core/rfnoc_chdr_utils.vh" 65 `include "../../lib/rfnoc/core/rfnoc_chdr_internal_utils.vh" 66 `include "../../lib/rfnoc/xport/rfnoc_xport_types.vh" 67 68 //--------------------------------------- 69 // CHDR Transport Adapter 70 //--------------------------------------- 71 72 chdr_xport_adapter_generic #( 73 .PROTOVER (PROTOVER), 74 .CHDR_W (64), 75 .USER_W (DMA_ID_WIDTH), 76 .TBL_SIZE (RT_TBL_SIZE), 77 .NODE_SUBTYPE (NODE_SUBTYPE_XPORT_NIRIO_CHDR64), 78 .NODE_INST (NODE_INST), 79 .ALLOW_DISC (0) 80 ) xport_adapter_gen_i ( 81 .clk (clk), 82 .rst (rst), 83 .device_id (device_id), 84 .s_axis_xport_tdata (s_dma_tdata), 85 .s_axis_xport_tuser (s_dma_tuser), 86 .s_axis_xport_tlast (s_dma_tlast), 87 .s_axis_xport_tvalid (s_dma_tvalid), 88 .s_axis_xport_tready (s_dma_tready), 89 .m_axis_xport_tdata (m_dma_tdata), 90 .m_axis_xport_tuser (m_dma_tuser), 91 .m_axis_xport_tlast (m_dma_tlast), 92 .m_axis_xport_tvalid (m_dma_tvalid), 93 .m_axis_xport_tready (m_dma_tready), 94 .s_axis_rfnoc_tdata (s_chdr_tdata), 95 .s_axis_rfnoc_tlast (s_chdr_tlast), 96 .s_axis_rfnoc_tvalid (s_chdr_tvalid), 97 .s_axis_rfnoc_tready (s_chdr_tready), 98 .m_axis_rfnoc_tdata (m_chdr_tdata), 99 .m_axis_rfnoc_tlast (m_chdr_tlast), 100 .m_axis_rfnoc_tvalid (m_chdr_tvalid), 101 .m_axis_rfnoc_tready (m_chdr_tready), 102 .ctrlport_req_wr (/* unused */), 103 .ctrlport_req_rd (/* unused */), 104 .ctrlport_req_addr (/* unused */), 105 .ctrlport_req_data (/* unused */), 106 .ctrlport_resp_ack (/* unused */ 1'b0), 107 .ctrlport_resp_data (/* unused */ 32'd0) 108 ); 109 110endmodule 111