1 //
2 // Copyright 2011,2015,2016 Ettus Research LLC
3 // Copyright 2018 Ettus Research, a National Instruments Company
4 //
5 // SPDX-License-Identifier: GPL-3.0-or-later
6 //
7
8 #include "b100_regs.hpp"
9 #include "clock_ctrl.hpp"
10 #include "codec_ctrl.hpp"
11 #include <uhd/exception.hpp>
12 #include <uhd/types/dict.hpp>
13 #include <uhd/types/serial.hpp>
14 #include <uhd/usrp/dboard_iface.hpp>
15 #include <uhdlib/usrp/cores/gpio_core_200.hpp>
16 #include <boost/assign/list_of.hpp>
17
18 using namespace uhd;
19 using namespace uhd::usrp;
20 using namespace boost::assign;
21
22 class b100_dboard_iface : public dboard_iface
23 {
24 public:
b100_dboard_iface(timed_wb_iface::sptr wb_iface,i2c_iface::sptr i2c_iface,spi_iface::sptr spi_iface,b100_clock_ctrl::sptr clock,b100_codec_ctrl::sptr codec)25 b100_dboard_iface(timed_wb_iface::sptr wb_iface,
26 i2c_iface::sptr i2c_iface,
27 spi_iface::sptr spi_iface,
28 b100_clock_ctrl::sptr clock,
29 b100_codec_ctrl::sptr codec)
30 {
31 _wb_iface = wb_iface;
32 _i2c_iface = i2c_iface;
33 _spi_iface = spi_iface;
34 _clock = clock;
35 _codec = codec;
36 _gpio = gpio_core_200::make(_wb_iface, TOREG(SR_GPIO), REG_RB_GPIO);
37
38 // init the clock rate shadows
39 this->set_clock_rate(UNIT_RX, _clock->get_fpga_clock_rate());
40 this->set_clock_rate(UNIT_TX, _clock->get_fpga_clock_rate());
41 }
42
~b100_dboard_iface(void)43 ~b100_dboard_iface(void)
44 {
45 /* NOP */
46 }
47
get_special_props(void)48 special_props_t get_special_props(void)
49 {
50 special_props_t props;
51 props.soft_clock_divider = false;
52 props.mangle_i2c_addrs = false;
53 return props;
54 }
55
56 void write_aux_dac(unit_t, aux_dac_t, double);
57 double read_aux_adc(unit_t, aux_adc_t);
58
59 void set_pin_ctrl(unit_t unit, uint32_t value, uint32_t mask = 0xffffffff);
60 uint32_t get_pin_ctrl(unit_t unit);
61 void set_atr_reg(
62 unit_t unit, atr_reg_t reg, uint32_t value, uint32_t mask = 0xffffffff);
63 uint32_t get_atr_reg(unit_t unit, atr_reg_t reg);
64 void set_gpio_ddr(unit_t unit, uint32_t value, uint32_t mask = 0xffffffff);
65 uint32_t get_gpio_ddr(unit_t unit);
66 void set_gpio_out(unit_t unit, uint32_t value, uint32_t mask = 0xffffffff);
67 uint32_t get_gpio_out(unit_t unit);
68 uint32_t read_gpio(unit_t unit);
69
70 void set_command_time(const uhd::time_spec_t& t);
71 uhd::time_spec_t get_command_time(void);
72
73 void write_i2c(uint16_t, const byte_vector_t&);
74 byte_vector_t read_i2c(uint16_t, size_t);
75
76 void write_spi(
77 unit_t unit, const spi_config_t& config, uint32_t data, size_t num_bits);
78
79 uint32_t read_write_spi(
80 unit_t unit, const spi_config_t& config, uint32_t data, size_t num_bits);
81
82 void set_clock_rate(unit_t, double);
83 std::vector<double> get_clock_rates(unit_t);
84 double get_clock_rate(unit_t);
85 void set_clock_enabled(unit_t, bool);
86 double get_codec_rate(unit_t);
87 void set_fe_connection(
88 unit_t unit, const std::string&, const fe_connection_t& fe_conn);
89
90 private:
91 timed_wb_iface::sptr _wb_iface;
92 i2c_iface::sptr _i2c_iface;
93 spi_iface::sptr _spi_iface;
94 b100_clock_ctrl::sptr _clock;
95 b100_codec_ctrl::sptr _codec;
96 gpio_core_200::sptr _gpio;
97 };
98
99 /***********************************************************************
100 * Make Function
101 **********************************************************************/
make_b100_dboard_iface(timed_wb_iface::sptr wb_iface,i2c_iface::sptr i2c_iface,spi_iface::sptr spi_iface,b100_clock_ctrl::sptr clock,b100_codec_ctrl::sptr codec)102 dboard_iface::sptr make_b100_dboard_iface(timed_wb_iface::sptr wb_iface,
103 i2c_iface::sptr i2c_iface,
104 spi_iface::sptr spi_iface,
105 b100_clock_ctrl::sptr clock,
106 b100_codec_ctrl::sptr codec)
107 {
108 return dboard_iface::sptr(
109 new b100_dboard_iface(wb_iface, i2c_iface, spi_iface, clock, codec));
110 }
111
112 /***********************************************************************
113 * Clock Rates
114 **********************************************************************/
set_clock_rate(unit_t unit,double rate)115 void b100_dboard_iface::set_clock_rate(unit_t unit, double rate)
116 {
117 switch (unit) {
118 case UNIT_RX:
119 return _clock->set_rx_dboard_clock_rate(rate);
120 case UNIT_TX:
121 return _clock->set_tx_dboard_clock_rate(rate);
122 case UNIT_BOTH:
123 set_clock_rate(UNIT_RX, rate);
124 set_clock_rate(UNIT_TX, rate);
125 return;
126 }
127 }
128
get_clock_rates(unit_t unit)129 std::vector<double> b100_dboard_iface::get_clock_rates(unit_t unit)
130 {
131 switch (unit) {
132 case UNIT_RX:
133 return _clock->get_rx_dboard_clock_rates();
134 case UNIT_TX:
135 return _clock->get_tx_dboard_clock_rates();
136 default:
137 UHD_THROW_INVALID_CODE_PATH();
138 }
139 }
140
get_clock_rate(unit_t unit)141 double b100_dboard_iface::get_clock_rate(unit_t unit)
142 {
143 switch (unit) {
144 case UNIT_RX:
145 return _clock->get_rx_clock_rate();
146 case UNIT_TX:
147 return _clock->get_tx_clock_rate();
148 default:
149 UHD_THROW_INVALID_CODE_PATH();
150 }
151 }
152
set_clock_enabled(unit_t unit,bool enb)153 void b100_dboard_iface::set_clock_enabled(unit_t unit, bool enb)
154 {
155 switch (unit) {
156 case UNIT_RX:
157 return _clock->enable_rx_dboard_clock(enb);
158 case UNIT_TX:
159 return _clock->enable_tx_dboard_clock(enb);
160 case UNIT_BOTH:
161 set_clock_enabled(UNIT_RX, enb);
162 set_clock_enabled(UNIT_TX, enb);
163 return;
164 }
165 }
166
get_codec_rate(unit_t)167 double b100_dboard_iface::get_codec_rate(unit_t)
168 {
169 return _clock->get_fpga_clock_rate();
170 }
171
172 /***********************************************************************
173 * GPIO
174 **********************************************************************/
set_pin_ctrl(unit_t unit,uint32_t value,uint32_t mask)175 void b100_dboard_iface::set_pin_ctrl(unit_t unit, uint32_t value, uint32_t mask)
176 {
177 _gpio->set_pin_ctrl(unit, static_cast<uint16_t>(value), static_cast<uint16_t>(mask));
178 }
179
get_pin_ctrl(unit_t unit)180 uint32_t b100_dboard_iface::get_pin_ctrl(unit_t unit)
181 {
182 return static_cast<uint32_t>(_gpio->get_pin_ctrl(unit));
183 }
184
set_atr_reg(unit_t unit,atr_reg_t reg,uint32_t value,uint32_t mask)185 void b100_dboard_iface::set_atr_reg(
186 unit_t unit, atr_reg_t reg, uint32_t value, uint32_t mask)
187 {
188 _gpio->set_atr_reg(
189 unit, reg, static_cast<uint16_t>(value), static_cast<uint16_t>(mask));
190 }
191
get_atr_reg(unit_t unit,atr_reg_t reg)192 uint32_t b100_dboard_iface::get_atr_reg(unit_t unit, atr_reg_t reg)
193 {
194 return static_cast<uint32_t>(_gpio->get_atr_reg(unit, reg));
195 }
196
set_gpio_ddr(unit_t unit,uint32_t value,uint32_t mask)197 void b100_dboard_iface::set_gpio_ddr(unit_t unit, uint32_t value, uint32_t mask)
198 {
199 _gpio->set_gpio_ddr(unit, static_cast<uint16_t>(value), static_cast<uint16_t>(mask));
200 }
201
get_gpio_ddr(unit_t unit)202 uint32_t b100_dboard_iface::get_gpio_ddr(unit_t unit)
203 {
204 return static_cast<uint32_t>(_gpio->get_gpio_ddr(unit));
205 }
206
set_gpio_out(unit_t unit,uint32_t value,uint32_t mask)207 void b100_dboard_iface::set_gpio_out(unit_t unit, uint32_t value, uint32_t mask)
208 {
209 _gpio->set_gpio_out(unit, static_cast<uint16_t>(value), static_cast<uint16_t>(mask));
210 }
211
get_gpio_out(unit_t unit)212 uint32_t b100_dboard_iface::get_gpio_out(unit_t unit)
213 {
214 return static_cast<uint32_t>(_gpio->get_gpio_out(unit));
215 }
216
read_gpio(unit_t unit)217 uint32_t b100_dboard_iface::read_gpio(unit_t unit)
218 {
219 return _gpio->read_gpio(unit);
220 }
221
222 /***********************************************************************
223 * SPI
224 **********************************************************************/
225 /*!
226 * Static function to convert a unit type to a spi slave device number.
227 * \param unit the dboard interface unit type enum
228 * \return the slave device number
229 */
unit_to_otw_spi_dev(dboard_iface::unit_t unit)230 static uint32_t unit_to_otw_spi_dev(dboard_iface::unit_t unit)
231 {
232 switch (unit) {
233 case dboard_iface::UNIT_TX:
234 return B100_SPI_SS_TX_DB;
235 case dboard_iface::UNIT_RX:
236 return B100_SPI_SS_RX_DB;
237 default:
238 UHD_THROW_INVALID_CODE_PATH();
239 }
240 }
241
write_spi(unit_t unit,const spi_config_t & config,uint32_t data,size_t num_bits)242 void b100_dboard_iface::write_spi(
243 unit_t unit, const spi_config_t& config, uint32_t data, size_t num_bits)
244 {
245 _spi_iface->write_spi(unit_to_otw_spi_dev(unit), config, data, num_bits);
246 }
247
read_write_spi(unit_t unit,const spi_config_t & config,uint32_t data,size_t num_bits)248 uint32_t b100_dboard_iface::read_write_spi(
249 unit_t unit, const spi_config_t& config, uint32_t data, size_t num_bits)
250 {
251 return _spi_iface->read_spi(unit_to_otw_spi_dev(unit), config, data, num_bits);
252 }
253
254 /***********************************************************************
255 * I2C
256 **********************************************************************/
write_i2c(uint16_t addr,const byte_vector_t & bytes)257 void b100_dboard_iface::write_i2c(uint16_t addr, const byte_vector_t& bytes)
258 {
259 return _i2c_iface->write_i2c(addr, bytes);
260 }
261
read_i2c(uint16_t addr,size_t num_bytes)262 byte_vector_t b100_dboard_iface::read_i2c(uint16_t addr, size_t num_bytes)
263 {
264 return _i2c_iface->read_i2c(addr, num_bytes);
265 }
266
267 /***********************************************************************
268 * Aux DAX/ADC
269 **********************************************************************/
write_aux_dac(dboard_iface::unit_t,aux_dac_t which,double value)270 void b100_dboard_iface::write_aux_dac(dboard_iface::unit_t, aux_dac_t which, double value)
271 {
272 // same aux dacs for each unit
273 static const uhd::dict<aux_dac_t, b100_codec_ctrl::aux_dac_t> which_to_aux_dac =
274 map_list_of(AUX_DAC_A, b100_codec_ctrl::AUX_DAC_A)(
275 AUX_DAC_B, b100_codec_ctrl::AUX_DAC_B)(AUX_DAC_C, b100_codec_ctrl::AUX_DAC_C)(
276 AUX_DAC_D, b100_codec_ctrl::AUX_DAC_D);
277 _codec->write_aux_dac(which_to_aux_dac[which], value);
278 }
279
read_aux_adc(dboard_iface::unit_t unit,aux_adc_t which)280 double b100_dboard_iface::read_aux_adc(dboard_iface::unit_t unit, aux_adc_t which)
281 {
282 static const uhd::dict<unit_t, uhd::dict<aux_adc_t, b100_codec_ctrl::aux_adc_t>>
283 unit_to_which_to_aux_adc = map_list_of(UNIT_RX,
284 map_list_of(AUX_ADC_A, b100_codec_ctrl::AUX_ADC_A1)(
285 AUX_ADC_B, b100_codec_ctrl::AUX_ADC_B1))(UNIT_TX,
286 map_list_of(AUX_ADC_A, b100_codec_ctrl::AUX_ADC_A2)(
287 AUX_ADC_B, b100_codec_ctrl::AUX_ADC_B2));
288 return _codec->read_aux_adc(unit_to_which_to_aux_adc[unit][which]);
289 }
290
set_command_time(const uhd::time_spec_t & t)291 void b100_dboard_iface::set_command_time(const uhd::time_spec_t& t)
292 {
293 _wb_iface->set_time(t);
294 }
295
get_command_time(void)296 uhd::time_spec_t b100_dboard_iface::get_command_time(void)
297 {
298 return _wb_iface->get_time();
299 }
300
set_fe_connection(unit_t,const std::string &,const fe_connection_t &)301 void b100_dboard_iface::set_fe_connection(
302 unit_t, const std::string&, const fe_connection_t&)
303 {
304 throw uhd::not_implemented_error(
305 "fe connection configuration support not implemented");
306 }
307