1 /* Machine description for AArch64 architecture. 2 Copyright (C) 2009-2018 Free Software Foundation, Inc. 3 Contributed by ARM Ltd. 4 5 This file is part of GCC. 6 7 GCC is free software; you can redistribute it and/or modify it 8 under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3, or (at your option) 10 any later version. 11 12 GCC is distributed in the hope that it will be useful, but 13 WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with GCC; see the file COPYING3. If not see 19 <http://www.gnu.org/licenses/>. */ 20 21 22 #ifndef GCC_AARCH64_PROTOS_H 23 #define GCC_AARCH64_PROTOS_H 24 25 #include "input.h" 26 27 /* SYMBOL_SMALL_ABSOLUTE: Generate symbol accesses through 28 high and lo relocs that calculate the base address using a PC 29 relative reloc. 30 So to get the address of foo, we generate 31 adrp x0, foo 32 add x0, x0, :lo12:foo 33 34 To load or store something to foo, we could use the corresponding 35 load store variants that generate an 36 ldr x0, [x0,:lo12:foo] 37 or 38 str x1, [x0, :lo12:foo] 39 40 This corresponds to the small code model of the compiler. 41 42 SYMBOL_SMALL_GOT_4G: Similar to the one above but this 43 gives us the GOT entry of the symbol being referred to : 44 Thus calculating the GOT entry for foo is done using the 45 following sequence of instructions. The ADRP instruction 46 gets us to the page containing the GOT entry of the symbol 47 and the got_lo12 gets us the actual offset in it, together 48 the base and offset, we can address 4G size GOT table. 49 50 adrp x0, :got:foo 51 ldr x0, [x0, :gotoff_lo12:foo] 52 53 This corresponds to the small PIC model of the compiler. 54 55 SYMBOL_SMALL_GOT_28K: Similar to SYMBOL_SMALL_GOT_4G, but used for symbol 56 restricted within 28K GOT table size. 57 58 ldr reg, [gp, #:gotpage_lo15:sym] 59 60 This corresponds to -fpic model for small memory model of the compiler. 61 62 SYMBOL_SMALL_TLSGD 63 SYMBOL_SMALL_TLSDESC 64 SYMBOL_SMALL_TLSIE 65 SYMBOL_TINY_TLSIE 66 SYMBOL_TLSLE12 67 SYMBOL_TLSLE24 68 SYMBOL_TLSLE32 69 SYMBOL_TLSLE48 70 Each of these represents a thread-local symbol, and corresponds to the 71 thread local storage relocation operator for the symbol being referred to. 72 73 SYMBOL_TINY_ABSOLUTE 74 75 Generate symbol accesses as a PC relative address using a single 76 instruction. To compute the address of symbol foo, we generate: 77 78 ADR x0, foo 79 80 SYMBOL_TINY_GOT 81 82 Generate symbol accesses via the GOT using a single PC relative 83 instruction. To compute the address of symbol foo, we generate: 84 85 ldr t0, :got:foo 86 87 The value of foo can subsequently read using: 88 89 ldrb t0, [t0] 90 91 SYMBOL_FORCE_TO_MEM : Global variables are addressed using 92 constant pool. All variable addresses are spilled into constant 93 pools. The constant pools themselves are addressed using PC 94 relative accesses. This only works for the large code model. 95 */ 96 enum aarch64_symbol_type 97 { 98 SYMBOL_SMALL_ABSOLUTE, 99 SYMBOL_SMALL_GOT_28K, 100 SYMBOL_SMALL_GOT_4G, 101 SYMBOL_SMALL_TLSGD, 102 SYMBOL_SMALL_TLSDESC, 103 SYMBOL_SMALL_TLSIE, 104 SYMBOL_TINY_ABSOLUTE, 105 SYMBOL_TINY_GOT, 106 SYMBOL_TINY_TLSIE, 107 SYMBOL_TLSLE12, 108 SYMBOL_TLSLE24, 109 SYMBOL_TLSLE32, 110 SYMBOL_TLSLE48, 111 SYMBOL_FORCE_TO_MEM 112 }; 113 114 /* Classifies the type of an address query. 115 116 ADDR_QUERY_M 117 Query what is valid for an "m" constraint and a memory_operand 118 (the rules are the same for both). 119 120 ADDR_QUERY_LDP_STP 121 Query what is valid for a load/store pair. 122 123 ADDR_QUERY_ANY 124 Query what is valid for at least one memory constraint, which may 125 allow things that "m" doesn't. For example, the SVE LDR and STR 126 addressing modes allow a wider range of immediate offsets than "m" 127 does. */ 128 enum aarch64_addr_query_type { 129 ADDR_QUERY_M, 130 ADDR_QUERY_LDP_STP, 131 ADDR_QUERY_ANY 132 }; 133 134 /* A set of tuning parameters contains references to size and time 135 cost models and vectors for address cost calculations, register 136 move costs and memory move costs. */ 137 138 /* Scaled addressing modes can vary cost depending on the mode of the 139 value to be loaded/stored. QImode values cannot use scaled 140 addressing modes. */ 141 142 struct scale_addr_mode_cost 143 { 144 const int hi; 145 const int si; 146 const int di; 147 const int ti; 148 }; 149 150 /* Additional cost for addresses. */ 151 struct cpu_addrcost_table 152 { 153 const struct scale_addr_mode_cost addr_scale_costs; 154 const int pre_modify; 155 const int post_modify; 156 const int register_offset; 157 const int register_sextend; 158 const int register_zextend; 159 const int imm_offset; 160 }; 161 162 /* Additional costs for register copies. Cost is for one register. */ 163 struct cpu_regmove_cost 164 { 165 const int GP2GP; 166 const int GP2FP; 167 const int FP2GP; 168 const int FP2FP; 169 }; 170 171 /* Cost for vector insn classes. */ 172 struct cpu_vector_cost 173 { 174 const int scalar_int_stmt_cost; /* Cost of any int scalar operation, 175 excluding load and store. */ 176 const int scalar_fp_stmt_cost; /* Cost of any fp scalar operation, 177 excluding load and store. */ 178 const int scalar_load_cost; /* Cost of scalar load. */ 179 const int scalar_store_cost; /* Cost of scalar store. */ 180 const int vec_int_stmt_cost; /* Cost of any int vector operation, 181 excluding load, store, permute, 182 vector-to-scalar and 183 scalar-to-vector operation. */ 184 const int vec_fp_stmt_cost; /* Cost of any fp vector operation, 185 excluding load, store, permute, 186 vector-to-scalar and 187 scalar-to-vector operation. */ 188 const int vec_permute_cost; /* Cost of permute operation. */ 189 const int vec_to_scalar_cost; /* Cost of vec-to-scalar operation. */ 190 const int scalar_to_vec_cost; /* Cost of scalar-to-vector 191 operation. */ 192 const int vec_align_load_cost; /* Cost of aligned vector load. */ 193 const int vec_unalign_load_cost; /* Cost of unaligned vector load. */ 194 const int vec_unalign_store_cost; /* Cost of unaligned vector store. */ 195 const int vec_store_cost; /* Cost of vector store. */ 196 const int cond_taken_branch_cost; /* Cost of taken branch. */ 197 const int cond_not_taken_branch_cost; /* Cost of not taken branch. */ 198 }; 199 200 /* Branch costs. */ 201 struct cpu_branch_cost 202 { 203 const int predictable; /* Predictable branch or optimizing for size. */ 204 const int unpredictable; /* Unpredictable branch or optimizing for speed. */ 205 }; 206 207 /* Control approximate alternatives to certain FP operators. */ 208 #define AARCH64_APPROX_MODE(MODE) \ 209 ((MIN_MODE_FLOAT <= (MODE) && (MODE) <= MAX_MODE_FLOAT) \ 210 ? (1 << ((MODE) - MIN_MODE_FLOAT)) \ 211 : (MIN_MODE_VECTOR_FLOAT <= (MODE) && (MODE) <= MAX_MODE_VECTOR_FLOAT) \ 212 ? (1 << ((MODE) - MIN_MODE_VECTOR_FLOAT \ 213 + MAX_MODE_FLOAT - MIN_MODE_FLOAT + 1)) \ 214 : (0)) 215 #define AARCH64_APPROX_NONE (0) 216 #define AARCH64_APPROX_ALL (-1) 217 218 /* Allowed modes for approximations. */ 219 struct cpu_approx_modes 220 { 221 const unsigned int division; /* Division. */ 222 const unsigned int sqrt; /* Square root. */ 223 const unsigned int recip_sqrt; /* Reciprocal square root. */ 224 }; 225 226 /* Cache prefetch settings for prefetch-loop-arrays. */ 227 struct cpu_prefetch_tune 228 { 229 const int num_slots; 230 const int l1_cache_size; 231 const int l1_cache_line_size; 232 const int l2_cache_size; 233 const int default_opt_level; 234 }; 235 236 struct tune_params 237 { 238 const struct cpu_cost_table *insn_extra_cost; 239 const struct cpu_addrcost_table *addr_cost; 240 const struct cpu_regmove_cost *regmove_cost; 241 const struct cpu_vector_cost *vec_costs; 242 const struct cpu_branch_cost *branch_costs; 243 const struct cpu_approx_modes *approx_modes; 244 int memmov_cost; 245 int issue_rate; 246 unsigned int fusible_ops; 247 int function_align; 248 int jump_align; 249 int loop_align; 250 int int_reassoc_width; 251 int fp_reassoc_width; 252 int vec_reassoc_width; 253 int min_div_recip_mul_sf; 254 int min_div_recip_mul_df; 255 /* Value for aarch64_case_values_threshold; or 0 for the default. */ 256 unsigned int max_case_values; 257 /* An enum specifying how to take into account CPU autoprefetch capabilities 258 during instruction scheduling: 259 - AUTOPREFETCHER_OFF: Do not take autoprefetch capabilities into account. 260 - AUTOPREFETCHER_WEAK: Attempt to sort sequences of loads/store in order of 261 offsets but allow the pipeline hazard recognizer to alter that order to 262 maximize multi-issue opportunities. 263 - AUTOPREFETCHER_STRONG: Attempt to sort sequences of loads/store in order of 264 offsets and prefer this even if it restricts multi-issue opportunities. */ 265 266 enum aarch64_autoprefetch_model 267 { 268 AUTOPREFETCHER_OFF, 269 AUTOPREFETCHER_WEAK, 270 AUTOPREFETCHER_STRONG 271 } autoprefetcher_model; 272 273 unsigned int extra_tuning_flags; 274 275 /* Place prefetch struct pointer at the end to enable type checking 276 errors when tune_params misses elements (e.g., from erroneous merges). */ 277 const struct cpu_prefetch_tune *prefetch; 278 }; 279 280 #define AARCH64_FUSION_PAIR(x, name) \ 281 AARCH64_FUSE_##name##_index, 282 /* Supported fusion operations. */ 283 enum aarch64_fusion_pairs_index 284 { 285 #include "aarch64-fusion-pairs.def" 286 AARCH64_FUSE_index_END 287 }; 288 289 #define AARCH64_FUSION_PAIR(x, name) \ 290 AARCH64_FUSE_##name = (1u << AARCH64_FUSE_##name##_index), 291 /* Supported fusion operations. */ 292 enum aarch64_fusion_pairs 293 { 294 AARCH64_FUSE_NOTHING = 0, 295 #include "aarch64-fusion-pairs.def" 296 AARCH64_FUSE_ALL = (1u << AARCH64_FUSE_index_END) - 1 297 }; 298 299 #define AARCH64_EXTRA_TUNING_OPTION(x, name) \ 300 AARCH64_EXTRA_TUNE_##name##_index, 301 /* Supported tuning flags indexes. */ 302 enum aarch64_extra_tuning_flags_index 303 { 304 #include "aarch64-tuning-flags.def" 305 AARCH64_EXTRA_TUNE_index_END 306 }; 307 308 309 #define AARCH64_EXTRA_TUNING_OPTION(x, name) \ 310 AARCH64_EXTRA_TUNE_##name = (1u << AARCH64_EXTRA_TUNE_##name##_index), 311 /* Supported tuning flags. */ 312 enum aarch64_extra_tuning_flags 313 { 314 AARCH64_EXTRA_TUNE_NONE = 0, 315 #include "aarch64-tuning-flags.def" 316 AARCH64_EXTRA_TUNE_ALL = (1u << AARCH64_EXTRA_TUNE_index_END) - 1 317 }; 318 319 /* Enum describing the various ways that the 320 aarch64_parse_{arch,tune,cpu,extension} functions can fail. 321 This way their callers can choose what kind of error to give. */ 322 323 enum aarch64_parse_opt_result 324 { 325 AARCH64_PARSE_OK, /* Parsing was successful. */ 326 AARCH64_PARSE_MISSING_ARG, /* Missing argument. */ 327 AARCH64_PARSE_INVALID_FEATURE, /* Invalid feature modifier. */ 328 AARCH64_PARSE_INVALID_ARG /* Invalid arch, tune, cpu arg. */ 329 }; 330 331 /* Enum to distinguish which type of check is to be done in 332 aarch64_simd_valid_immediate. This is used as a bitmask where 333 AARCH64_CHECK_MOV has both bits set. Thus AARCH64_CHECK_MOV will 334 perform all checks. Adding new types would require changes accordingly. */ 335 enum simd_immediate_check { 336 AARCH64_CHECK_ORR = 1 << 0, 337 AARCH64_CHECK_BIC = 1 << 1, 338 AARCH64_CHECK_MOV = AARCH64_CHECK_ORR | AARCH64_CHECK_BIC 339 }; 340 341 extern struct tune_params aarch64_tune_params; 342 343 poly_int64 aarch64_initial_elimination_offset (unsigned, unsigned); 344 int aarch64_get_condition_code (rtx); 345 bool aarch64_address_valid_for_prefetch_p (rtx, bool); 346 bool aarch64_bitmask_imm (HOST_WIDE_INT val, machine_mode); 347 unsigned HOST_WIDE_INT aarch64_and_split_imm1 (HOST_WIDE_INT val_in); 348 unsigned HOST_WIDE_INT aarch64_and_split_imm2 (HOST_WIDE_INT val_in); 349 bool aarch64_and_bitmask_imm (unsigned HOST_WIDE_INT val_in, machine_mode mode); 350 int aarch64_branch_cost (bool, bool); 351 enum aarch64_symbol_type aarch64_classify_symbolic_expression (rtx); 352 bool aarch64_can_const_movi_rtx_p (rtx x, machine_mode mode); 353 bool aarch64_const_vec_all_same_int_p (rtx, HOST_WIDE_INT); 354 bool aarch64_const_vec_all_same_in_range_p (rtx, HOST_WIDE_INT, 355 HOST_WIDE_INT); 356 bool aarch64_constant_address_p (rtx); 357 bool aarch64_emit_approx_div (rtx, rtx, rtx); 358 bool aarch64_emit_approx_sqrt (rtx, rtx, bool); 359 void aarch64_expand_call (rtx, rtx, bool); 360 bool aarch64_expand_movmem (rtx *); 361 bool aarch64_float_const_zero_rtx_p (rtx); 362 bool aarch64_float_const_rtx_p (rtx); 363 bool aarch64_function_arg_regno_p (unsigned); 364 bool aarch64_fusion_enabled_p (enum aarch64_fusion_pairs); 365 bool aarch64_gen_movmemqi (rtx *); 366 bool aarch64_gimple_fold_builtin (gimple_stmt_iterator *); 367 bool aarch64_is_extend_from_extract (scalar_int_mode, rtx, rtx); 368 bool aarch64_is_long_call_p (rtx); 369 bool aarch64_is_noplt_call_p (rtx); 370 bool aarch64_label_mentioned_p (rtx); 371 void aarch64_declare_function_name (FILE *, const char*, tree); 372 bool aarch64_legitimate_pic_operand_p (rtx); 373 bool aarch64_mask_and_shift_for_ubfiz_p (scalar_int_mode, rtx, rtx); 374 bool aarch64_zero_extend_const_eq (machine_mode, rtx, machine_mode, rtx); 375 bool aarch64_move_imm (HOST_WIDE_INT, machine_mode); 376 opt_machine_mode aarch64_sve_pred_mode (unsigned int); 377 bool aarch64_sve_cnt_immediate_p (rtx); 378 bool aarch64_sve_addvl_addpl_immediate_p (rtx); 379 bool aarch64_sve_inc_dec_immediate_p (rtx); 380 int aarch64_add_offset_temporaries (rtx); 381 void aarch64_split_add_offset (scalar_int_mode, rtx, rtx, rtx, rtx, rtx); 382 bool aarch64_mov_operand_p (rtx, machine_mode); 383 rtx aarch64_reverse_mask (machine_mode, unsigned int); 384 bool aarch64_offset_7bit_signed_scaled_p (machine_mode, poly_int64); 385 char *aarch64_output_sve_cnt_immediate (const char *, const char *, rtx); 386 char *aarch64_output_sve_addvl_addpl (rtx, rtx, rtx); 387 char *aarch64_output_sve_inc_dec_immediate (const char *, rtx); 388 char *aarch64_output_scalar_simd_mov_immediate (rtx, scalar_int_mode); 389 char *aarch64_output_simd_mov_immediate (rtx, unsigned, 390 enum simd_immediate_check w = AARCH64_CHECK_MOV); 391 char *aarch64_output_sve_mov_immediate (rtx); 392 char *aarch64_output_ptrue (machine_mode, char); 393 bool aarch64_pad_reg_upward (machine_mode, const_tree, bool); 394 bool aarch64_regno_ok_for_base_p (int, bool); 395 bool aarch64_regno_ok_for_index_p (int, bool); 396 bool aarch64_reinterpret_float_as_int (rtx value, unsigned HOST_WIDE_INT *fail); 397 bool aarch64_simd_check_vect_par_cnst_half (rtx op, machine_mode mode, 398 bool high); 399 bool aarch64_simd_scalar_immediate_valid_for_move (rtx, scalar_int_mode); 400 bool aarch64_simd_shift_imm_p (rtx, machine_mode, bool); 401 bool aarch64_simd_valid_immediate (rtx, struct simd_immediate_info *, 402 enum simd_immediate_check w = AARCH64_CHECK_MOV); 403 rtx aarch64_check_zero_based_sve_index_immediate (rtx); 404 bool aarch64_sve_index_immediate_p (rtx); 405 bool aarch64_sve_arith_immediate_p (rtx, bool); 406 bool aarch64_sve_bitmask_immediate_p (rtx); 407 bool aarch64_sve_dup_immediate_p (rtx); 408 bool aarch64_sve_cmp_immediate_p (rtx, bool); 409 bool aarch64_sve_float_arith_immediate_p (rtx, bool); 410 bool aarch64_sve_float_mul_immediate_p (rtx); 411 bool aarch64_split_dimode_const_store (rtx, rtx); 412 bool aarch64_symbolic_address_p (rtx); 413 bool aarch64_uimm12_shift (HOST_WIDE_INT); 414 bool aarch64_use_return_insn_p (void); 415 const char *aarch64_mangle_builtin_type (const_tree); 416 const char *aarch64_output_casesi (rtx *); 417 418 enum aarch64_symbol_type aarch64_classify_symbol (rtx, HOST_WIDE_INT); 419 enum aarch64_symbol_type aarch64_classify_tls_symbol (rtx); 420 enum reg_class aarch64_regno_regclass (unsigned); 421 int aarch64_asm_preferred_eh_data_format (int, int); 422 int aarch64_fpconst_pow_of_2 (rtx); 423 machine_mode aarch64_hard_regno_caller_save_mode (unsigned, unsigned, 424 machine_mode); 425 int aarch64_uxt_size (int, HOST_WIDE_INT); 426 int aarch64_vec_fpconst_pow_of_2 (rtx); 427 rtx aarch64_eh_return_handler_rtx (void); 428 rtx aarch64_mask_from_zextract_ops (rtx, rtx); 429 const char *aarch64_output_move_struct (rtx *operands); 430 rtx aarch64_return_addr (int, rtx); 431 rtx aarch64_simd_gen_const_vector_dup (machine_mode, HOST_WIDE_INT); 432 bool aarch64_simd_mem_operand_p (rtx); 433 bool aarch64_sve_ld1r_operand_p (rtx); 434 bool aarch64_sve_ldr_operand_p (rtx); 435 bool aarch64_sve_struct_memory_operand_p (rtx); 436 rtx aarch64_simd_vect_par_cnst_half (machine_mode, int, bool); 437 rtx aarch64_tls_get_addr (void); 438 tree aarch64_fold_builtin (tree, int, tree *, bool); 439 unsigned aarch64_dbx_register_number (unsigned); 440 unsigned aarch64_trampoline_size (void); 441 void aarch64_asm_output_labelref (FILE *, const char *); 442 void aarch64_cpu_cpp_builtins (cpp_reader *); 443 const char * aarch64_gen_far_branch (rtx *, int, const char *, const char *); 444 const char * aarch64_output_probe_stack_range (rtx, rtx); 445 void aarch64_err_no_fpadvsimd (machine_mode, const char *); 446 void aarch64_expand_epilogue (bool); 447 void aarch64_expand_mov_immediate (rtx, rtx, rtx (*) (rtx, rtx) = 0); 448 void aarch64_emit_sve_pred_move (rtx, rtx, rtx); 449 void aarch64_expand_sve_mem_move (rtx, rtx, machine_mode); 450 bool aarch64_maybe_expand_sve_subreg_move (rtx, rtx); 451 void aarch64_split_sve_subreg_move (rtx, rtx, rtx); 452 void aarch64_expand_prologue (void); 453 void aarch64_expand_vector_init (rtx, rtx); 454 void aarch64_init_cumulative_args (CUMULATIVE_ARGS *, const_tree, rtx, 455 const_tree, unsigned); 456 void aarch64_init_expanders (void); 457 void aarch64_init_simd_builtins (void); 458 void aarch64_emit_call_insn (rtx); 459 void aarch64_register_pragmas (void); 460 void aarch64_relayout_simd_types (void); 461 void aarch64_reset_previous_fndecl (void); 462 bool aarch64_return_address_signing_enabled (void); 463 void aarch64_save_restore_target_globals (tree); 464 465 /* Initialize builtins for SIMD intrinsics. */ 466 void init_aarch64_simd_builtins (void); 467 468 void aarch64_simd_emit_reg_reg_move (rtx *, machine_mode, unsigned int); 469 470 /* Expand builtins for SIMD intrinsics. */ 471 rtx aarch64_simd_expand_builtin (int, tree, rtx); 472 473 void aarch64_simd_lane_bounds (rtx, HOST_WIDE_INT, HOST_WIDE_INT, const_tree); 474 rtx aarch64_endian_lane_rtx (machine_mode, unsigned int); 475 476 void aarch64_split_128bit_move (rtx, rtx); 477 478 bool aarch64_split_128bit_move_p (rtx, rtx); 479 480 bool aarch64_mov128_immediate (rtx); 481 482 void aarch64_split_simd_combine (rtx, rtx, rtx); 483 484 void aarch64_split_simd_move (rtx, rtx); 485 486 /* Check for a legitimate floating point constant for FMOV. */ 487 bool aarch64_float_const_representable_p (rtx); 488 489 #if defined (RTX_CODE) 490 491 bool aarch64_legitimate_address_p (machine_mode, rtx, bool, 492 aarch64_addr_query_type = ADDR_QUERY_M); 493 machine_mode aarch64_select_cc_mode (RTX_CODE, rtx, rtx); 494 rtx aarch64_gen_compare_reg (RTX_CODE, rtx, rtx); 495 rtx aarch64_load_tp (rtx); 496 497 void aarch64_expand_compare_and_swap (rtx op[]); 498 void aarch64_split_compare_and_swap (rtx op[]); 499 void aarch64_gen_atomic_cas (rtx, rtx, rtx, rtx, rtx); 500 501 bool aarch64_atomic_ldop_supported_p (enum rtx_code); 502 void aarch64_gen_atomic_ldop (enum rtx_code, rtx, rtx, rtx, rtx, rtx); 503 void aarch64_split_atomic_op (enum rtx_code, rtx, rtx, rtx, rtx, rtx, rtx); 504 505 bool aarch64_gen_adjusted_ldpstp (rtx *, bool, scalar_mode, RTX_CODE); 506 507 void aarch64_expand_sve_vec_cmp_int (rtx, rtx_code, rtx, rtx); 508 bool aarch64_expand_sve_vec_cmp_float (rtx, rtx_code, rtx, rtx, bool); 509 void aarch64_expand_sve_vcond (machine_mode, machine_mode, rtx *); 510 #endif /* RTX_CODE */ 511 512 void aarch64_init_builtins (void); 513 514 bool aarch64_process_target_attr (tree); 515 void aarch64_override_options_internal (struct gcc_options *); 516 517 rtx aarch64_expand_builtin (tree exp, 518 rtx target, 519 rtx subtarget ATTRIBUTE_UNUSED, 520 machine_mode mode ATTRIBUTE_UNUSED, 521 int ignore ATTRIBUTE_UNUSED); 522 tree aarch64_builtin_decl (unsigned, bool ATTRIBUTE_UNUSED); 523 tree aarch64_builtin_rsqrt (unsigned int); 524 tree aarch64_builtin_vectorized_function (unsigned int, tree, tree); 525 526 extern void aarch64_split_combinev16qi (rtx operands[3]); 527 extern void aarch64_expand_vec_perm (rtx, rtx, rtx, rtx, unsigned int); 528 extern void aarch64_expand_sve_vec_perm (rtx, rtx, rtx, rtx); 529 extern bool aarch64_madd_needs_nop (rtx_insn *); 530 extern void aarch64_final_prescan_insn (rtx_insn *); 531 void aarch64_atomic_assign_expand_fenv (tree *, tree *, tree *); 532 int aarch64_ccmp_mode_to_code (machine_mode mode); 533 534 bool extract_base_offset_in_addr (rtx mem, rtx *base, rtx *offset); 535 bool aarch64_operands_ok_for_ldpstp (rtx *, bool, machine_mode); 536 bool aarch64_operands_adjust_ok_for_ldpstp (rtx *, bool, scalar_mode); 537 538 extern void aarch64_asm_output_pool_epilogue (FILE *, const char *, 539 tree, HOST_WIDE_INT); 540 541 /* Defined in common/config/aarch64-common.c. */ 542 bool aarch64_handle_option (struct gcc_options *, struct gcc_options *, 543 const struct cl_decoded_option *, location_t); 544 const char *aarch64_rewrite_selected_cpu (const char *name); 545 enum aarch64_parse_opt_result aarch64_parse_extension (const char *, 546 unsigned long *); 547 std::string aarch64_get_extension_string_for_isa_flags (unsigned long, 548 unsigned long); 549 550 rtl_opt_pass *make_pass_fma_steering (gcc::context *ctxt); 551 552 poly_uint64 aarch64_regmode_natural_size (machine_mode); 553 554 #endif /* GCC_AARCH64_PROTOS_H */ 555