1;; Machine description for DEC Alpha for GNU C compiler 2;; Copyright (C) 1992-2018 Free Software Foundation, Inc. 3;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) 4;; 5;; This file is part of GCC. 6;; 7;; GCC is free software; you can redistribute it and/or modify 8;; it under the terms of the GNU General Public License as published by 9;; the Free Software Foundation; either version 3, or (at your option) 10;; any later version. 11;; 12;; GCC is distributed in the hope that it will be useful, 13;; but WITHOUT ANY WARRANTY; without even the implied warranty of 14;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15;; GNU General Public License for more details. 16;; 17;; You should have received a copy of the GNU General Public License 18;; along with GCC; see the file COPYING3. If not see 19;; <http://www.gnu.org/licenses/>. 20 21;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. 22 23;; Uses of UNSPEC in this file: 24 25(define_c_enum "unspec" [ 26 UNSPEC_XFLT_COMPARE 27 UNSPEC_ARG_HOME 28 UNSPEC_LDGP1 29 UNSPEC_INSXH 30 UNSPEC_MSKXH 31 UNSPEC_CVTQL 32 UNSPEC_CVTLQ 33 UNSPEC_LDGP2 34 UNSPEC_LITERAL 35 UNSPEC_LITUSE 36 UNSPEC_SIBCALL 37 UNSPEC_SYMBOL 38 39 ;; TLS Support 40 UNSPEC_TLSGD_CALL 41 UNSPEC_TLSLDM_CALL 42 UNSPEC_TLSGD 43 UNSPEC_TLSLDM 44 UNSPEC_DTPREL 45 UNSPEC_TPREL 46 UNSPEC_TP 47 48 ;; Builtins 49 UNSPEC_CMPBGE 50 UNSPEC_ZAP 51 UNSPEC_AMASK 52 UNSPEC_IMPLVER 53 UNSPEC_PERR 54 UNSPEC_COPYSIGN 55 56 ;; Atomic operations 57 UNSPEC_MB 58 UNSPEC_ATOMIC 59 UNSPEC_CMPXCHG 60 UNSPEC_XCHG 61]) 62 63;; UNSPEC_VOLATILE: 64 65(define_c_enum "unspecv" [ 66 UNSPECV_IMB 67 UNSPECV_BLOCKAGE 68 UNSPECV_SETJMPR ; builtin_setjmp_receiver 69 UNSPECV_LONGJMP ; builtin_longjmp 70 UNSPECV_TRAPB 71 UNSPECV_PSPL ; prologue_stack_probe_loop 72 UNSPECV_REALIGN 73 UNSPECV_EHR ; exception_receiver 74 UNSPECV_MCOUNT 75 UNSPECV_FORCE_MOV 76 UNSPECV_LDGP1 77 UNSPECV_PLDGP2 ; prologue ldgp 78 UNSPECV_SET_TP 79 UNSPECV_RPCC 80 UNSPECV_SETJMPR_ER ; builtin_setjmp_receiver fragment 81 UNSPECV_LL ; load-locked 82 UNSPECV_SC ; store-conditional 83 UNSPECV_CMPXCHG 84]) 85 86;; On non-BWX targets, CQImode must be handled the similarly to HImode 87;; when generating reloads. 88(define_mode_iterator RELOAD12 [QI HI CQI]) 89(define_mode_attr reloadmode [(QI "qi") (HI "hi") (CQI "hi")]) 90 91;; Other mode iterators 92(define_mode_iterator IMODE [QI HI SI DI]) 93(define_mode_iterator I12MODE [QI HI]) 94(define_mode_iterator I124MODE [QI HI SI]) 95(define_mode_iterator I24MODE [HI SI]) 96(define_mode_iterator I248MODE [HI SI DI]) 97(define_mode_iterator I48MODE [SI DI]) 98 99(define_mode_attr DWI [(SI "DI") (DI "TI")]) 100(define_mode_attr modesuffix [(QI "b") (HI "w") (SI "l") (DI "q") 101 (V8QI "b8") (V4HI "w4") 102 (SF "%,") (DF "%-")]) 103(define_mode_attr vecmodesuffix [(QI "b8") (HI "w4")]) 104 105(define_code_iterator any_maxmin [smax smin umax umin]) 106 107(define_code_attr maxmin [(smax "maxs") (smin "mins") 108 (umax "maxu") (umin "minu")]) 109 110;; Where necessary, the suffixes _le and _be are used to distinguish between 111;; little-endian and big-endian patterns. 112;; 113;; Note that the Unicos/Mk assembler does not support the following 114;; opcodes: mov, fmov, nop, fnop, unop. 115 116;; Processor type -- this attribute must exactly match the processor_type 117;; enumeration in alpha.h. 118 119(define_attr "tune" "ev4,ev5,ev6" 120 (const (symbol_ref "((enum attr_tune) alpha_tune)"))) 121 122;; Define an insn type attribute. This is used in function unit delay 123;; computations, among other purposes. For the most part, we use the names 124;; defined in the EV4 documentation, but add a few that we have to know about 125;; separately. 126 127(define_attr "type" 128 "ild,fld,ldsym,ist,fst,ibr,callpal,fbr,jsr,iadd,ilog,shift,icmov,fcmov, 129 icmp,imul,fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,mb,ld_l,st_c, 130 multi,none" 131 (const_string "iadd")) 132 133;; Describe a user's asm statement. 134(define_asm_attributes 135 [(set_attr "type" "multi")]) 136 137;; Define the operand size an insn operates on. Used primarily by mul 138;; and div operations that have size dependent timings. 139 140(define_attr "opsize" "si,di,udi" 141 (const_string "di")) 142 143;; The TRAP attribute marks instructions that may generate traps 144;; (which are imprecise and may need a trapb if software completion 145;; is desired). 146 147(define_attr "trap" "no,yes" 148 (const_string "no")) 149 150;; The ROUND_SUFFIX attribute marks which instructions require a 151;; rounding-mode suffix. The value NONE indicates no suffix, 152;; the value NORMAL indicates a suffix controlled by alpha_fprm. 153 154(define_attr "round_suffix" "none,normal,c" 155 (const_string "none")) 156 157;; The TRAP_SUFFIX attribute marks instructions requiring a trap-mode suffix: 158;; NONE no suffix 159;; SU accepts only /su (cmpt et al) 160;; SUI accepts only /sui (cvtqt and cvtqs) 161;; V_SV accepts /v and /sv (cvtql only) 162;; V_SV_SVI accepts /v, /sv and /svi (cvttq only) 163;; U_SU_SUI accepts /u, /su and /sui (most fp instructions) 164;; 165;; The actual suffix emitted is controlled by alpha_fptm. 166 167(define_attr "trap_suffix" "none,su,sui,v_sv,v_sv_svi,u_su_sui" 168 (const_string "none")) 169 170;; The length of an instruction sequence in bytes. 171 172(define_attr "length" "" 173 (const_int 4)) 174 175;; The USEGP attribute marks instructions that have relocations that use 176;; the GP. 177 178(define_attr "usegp" "no,yes" 179 (cond [(eq_attr "type" "ldsym,jsr") 180 (const_string "yes") 181 (eq_attr "type" "ild,fld,ist,fst") 182 (symbol_ref "((enum attr_usegp) alpha_find_lo_sum_using_gp (insn))") 183 ] 184 (const_string "no"))) 185 186;; The CANNOT_COPY attribute marks instructions with relocations that 187;; cannot easily be duplicated. This includes insns with gpdisp relocs 188;; since they have to stay in 1-1 correspondence with one another. This 189;; also includes jsr insns, since they must stay in correspondence with 190;; the immediately following gpdisp instructions. 191 192(define_attr "cannot_copy" "false,true" 193 (const_string "false")) 194 195;; Used to control the "enabled" attribute on a per-instruction basis. 196;; For convenience, conflate ABI issues re loading of addresses with 197;; an "isa". 198(define_attr "isa" "base,bwx,max,fix,cix,vms,ner,er" 199 (const_string "base")) 200 201(define_attr "enabled" "" 202 (cond [(eq_attr "isa" "bwx") (symbol_ref "TARGET_BWX") 203 (eq_attr "isa" "max") (symbol_ref "TARGET_MAX") 204 (eq_attr "isa" "fix") (symbol_ref "TARGET_FIX") 205 (eq_attr "isa" "cix") (symbol_ref "TARGET_CIX") 206 (eq_attr "isa" "vms") (symbol_ref "TARGET_ABI_OPEN_VMS") 207 (eq_attr "isa" "ner") (symbol_ref "!TARGET_EXPLICIT_RELOCS") 208 (eq_attr "isa" "er") (symbol_ref "TARGET_EXPLICIT_RELOCS") 209 ] 210 (const_int 1))) 211 212;; Include scheduling descriptions. 213 214(include "ev4.md") 215(include "ev5.md") 216(include "ev6.md") 217 218 219;; Operand and operator predicates and constraints 220 221(include "predicates.md") 222(include "constraints.md") 223 224 225;; First define the arithmetic insns. Note that the 32-bit forms also 226;; sign-extend. 227 228;; Handle 32-64 bit extension from memory to a floating point register 229;; specially, since this occurs frequently in int->double conversions. 230;; 231;; Note that while we must retain the =f case in the insn for reload's 232;; benefit, it should be eliminated after reload, so we should never emit 233;; code for that case. But we don't reject the possibility. 234 235(define_expand "extendsidi2" 236 [(set (match_operand:DI 0 "register_operand") 237 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand")))]) 238 239(define_insn "*cvtlq" 240 [(set (match_operand:DI 0 "register_operand" "=f") 241 (unspec:DI [(match_operand:SF 1 "reg_or_0_operand" "fG")] 242 UNSPEC_CVTLQ))] 243 "" 244 "cvtlq %1,%0" 245 [(set_attr "type" "fadd")]) 246 247(define_insn "*extendsidi2_1" 248 [(set (match_operand:DI 0 "register_operand" "=r,r,!*f") 249 (sign_extend:DI 250 (match_operand:SI 1 "nonimmediate_operand" "r,m,m")))] 251 "" 252 "@ 253 addl $31,%1,%0 254 ldl %0,%1 255 lds %0,%1\;cvtlq %0,%0" 256 [(set_attr "type" "iadd,ild,fld") 257 (set_attr "length" "*,*,8")]) 258 259(define_split 260 [(set (match_operand:DI 0 "hard_fp_register_operand") 261 (sign_extend:DI (match_operand:SI 1 "memory_operand")))] 262 "reload_completed" 263 [(set (match_dup 2) (match_dup 1)) 264 (set (match_dup 0) (unspec:DI [(match_dup 2)] UNSPEC_CVTLQ))] 265{ 266 operands[1] = adjust_address (operands[1], SFmode, 0); 267 operands[2] = gen_rtx_REG (SFmode, REGNO (operands[0])); 268}) 269 270;; Optimize sign-extension of SImode loads. This shows up in the wake of 271;; reload when converting fp->int. 272 273(define_peephole2 274 [(set (match_operand:SI 0 "hard_int_register_operand") 275 (match_operand:SI 1 "memory_operand")) 276 (set (match_operand:DI 2 "hard_int_register_operand") 277 (sign_extend:DI (match_dup 0)))] 278 "true_regnum (operands[0]) == true_regnum (operands[2]) 279 || peep2_reg_dead_p (2, operands[0])" 280 [(set (match_dup 2) 281 (sign_extend:DI (match_dup 1)))]) 282 283(define_insn "addsi3" 284 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") 285 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ,rJ,rJ") 286 (match_operand:SI 2 "add_operand" "rI,O,K,L")))] 287 "" 288 "@ 289 addl %r1,%2,%0 290 subl %r1,%n2,%0 291 lda %0,%2(%r1) 292 ldah %0,%h2(%r1)") 293 294(define_split 295 [(set (match_operand:SI 0 "register_operand") 296 (plus:SI (match_operand:SI 1 "register_operand") 297 (match_operand:SI 2 "const_int_operand")))] 298 "! add_operand (operands[2], SImode)" 299 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3))) 300 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))] 301{ 302 HOST_WIDE_INT val = INTVAL (operands[2]); 303 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000); 304 HOST_WIDE_INT rest = val - low; 305 306 operands[3] = GEN_INT (rest); 307 operands[4] = GEN_INT (low); 308}) 309 310(define_insn "*addsi_se" 311 [(set (match_operand:DI 0 "register_operand" "=r,r") 312 (sign_extend:DI 313 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ") 314 (match_operand:SI 2 "sext_add_operand" "rI,O"))))] 315 "" 316 "@ 317 addl %r1,%2,%0 318 subl %r1,%n2,%0") 319 320(define_insn "*addsi_se2" 321 [(set (match_operand:DI 0 "register_operand" "=r,r") 322 (sign_extend:DI 323 (subreg:SI (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ") 324 (match_operand:DI 2 "sext_add_operand" "rI,O")) 325 0)))] 326 "" 327 "@ 328 addl %r1,%2,%0 329 subl %r1,%n2,%0") 330 331(define_split 332 [(set (match_operand:DI 0 "register_operand") 333 (sign_extend:DI 334 (plus:SI (match_operand:SI 1 "reg_not_elim_operand") 335 (match_operand:SI 2 "const_int_operand")))) 336 (clobber (match_operand:SI 3 "reg_not_elim_operand"))] 337 "! sext_add_operand (operands[2], SImode) && INTVAL (operands[2]) > 0 338 && INTVAL (operands[2]) % 4 == 0" 339 [(set (match_dup 3) (match_dup 4)) 340 (set (match_dup 0) (sign_extend:DI (plus:SI (ashift:SI (match_dup 3) 341 (match_dup 5)) 342 (match_dup 1))))] 343{ 344 HOST_WIDE_INT val = INTVAL (operands[2]) / 4; 345 int mult = 4; 346 347 if (val % 2 == 0) 348 val /= 2, mult = 8; 349 350 operands[4] = GEN_INT (val); 351 operands[5] = GEN_INT (exact_log2 (mult)); 352}) 353 354(define_split 355 [(set (match_operand:DI 0 "register_operand") 356 (sign_extend:DI 357 (plus:SI (match_operator:SI 1 "comparison_operator" 358 [(match_operand 2) 359 (match_operand 3)]) 360 (match_operand:SI 4 "add_operand")))) 361 (clobber (match_operand:DI 5 "register_operand"))] 362 "" 363 [(set (match_dup 5) (match_dup 6)) 364 (set (match_dup 0) (sign_extend:DI (plus:SI (match_dup 7) (match_dup 4))))] 365{ 366 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode, 367 operands[2], operands[3]); 368 operands[7] = gen_lowpart (SImode, operands[5]); 369}) 370 371(define_expand "adddi3" 372 [(set (match_operand:DI 0 "register_operand") 373 (plus:DI (match_operand:DI 1 "register_operand") 374 (match_operand:DI 2 "add_operand")))]) 375 376(define_insn "*adddi_er_lo16_dtp" 377 [(set (match_operand:DI 0 "register_operand" "=r") 378 (lo_sum:DI (match_operand:DI 1 "register_operand" "r") 379 (match_operand:DI 2 "dtp16_symbolic_operand")))] 380 "HAVE_AS_TLS" 381 "lda %0,%2(%1)\t\t!dtprel") 382 383(define_insn "*adddi_er_hi32_dtp" 384 [(set (match_operand:DI 0 "register_operand" "=r") 385 (plus:DI (match_operand:DI 1 "register_operand" "r") 386 (high:DI (match_operand:DI 2 "dtp32_symbolic_operand"))))] 387 "HAVE_AS_TLS" 388 "ldah %0,%2(%1)\t\t!dtprelhi") 389 390(define_insn "*adddi_er_lo32_dtp" 391 [(set (match_operand:DI 0 "register_operand" "=r") 392 (lo_sum:DI (match_operand:DI 1 "register_operand" "r") 393 (match_operand:DI 2 "dtp32_symbolic_operand")))] 394 "HAVE_AS_TLS" 395 "lda %0,%2(%1)\t\t!dtprello") 396 397(define_insn "*adddi_er_lo16_tp" 398 [(set (match_operand:DI 0 "register_operand" "=r") 399 (lo_sum:DI (match_operand:DI 1 "register_operand" "r") 400 (match_operand:DI 2 "tp16_symbolic_operand")))] 401 "HAVE_AS_TLS" 402 "lda %0,%2(%1)\t\t!tprel") 403 404(define_insn "*adddi_er_hi32_tp" 405 [(set (match_operand:DI 0 "register_operand" "=r") 406 (plus:DI (match_operand:DI 1 "register_operand" "r") 407 (high:DI (match_operand:DI 2 "tp32_symbolic_operand"))))] 408 "HAVE_AS_TLS" 409 "ldah %0,%2(%1)\t\t!tprelhi") 410 411(define_insn "*adddi_er_lo32_tp" 412 [(set (match_operand:DI 0 "register_operand" "=r") 413 (lo_sum:DI (match_operand:DI 1 "register_operand" "r") 414 (match_operand:DI 2 "tp32_symbolic_operand")))] 415 "HAVE_AS_TLS" 416 "lda %0,%2(%1)\t\t!tprello") 417 418(define_insn "*adddi_er_high_l" 419 [(set (match_operand:DI 0 "register_operand" "=r") 420 (plus:DI (match_operand:DI 1 "register_operand" "r") 421 (high:DI (match_operand:DI 2 "local_symbolic_operand"))))] 422 "TARGET_EXPLICIT_RELOCS && reload_completed" 423 "ldah %0,%2(%1)\t\t!gprelhigh" 424 [(set_attr "usegp" "yes")]) 425 426(define_split 427 [(set (match_operand:DI 0 "register_operand") 428 (high:DI (match_operand:DI 1 "local_symbolic_operand")))] 429 "TARGET_EXPLICIT_RELOCS && reload_completed" 430 [(set (match_dup 0) 431 (plus:DI (match_dup 2) (high:DI (match_dup 1))))] 432 "operands[2] = pic_offset_table_rtx;") 433 434;; We used to expend quite a lot of effort choosing addq/subq/lda. 435;; With complications like 436;; 437;; The NT stack unwind code can't handle a subq to adjust the stack 438;; (that's a bug, but not one we can do anything about). As of NT4.0 SP3, 439;; the exception handling code will loop if a subq is used and an 440;; exception occurs. 441;; 442;; The 19980616 change to emit prologues as RTL also confused some 443;; versions of GDB, which also interprets prologues. This has been 444;; fixed as of GDB 4.18, but it does not harm to unconditionally 445;; use lda here. 446;; 447;; and the fact that the three insns schedule exactly the same, it's 448;; just not worth the effort. 449 450(define_insn "*adddi_internal" 451 [(set (match_operand:DI 0 "register_operand" "=r,r,r") 452 (plus:DI (match_operand:DI 1 "register_operand" "%r,r,r") 453 (match_operand:DI 2 "add_operand" "r,K,L")))] 454 "" 455 "@ 456 addq %1,%2,%0 457 lda %0,%2(%1) 458 ldah %0,%h2(%1)") 459 460;; ??? Allow large constants when basing off the frame pointer or some 461;; virtual register that may eliminate to the frame pointer. This is 462;; done because register elimination offsets will change the hi/lo split, 463;; and if we split before reload, we will require additional instructions. 464 465(define_insn "*adddi_fp_hack" 466 [(set (match_operand:DI 0 "register_operand" "=r,r,r") 467 (plus:DI (match_operand:DI 1 "reg_no_subreg_operand" "r,r,r") 468 (match_operand:DI 2 "const_int_operand" "K,L,n")))] 469 "NONSTRICT_REG_OK_FP_BASE_P (operands[1]) 470 && INTVAL (operands[2]) >= 0 471 /* This is the largest constant an lda+ldah pair can add, minus 472 an upper bound on the displacement between SP and AP during 473 register elimination. See INITIAL_ELIMINATION_OFFSET. */ 474 && INTVAL (operands[2]) 475 < (0x7fff8000 476 - FIRST_PSEUDO_REGISTER * UNITS_PER_WORD 477 - ALPHA_ROUND(crtl->outgoing_args_size) 478 - (ALPHA_ROUND (get_frame_size () 479 + max_reg_num () * UNITS_PER_WORD 480 + crtl->args.pretend_args_size) 481 - crtl->args.pretend_args_size))" 482 "@ 483 lda %0,%2(%1) 484 ldah %0,%h2(%1) 485 #") 486 487;; Don't do this if we are adjusting SP since we don't want to do it 488;; in two steps. Don't split FP sources for the reason listed above. 489(define_split 490 [(set (match_operand:DI 0 "register_operand") 491 (plus:DI (match_operand:DI 1 "register_operand") 492 (match_operand:DI 2 "const_int_operand")))] 493 "! add_operand (operands[2], DImode) 494 && operands[0] != stack_pointer_rtx 495 && operands[1] != frame_pointer_rtx 496 && operands[1] != arg_pointer_rtx" 497 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3))) 498 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))] 499{ 500 HOST_WIDE_INT val = INTVAL (operands[2]); 501 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000); 502 HOST_WIDE_INT rest = val - low; 503 rtx rest_rtx = GEN_INT (rest); 504 505 operands[4] = GEN_INT (low); 506 if (satisfies_constraint_L (rest_rtx)) 507 operands[3] = rest_rtx; 508 else if (can_create_pseudo_p ()) 509 { 510 operands[3] = gen_reg_rtx (DImode); 511 emit_move_insn (operands[3], operands[2]); 512 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3])); 513 DONE; 514 } 515 else 516 FAIL; 517}) 518 519(define_insn "*sadd<modesuffix>" 520 [(set (match_operand:I48MODE 0 "register_operand" "=r,r") 521 (plus:I48MODE 522 (ashift:I48MODE (match_operand:I48MODE 1 "reg_not_elim_operand" "r,r") 523 (match_operand:I48MODE 2 "const23_operand" "I,I")) 524 (match_operand:I48MODE 3 "sext_add_operand" "rI,O")))] 525 "" 526 "@ 527 s%P2add<modesuffix> %1,%3,%0 528 s%P2sub<modesuffix> %1,%n3,%0") 529 530(define_insn_and_split "*saddsi_1" 531 [(set (match_operand:SI 0 "register_operand" "=r,r") 532 (plus:SI 533 (subreg:SI 534 (ashift:DI (match_operand:DI 1 "reg_not_elim_operand" "r,r") 535 (match_operand:DI 2 "const23_operand" "I,I")) 0) 536 (match_operand:SI 3 "sext_add_operand" "rI,O")))] 537 "" 538 "#" 539 "" 540 [(set (match_dup 0) 541 (plus:SI (ashift:SI (match_dup 1) (match_dup 2)) 542 (match_dup 3)))] 543 "operands[1] = gen_lowpart (SImode, operands[1]);") 544 545(define_insn "*saddl_se" 546 [(set (match_operand:DI 0 "register_operand" "=r,r") 547 (sign_extend:DI 548 (plus:SI 549 (ashift:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r") 550 (match_operand:SI 2 "const23_operand" "I,I")) 551 (match_operand:SI 3 "sext_add_operand" "rI,O"))))] 552 "" 553 "@ 554 s%P2addl %1,%3,%0 555 s%P2subl %1,%n3,%0") 556 557(define_insn_and_split "*saddl_se_1" 558 [(set (match_operand:DI 0 "register_operand" "=r,r") 559 (sign_extend:DI 560 (plus:SI 561 (subreg:SI 562 (ashift:DI (match_operand:DI 1 "reg_not_elim_operand" "r,r") 563 (match_operand:DI 2 "const23_operand" "I,I")) 0) 564 (match_operand:SI 3 "sext_add_operand" "rI,O"))))] 565 "" 566 "#" 567 "" 568 [(set (match_dup 0) 569 (sign_extend:DI 570 (plus:SI (ashift:SI (match_dup 1) (match_dup 2)) 571 (match_dup 3))))] 572 "operands[1] = gen_lowpart (SImode, operands[1]);") 573 574(define_split 575 [(set (match_operand:DI 0 "register_operand") 576 (sign_extend:DI 577 (plus:SI (ashift:SI (match_operator:SI 1 "comparison_operator" 578 [(match_operand 2) 579 (match_operand 3)]) 580 (match_operand:SI 4 "const23_operand")) 581 (match_operand:SI 5 "sext_add_operand")))) 582 (clobber (match_operand:DI 6 "reg_not_elim_operand"))] 583 "" 584 [(set (match_dup 6) (match_dup 7)) 585 (set (match_dup 0) 586 (sign_extend:DI (plus:SI (ashift:SI (match_dup 8) (match_dup 4)) 587 (match_dup 5))))] 588{ 589 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode, 590 operands[2], operands[3]); 591 operands[8] = gen_lowpart (SImode, operands[6]); 592}) 593 594(define_insn "addv<mode>3" 595 [(set (match_operand:I48MODE 0 "register_operand" "=r,r") 596 (plus:I48MODE (match_operand:I48MODE 1 "reg_or_0_operand" "%rJ,rJ") 597 (match_operand:I48MODE 2 "sext_add_operand" "rI,O"))) 598 (trap_if (ne (plus:<DWI> (sign_extend:<DWI> (match_dup 1)) 599 (sign_extend:<DWI> (match_dup 2))) 600 (sign_extend:<DWI> (plus:I48MODE (match_dup 1) 601 (match_dup 2)))) 602 (const_int 0))] 603 "" 604 "@ 605 add<modesuffix>v %r1,%2,%0 606 sub<modesuffix>v %r1,%n2,%0") 607 608(define_insn "neg<mode>2" 609 [(set (match_operand:I48MODE 0 "register_operand" "=r") 610 (neg:I48MODE (match_operand:I48MODE 1 "reg_or_8bit_operand" "rI")))] 611 "" 612 "sub<modesuffix> $31,%1,%0") 613 614(define_insn "*negsi_se" 615 [(set (match_operand:DI 0 "register_operand" "=r") 616 (sign_extend:DI (neg:SI 617 (match_operand:SI 1 "reg_or_8bit_operand" "rI"))))] 618 "" 619 "subl $31,%1,%0") 620 621(define_insn "negv<mode>2" 622 [(set (match_operand:I48MODE 0 "register_operand" "=r") 623 (neg:I48MODE (match_operand:I48MODE 1 "register_operand" "r"))) 624 (trap_if (ne (neg:<DWI> (sign_extend:<DWI> (match_dup 1))) 625 (sign_extend:<DWI> (neg:I48MODE (match_dup 1)))) 626 (const_int 0))] 627 "" 628 "sub<modesuffix>v $31,%1,%0") 629 630(define_insn "sub<mode>3" 631 [(set (match_operand:I48MODE 0 "register_operand" "=r") 632 (minus:I48MODE (match_operand:I48MODE 1 "reg_or_0_operand" "rJ") 633 (match_operand:I48MODE 2 "reg_or_8bit_operand" "rI")))] 634 "" 635 "sub<modesuffix> %r1,%2,%0") 636 637(define_insn "*subsi_se" 638 [(set (match_operand:DI 0 "register_operand" "=r") 639 (sign_extend:DI 640 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ") 641 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))] 642 "" 643 "subl %r1,%2,%0") 644 645(define_insn "*subsi_se2" 646 [(set (match_operand:DI 0 "register_operand" "=r") 647 (sign_extend:DI 648 (subreg:SI (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 649 (match_operand:DI 2 "reg_or_8bit_operand" "rI")) 650 0)))] 651 "" 652 "subl %r1,%2,%0") 653 654(define_insn "*ssub<modesuffix>" 655 [(set (match_operand:I48MODE 0 "register_operand" "=r") 656 (minus:I48MODE 657 (ashift:I48MODE (match_operand:I48MODE 1 "reg_not_elim_operand" "r") 658 (match_operand:I48MODE 2 "const23_operand" "I")) 659 (match_operand:I48MODE 3 "reg_or_8bit_operand" "rI")))] 660 "" 661 "s%P2sub<modesuffix> %1,%3,%0") 662 663(define_insn_and_split "*ssubsi_1" 664 [(set (match_operand:SI 0 "register_operand" "=r") 665 (minus:SI 666 (subreg:SI 667 (ashift:DI (match_operand:DI 1 "reg_not_elim_operand" "r") 668 (match_operand:DI 2 "const23_operand" "I")) 0) 669 (match_operand:SI 3 "reg_or_8bit_operand" "rI")))] 670 "" 671 "#" 672 "" 673 [(set (match_dup 0) 674 (minus:SI (ashift:SI (match_dup 1) (match_dup 2)) 675 (match_dup 3)))] 676 "operands[1] = gen_lowpart (SImode, operands[1]);") 677 678(define_insn "*ssubl_se" 679 [(set (match_operand:DI 0 "register_operand" "=r") 680 (sign_extend:DI 681 (minus:SI 682 (ashift:SI (match_operand:SI 1 "reg_not_elim_operand" "r") 683 (match_operand:SI 2 "const23_operand" "I")) 684 (match_operand:SI 3 "reg_or_8bit_operand" "rI"))))] 685 "" 686 "s%P2subl %1,%3,%0") 687 688(define_insn_and_split "*ssubl_se_1" 689 [(set (match_operand:DI 0 "register_operand" "=r") 690 (sign_extend:DI 691 (minus:SI 692 (subreg:SI 693 (ashift:DI (match_operand:DI 1 "reg_not_elim_operand" "r") 694 (match_operand:DI 2 "const23_operand" "I")) 0) 695 (match_operand:SI 3 "reg_or_8bit_operand" "rI"))))] 696 "" 697 "#" 698 "" 699 [(set (match_dup 0) 700 (sign_extend:DI 701 (minus:SI (ashift:SI (match_dup 1) (match_dup 2)) 702 (match_dup 3))))] 703 "operands[1] = gen_lowpart (SImode, operands[1]);") 704 705(define_insn "subv<mode>3" 706 [(set (match_operand:I48MODE 0 "register_operand" "=r") 707 (minus:I48MODE (match_operand:I48MODE 1 "reg_or_0_operand" "rJ") 708 (match_operand:I48MODE 2 "reg_or_8bit_operand" "rI"))) 709 (trap_if (ne (minus:<DWI> (sign_extend:<DWI> (match_dup 1)) 710 (sign_extend:<DWI> (match_dup 2))) 711 (sign_extend:<DWI> (minus:I48MODE (match_dup 1) 712 (match_dup 2)))) 713 (const_int 0))] 714 "" 715 "sub<modesuffix>v %r1,%2,%0") 716 717(define_insn "mul<mode>3" 718 [(set (match_operand:I48MODE 0 "register_operand" "=r") 719 (mult:I48MODE (match_operand:I48MODE 1 "reg_or_0_operand" "%rJ") 720 (match_operand:I48MODE 2 "reg_or_8bit_operand" "rI")))] 721 "" 722 "mul<modesuffix> %r1,%2,%0" 723 [(set_attr "type" "imul") 724 (set_attr "opsize" "<mode>")]) 725 726(define_insn "*mulsi_se" 727 [(set (match_operand:DI 0 "register_operand" "=r") 728 (sign_extend:DI 729 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ") 730 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))] 731 "" 732 "mull %r1,%2,%0" 733 [(set_attr "type" "imul") 734 (set_attr "opsize" "si")]) 735 736(define_insn "mulv<mode>3" 737 [(set (match_operand:I48MODE 0 "register_operand" "=r") 738 (mult:I48MODE (match_operand:I48MODE 1 "reg_or_0_operand" "%rJ") 739 (match_operand:I48MODE 2 "reg_or_8bit_operand" "rI"))) 740 (trap_if (ne (mult:<DWI> (sign_extend:<DWI> (match_dup 1)) 741 (sign_extend:<DWI> (match_dup 2))) 742 (sign_extend:<DWI> (mult:I48MODE (match_dup 1) 743 (match_dup 2)))) 744 (const_int 0))] 745 "" 746 "mul<modesuffix>v %r1,%2,%0" 747 [(set_attr "type" "imul") 748 (set_attr "opsize" "<mode>")]) 749 750(define_expand "umuldi3_highpart" 751 [(set (match_operand:DI 0 "register_operand") 752 (truncate:DI 753 (lshiftrt:TI 754 (mult:TI (zero_extend:TI 755 (match_operand:DI 1 "register_operand")) 756 (match_operand:DI 2 "reg_or_8bit_operand")) 757 (const_int 64))))] 758 "" 759{ 760 if (REG_P (operands[2])) 761 operands[2] = gen_rtx_ZERO_EXTEND (TImode, operands[2]); 762}) 763 764(define_insn "*umuldi3_highpart_reg" 765 [(set (match_operand:DI 0 "register_operand" "=r") 766 (truncate:DI 767 (lshiftrt:TI 768 (mult:TI (zero_extend:TI 769 (match_operand:DI 1 "register_operand" "r")) 770 (zero_extend:TI 771 (match_operand:DI 2 "register_operand" "r"))) 772 (const_int 64))))] 773 "" 774 "umulh %1,%2,%0" 775 [(set_attr "type" "imul") 776 (set_attr "opsize" "udi")]) 777 778(define_insn "*umuldi3_highpart_const" 779 [(set (match_operand:DI 0 "register_operand" "=r") 780 (truncate:DI 781 (lshiftrt:TI 782 (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "r")) 783 (match_operand:TI 2 "cint8_operand" "I")) 784 (const_int 64))))] 785 "" 786 "umulh %1,%2,%0" 787 [(set_attr "type" "imul") 788 (set_attr "opsize" "udi")]) 789 790(define_expand "umulditi3" 791 [(set (match_operand:TI 0 "register_operand") 792 (mult:TI 793 (zero_extend:TI (match_operand:DI 1 "reg_no_subreg_operand")) 794 (zero_extend:TI (match_operand:DI 2 "reg_no_subreg_operand"))))] 795 "" 796{ 797 rtx l = gen_reg_rtx (DImode), h = gen_reg_rtx (DImode); 798 emit_insn (gen_muldi3 (l, operands[1], operands[2])); 799 emit_insn (gen_umuldi3_highpart (h, operands[1], operands[2])); 800 emit_move_insn (gen_lowpart (DImode, operands[0]), l); 801 emit_move_insn (gen_highpart (DImode, operands[0]), h); 802 DONE; 803}) 804 805;; The divide and remainder operations take their inputs from r24 and 806;; r25, put their output in r27, and clobber r23 and r28 on all systems. 807;; 808;; ??? Force sign-extension here because some versions of OSF/1 and 809;; Interix/NT don't do the right thing if the inputs are not properly 810;; sign-extended. But Linux, for instance, does not have this 811;; problem. Is it worth the complication here to eliminate the sign 812;; extension? 813 814(define_code_iterator any_divmod [div mod udiv umod]) 815 816(define_expand "<code>si3" 817 [(set (match_dup 3) 818 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand"))) 819 (set (match_dup 4) 820 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand"))) 821 (parallel [(set (match_dup 5) 822 (sign_extend:DI 823 (any_divmod:SI (match_dup 3) (match_dup 4)))) 824 (clobber (reg:DI 23)) 825 (clobber (reg:DI 28))]) 826 (set (match_operand:SI 0 "nonimmediate_operand") 827 (subreg:SI (match_dup 5) 0))] 828 "TARGET_ABI_OSF" 829{ 830 operands[3] = gen_reg_rtx (DImode); 831 operands[4] = gen_reg_rtx (DImode); 832 operands[5] = gen_reg_rtx (DImode); 833}) 834 835(define_expand "<code>di3" 836 [(parallel [(set (match_operand:DI 0 "register_operand") 837 (any_divmod:DI 838 (match_operand:DI 1 "register_operand") 839 (match_operand:DI 2 "register_operand"))) 840 (clobber (reg:DI 23)) 841 (clobber (reg:DI 28))])] 842 "TARGET_ABI_OSF") 843 844;; Lengths of 8 for ldq $t12,__divq($gp); jsr $t9,($t12),__divq as 845;; expanded by the assembler. 846 847(define_insn_and_split "*divmodsi_internal_er" 848 [(set (match_operand:DI 0 "register_operand" "=c") 849 (sign_extend:DI (match_operator:SI 3 "divmod_operator" 850 [(match_operand:DI 1 "register_operand" "a") 851 (match_operand:DI 2 "register_operand" "b")]))) 852 (clobber (reg:DI 23)) 853 (clobber (reg:DI 28))] 854 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 855 "#" 856 "&& reload_completed" 857 [(parallel [(set (match_dup 0) 858 (sign_extend:DI (match_dup 3))) 859 (use (match_dup 0)) 860 (use (match_dup 4)) 861 (clobber (reg:DI 23)) 862 (clobber (reg:DI 28))])] 863{ 864 const char *str; 865 switch (GET_CODE (operands[3])) 866 { 867 case DIV: 868 str = "__divl"; 869 break; 870 case UDIV: 871 str = "__divlu"; 872 break; 873 case MOD: 874 str = "__reml"; 875 break; 876 case UMOD: 877 str = "__remlu"; 878 break; 879 default: 880 gcc_unreachable (); 881 } 882 operands[4] = GEN_INT (alpha_next_sequence_number++); 883 emit_insn (gen_movdi_er_high_g (operands[0], pic_offset_table_rtx, 884 gen_rtx_SYMBOL_REF (DImode, str), 885 operands[4])); 886} 887 [(set_attr "type" "jsr") 888 (set_attr "length" "8")]) 889 890(define_insn "*divmodsi_internal_er_1" 891 [(set (match_operand:DI 0 "register_operand" "=c") 892 (sign_extend:DI (match_operator:SI 3 "divmod_operator" 893 [(match_operand:DI 1 "register_operand" "a") 894 (match_operand:DI 2 "register_operand" "b")]))) 895 (use (match_operand:DI 4 "register_operand" "c")) 896 (use (match_operand 5 "const_int_operand")) 897 (clobber (reg:DI 23)) 898 (clobber (reg:DI 28))] 899 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 900 "jsr $23,($27),__%E3%j5" 901 [(set_attr "type" "jsr") 902 (set_attr "length" "4")]) 903 904(define_insn "*divmodsi_internal" 905 [(set (match_operand:DI 0 "register_operand" "=c") 906 (sign_extend:DI (match_operator:SI 3 "divmod_operator" 907 [(match_operand:DI 1 "register_operand" "a") 908 (match_operand:DI 2 "register_operand" "b")]))) 909 (clobber (reg:DI 23)) 910 (clobber (reg:DI 28))] 911 "TARGET_ABI_OSF" 912 "%E3 %1,%2,%0" 913 [(set_attr "type" "jsr") 914 (set_attr "length" "8")]) 915 916(define_insn_and_split "*divmoddi_internal_er" 917 [(set (match_operand:DI 0 "register_operand" "=c") 918 (match_operator:DI 3 "divmod_operator" 919 [(match_operand:DI 1 "register_operand" "a") 920 (match_operand:DI 2 "register_operand" "b")])) 921 (clobber (reg:DI 23)) 922 (clobber (reg:DI 28))] 923 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 924 "#" 925 "&& reload_completed" 926 [(parallel [(set (match_dup 0) (match_dup 3)) 927 (use (match_dup 0)) 928 (use (match_dup 4)) 929 (clobber (reg:DI 23)) 930 (clobber (reg:DI 28))])] 931{ 932 const char *str; 933 switch (GET_CODE (operands[3])) 934 { 935 case DIV: 936 str = "__divq"; 937 break; 938 case UDIV: 939 str = "__divqu"; 940 break; 941 case MOD: 942 str = "__remq"; 943 break; 944 case UMOD: 945 str = "__remqu"; 946 break; 947 default: 948 gcc_unreachable (); 949 } 950 operands[4] = GEN_INT (alpha_next_sequence_number++); 951 emit_insn (gen_movdi_er_high_g (operands[0], pic_offset_table_rtx, 952 gen_rtx_SYMBOL_REF (DImode, str), 953 operands[4])); 954} 955 [(set_attr "type" "jsr") 956 (set_attr "length" "8")]) 957 958(define_insn "*divmoddi_internal_er_1" 959 [(set (match_operand:DI 0 "register_operand" "=c") 960 (match_operator:DI 3 "divmod_operator" 961 [(match_operand:DI 1 "register_operand" "a") 962 (match_operand:DI 2 "register_operand" "b")])) 963 (use (match_operand:DI 4 "register_operand" "c")) 964 (use (match_operand 5 "const_int_operand")) 965 (clobber (reg:DI 23)) 966 (clobber (reg:DI 28))] 967 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 968 "jsr $23,($27),__%E3%j5" 969 [(set_attr "type" "jsr") 970 (set_attr "length" "4")]) 971 972(define_insn "*divmoddi_internal" 973 [(set (match_operand:DI 0 "register_operand" "=c") 974 (match_operator:DI 3 "divmod_operator" 975 [(match_operand:DI 1 "register_operand" "a") 976 (match_operand:DI 2 "register_operand" "b")])) 977 (clobber (reg:DI 23)) 978 (clobber (reg:DI 28))] 979 "TARGET_ABI_OSF" 980 "%E3 %1,%2,%0" 981 [(set_attr "type" "jsr") 982 (set_attr "length" "8")]) 983 984;; Next are the basic logical operations. We only expose the DImode operations 985;; to the rtl expanders, but SImode versions exist for combine as well as for 986;; the atomic operation splitters. 987 988(define_insn "*andsi_internal" 989 [(set (match_operand:SI 0 "register_operand" "=r,r,r") 990 (and:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ,rJ") 991 (match_operand:SI 2 "and_operand" "rI,N,M")))] 992 "" 993 "@ 994 and %r1,%2,%0 995 bic %r1,%N2,%0 996 zapnot %r1,%m2,%0" 997 [(set_attr "type" "ilog,ilog,shift")]) 998 999(define_insn "anddi3" 1000 [(set (match_operand:DI 0 "register_operand" "=r,r,r") 1001 (and:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ,rJ") 1002 (match_operand:DI 2 "and_operand" "rI,N,M")))] 1003 "" 1004 "@ 1005 and %r1,%2,%0 1006 bic %r1,%N2,%0 1007 zapnot %r1,%m2,%0" 1008 [(set_attr "type" "ilog,ilog,shift")]) 1009 1010;; There are times when we can split an AND into two AND insns. This occurs 1011;; when we can first clear any bytes and then clear anything else. For 1012;; example "I & 0xffff07" is "(I & 0xffffff) & 0xffffffffffffff07". 1013;; Only do this when running on 64-bit host since the computations are 1014;; too messy otherwise. 1015 1016(define_split 1017 [(set (match_operand:DI 0 "register_operand") 1018 (and:DI (match_operand:DI 1 "register_operand") 1019 (match_operand:DI 2 "const_int_operand")))] 1020 "! and_operand (operands[2], DImode)" 1021 [(set (match_dup 0) (and:DI (match_dup 1) (match_dup 3))) 1022 (set (match_dup 0) (and:DI (match_dup 0) (match_dup 4)))] 1023{ 1024 unsigned HOST_WIDE_INT mask1 = INTVAL (operands[2]); 1025 unsigned HOST_WIDE_INT mask2 = mask1; 1026 int i; 1027 1028 /* For each byte that isn't all zeros, make it all ones. */ 1029 for (i = 0; i < 64; i += 8) 1030 if ((mask1 & ((HOST_WIDE_INT) 0xff << i)) != 0) 1031 mask1 |= (HOST_WIDE_INT) 0xff << i; 1032 1033 /* Now turn on any bits we've just turned off. */ 1034 mask2 |= ~ mask1; 1035 1036 operands[3] = GEN_INT (mask1); 1037 operands[4] = GEN_INT (mask2); 1038}) 1039 1040(define_insn "zero_extendqi<mode>2" 1041 [(set (match_operand:I248MODE 0 "register_operand" "=r,r") 1042 (zero_extend:I248MODE 1043 (match_operand:QI 1 "reg_or_bwx_memory_operand" "r,m")))] 1044 "" 1045 "@ 1046 and %1,0xff,%0 1047 ldbu %0,%1" 1048 [(set_attr "type" "ilog,ild") 1049 (set_attr "isa" "*,bwx")]) 1050 1051(define_insn "zero_extendhi<mode>2" 1052 [(set (match_operand:I48MODE 0 "register_operand" "=r,r") 1053 (zero_extend:I48MODE 1054 (match_operand:HI 1 "reg_or_bwx_memory_operand" "r,m")))] 1055 "" 1056 "@ 1057 zapnot %1,3,%0 1058 ldwu %0,%1" 1059 [(set_attr "type" "shift,ild") 1060 (set_attr "isa" "*,bwx")]) 1061 1062(define_insn "zero_extendsidi2" 1063 [(set (match_operand:DI 0 "register_operand" "=r") 1064 (zero_extend:DI (match_operand:SI 1 "register_operand" "r")))] 1065 "" 1066 "zapnot %1,15,%0" 1067 [(set_attr "type" "shift")]) 1068 1069(define_insn "andnot<mode>3" 1070 [(set (match_operand:I48MODE 0 "register_operand" "=r") 1071 (and:I48MODE 1072 (not:I48MODE (match_operand:I48MODE 1 "reg_or_8bit_operand" "rI")) 1073 (match_operand:I48MODE 2 "reg_or_0_operand" "rJ")))] 1074 "" 1075 "bic %r2,%1,%0" 1076 [(set_attr "type" "ilog")]) 1077 1078(define_insn "*iorsi_internal" 1079 [(set (match_operand:SI 0 "register_operand" "=r,r") 1080 (ior:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ") 1081 (match_operand:SI 2 "or_operand" "rI,N")))] 1082 "" 1083 "@ 1084 bis %r1,%2,%0 1085 ornot %r1,%N2,%0" 1086 [(set_attr "type" "ilog")]) 1087 1088(define_insn "iordi3" 1089 [(set (match_operand:DI 0 "register_operand" "=r,r") 1090 (ior:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ") 1091 (match_operand:DI 2 "or_operand" "rI,N")))] 1092 "" 1093 "@ 1094 bis %r1,%2,%0 1095 ornot %r1,%N2,%0" 1096 [(set_attr "type" "ilog")]) 1097 1098(define_insn "*one_cmplsi_internal" 1099 [(set (match_operand:SI 0 "register_operand" "=r") 1100 (not:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI")))] 1101 "" 1102 "ornot $31,%1,%0" 1103 [(set_attr "type" "ilog")]) 1104 1105(define_insn "one_cmpldi2" 1106 [(set (match_operand:DI 0 "register_operand" "=r") 1107 (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))] 1108 "" 1109 "ornot $31,%1,%0" 1110 [(set_attr "type" "ilog")]) 1111 1112(define_insn "*iornot<mode>3" 1113 [(set (match_operand:I48MODE 0 "register_operand" "=r") 1114 (ior:I48MODE 1115 (not:I48MODE (match_operand:I48MODE 1 "reg_or_8bit_operand" "rI")) 1116 (match_operand:I48MODE 2 "reg_or_0_operand" "rJ")))] 1117 "" 1118 "ornot %r2,%1,%0" 1119 [(set_attr "type" "ilog")]) 1120 1121(define_insn "*xorsi_internal" 1122 [(set (match_operand:SI 0 "register_operand" "=r,r") 1123 (xor:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ") 1124 (match_operand:SI 2 "or_operand" "rI,N")))] 1125 "" 1126 "@ 1127 xor %r1,%2,%0 1128 eqv %r1,%N2,%0" 1129 [(set_attr "type" "ilog")]) 1130 1131(define_insn "xordi3" 1132 [(set (match_operand:DI 0 "register_operand" "=r,r") 1133 (xor:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ") 1134 (match_operand:DI 2 "or_operand" "rI,N")))] 1135 "" 1136 "@ 1137 xor %r1,%2,%0 1138 eqv %r1,%N2,%0" 1139 [(set_attr "type" "ilog")]) 1140 1141(define_insn "*xornot<mode>3" 1142 [(set (match_operand:I48MODE 0 "register_operand" "=r") 1143 (not:I48MODE (xor:I48MODE 1144 (match_operand:I48MODE 1 "register_operand" "%rJ") 1145 (match_operand:I48MODE 2 "register_operand" "rI"))))] 1146 "" 1147 "eqv %r1,%2,%0" 1148 [(set_attr "type" "ilog")]) 1149 1150;; Handle FFS and related insns iff we support CIX. 1151 1152(define_expand "ffsdi2" 1153 [(set (match_dup 2) 1154 (ctz:DI (match_operand:DI 1 "register_operand"))) 1155 (set (match_dup 3) 1156 (plus:DI (match_dup 2) (const_int 1))) 1157 (set (match_operand:DI 0 "register_operand") 1158 (if_then_else:DI (eq (match_dup 1) (const_int 0)) 1159 (const_int 0) (match_dup 3)))] 1160 "TARGET_CIX" 1161{ 1162 operands[2] = gen_reg_rtx (DImode); 1163 operands[3] = gen_reg_rtx (DImode); 1164}) 1165 1166(define_insn "clzdi2" 1167 [(set (match_operand:DI 0 "register_operand" "=r") 1168 (clz:DI (match_operand:DI 1 "register_operand" "r")))] 1169 "TARGET_CIX" 1170 "ctlz %1,%0" 1171 [(set_attr "type" "mvi")]) 1172 1173(define_insn "ctzdi2" 1174 [(set (match_operand:DI 0 "register_operand" "=r") 1175 (ctz:DI (match_operand:DI 1 "register_operand" "r")))] 1176 "TARGET_CIX" 1177 "cttz %1,%0" 1178 [(set_attr "type" "mvi")]) 1179 1180(define_insn "popcountdi2" 1181 [(set (match_operand:DI 0 "register_operand" "=r") 1182 (popcount:DI (match_operand:DI 1 "register_operand" "r")))] 1183 "TARGET_CIX" 1184 "ctpop %1,%0" 1185 [(set_attr "type" "mvi")]) 1186 1187(define_expand "bswapsi2" 1188 [(set (match_operand:SI 0 "register_operand") 1189 (bswap:SI (match_operand:SI 1 "register_operand")))] 1190 "!optimize_size" 1191{ 1192 rtx t0, t1; 1193 1194 t0 = gen_reg_rtx (DImode); 1195 t1 = gen_reg_rtx (DImode); 1196 1197 emit_insn (gen_inslh (t0, gen_lowpart (DImode, operands[1]), GEN_INT (7))); 1198 emit_insn (gen_inswl_const (t1, gen_lowpart (HImode, operands[1]), 1199 GEN_INT (24))); 1200 emit_insn (gen_iordi3 (t1, t0, t1)); 1201 emit_insn (gen_lshrdi3 (t0, t1, GEN_INT (16))); 1202 emit_insn (gen_anddi3 (t1, t1, alpha_expand_zap_mask (0x5))); 1203 emit_insn (gen_anddi3 (t0, t0, alpha_expand_zap_mask (0xa))); 1204 emit_insn (gen_addsi3 (operands[0], gen_lowpart (SImode, t0), 1205 gen_lowpart (SImode, t1))); 1206 DONE; 1207}) 1208 1209(define_expand "bswapdi2" 1210 [(set (match_operand:DI 0 "register_operand") 1211 (bswap:DI (match_operand:DI 1 "register_operand")))] 1212 "!optimize_size" 1213{ 1214 rtx t0, t1; 1215 1216 t0 = gen_reg_rtx (DImode); 1217 t1 = gen_reg_rtx (DImode); 1218 1219 /* This method of shifting and masking is not specific to Alpha, but 1220 is only profitable on Alpha because of our handy byte zap insn. */ 1221 1222 emit_insn (gen_lshrdi3 (t0, operands[1], GEN_INT (32))); 1223 emit_insn (gen_ashldi3 (t1, operands[1], GEN_INT (32))); 1224 emit_insn (gen_iordi3 (t1, t0, t1)); 1225 1226 emit_insn (gen_lshrdi3 (t0, t1, GEN_INT (16))); 1227 emit_insn (gen_ashldi3 (t1, t1, GEN_INT (16))); 1228 emit_insn (gen_anddi3 (t0, t0, alpha_expand_zap_mask (0xcc))); 1229 emit_insn (gen_anddi3 (t1, t1, alpha_expand_zap_mask (0x33))); 1230 emit_insn (gen_iordi3 (t1, t0, t1)); 1231 1232 emit_insn (gen_lshrdi3 (t0, t1, GEN_INT (8))); 1233 emit_insn (gen_ashldi3 (t1, t1, GEN_INT (8))); 1234 emit_insn (gen_anddi3 (t0, t0, alpha_expand_zap_mask (0xaa))); 1235 emit_insn (gen_anddi3 (t1, t1, alpha_expand_zap_mask (0x55))); 1236 emit_insn (gen_iordi3 (operands[0], t0, t1)); 1237 DONE; 1238}) 1239 1240;; Next come the shifts and the various extract and insert operations. 1241 1242(define_insn "ashldi3" 1243 [(set (match_operand:DI 0 "register_operand" "=r,r") 1244 (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ,rJ") 1245 (match_operand:DI 2 "reg_or_6bit_operand" "P,rS")))] 1246 "" 1247{ 1248 switch (which_alternative) 1249 { 1250 case 0: 1251 if (operands[2] == const1_rtx) 1252 return "addq %r1,%r1,%0"; 1253 else 1254 return "s%P2addq %r1,0,%0"; 1255 case 1: 1256 return "sll %r1,%2,%0"; 1257 default: 1258 gcc_unreachable (); 1259 } 1260} 1261 [(set_attr "type" "iadd,shift")]) 1262 1263(define_insn "*ashldi_se" 1264 [(set (match_operand:DI 0 "register_operand" "=r") 1265 (sign_extend:DI 1266 (subreg:SI (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 1267 (match_operand:DI 2 "const_int_operand" "P")) 1268 0)))] 1269 "IN_RANGE (INTVAL (operands[2]), 1, 3)" 1270{ 1271 if (operands[2] == const1_rtx) 1272 return "addl %r1,%r1,%0"; 1273 else 1274 return "s%P2addl %r1,0,%0"; 1275} 1276 [(set_attr "type" "iadd")]) 1277 1278(define_insn "lshrdi3" 1279 [(set (match_operand:DI 0 "register_operand" "=r") 1280 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 1281 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))] 1282 "" 1283 "srl %r1,%2,%0" 1284 [(set_attr "type" "shift")]) 1285 1286(define_insn "ashrdi3" 1287 [(set (match_operand:DI 0 "register_operand" "=r") 1288 (ashiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 1289 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))] 1290 "" 1291 "sra %r1,%2,%0" 1292 [(set_attr "type" "shift")]) 1293 1294(define_insn "extendqi<mode>2" 1295 [(set (match_operand:I24MODE 0 "register_operand" "=r") 1296 (sign_extend:I24MODE 1297 (match_operand:QI 1 "register_operand" "r")))] 1298 "TARGET_BWX" 1299 "sextb %1,%0" 1300 [(set_attr "type" "shift")]) 1301 1302(define_expand "extendqidi2" 1303 [(set (match_operand:DI 0 "register_operand") 1304 (sign_extend:DI (match_operand:QI 1 "general_operand")))] 1305 "" 1306{ 1307 if (TARGET_BWX) 1308 operands[1] = force_reg (QImode, operands[1]); 1309 else 1310 { 1311 rtx x, t1, t2, i56; 1312 1313 if (unaligned_memory_operand (operands[1], QImode)) 1314 { 1315 x = gen_unaligned_extendqidi (operands[0], XEXP (operands[1], 0)); 1316 alpha_set_memflags (x, operands[1]); 1317 emit_insn (x); 1318 DONE; 1319 } 1320 1321 t1 = gen_reg_rtx (DImode); 1322 t2 = gen_reg_rtx (DImode); 1323 i56 = GEN_INT (56); 1324 1325 x = gen_lowpart (DImode, force_reg (QImode, operands[1])); 1326 emit_move_insn (t1, x); 1327 emit_insn (gen_ashldi3 (t2, t1, i56)); 1328 emit_insn (gen_ashrdi3 (operands[0], t2, i56)); 1329 DONE; 1330 } 1331}) 1332 1333(define_insn "*extendqidi2_bwx" 1334 [(set (match_operand:DI 0 "register_operand" "=r") 1335 (sign_extend:DI (match_operand:QI 1 "register_operand" "r")))] 1336 "TARGET_BWX" 1337 "sextb %1,%0" 1338 [(set_attr "type" "shift")]) 1339 1340(define_insn "extendhisi2" 1341 [(set (match_operand:SI 0 "register_operand" "=r") 1342 (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))] 1343 "TARGET_BWX" 1344 "sextw %1,%0" 1345 [(set_attr "type" "shift")]) 1346 1347(define_expand "extendhidi2" 1348 [(set (match_operand:DI 0 "register_operand") 1349 (sign_extend:DI (match_operand:HI 1 "general_operand")))] 1350 "" 1351{ 1352 if (TARGET_BWX) 1353 operands[1] = force_reg (HImode, operands[1]); 1354 else 1355 { 1356 rtx x, t1, t2, i48; 1357 1358 if (unaligned_memory_operand (operands[1], HImode)) 1359 { 1360 x = gen_unaligned_extendhidi (operands[0], XEXP (operands[1], 0)); 1361 alpha_set_memflags (x, operands[1]); 1362 emit_insn (x); 1363 DONE; 1364 } 1365 1366 t1 = gen_reg_rtx (DImode); 1367 t2 = gen_reg_rtx (DImode); 1368 i48 = GEN_INT (48); 1369 1370 x = gen_lowpart (DImode, force_reg (HImode, operands[1])); 1371 emit_move_insn (t1, x); 1372 emit_insn (gen_ashldi3 (t2, t1, i48)); 1373 emit_insn (gen_ashrdi3 (operands[0], t2, i48)); 1374 DONE; 1375 } 1376}) 1377 1378(define_insn "*extendhidi2_bwx" 1379 [(set (match_operand:DI 0 "register_operand" "=r") 1380 (sign_extend:DI (match_operand:HI 1 "register_operand" "r")))] 1381 "TARGET_BWX" 1382 "sextw %1,%0" 1383 [(set_attr "type" "shift")]) 1384 1385;; Here's how we sign extend an unaligned byte and halfword. Doing this 1386;; as a pattern saves one instruction. The code is similar to that for 1387;; the unaligned loads (see below). 1388;; 1389;; Operand 1 is the address, operand 0 is the result. 1390 1391(define_expand "unaligned_extendqidi" 1392 [(set (match_dup 3) 1393 (mem:DI (and:DI (match_operand:DI 1 "address_operand") (const_int -8)))) 1394 (set (match_dup 4) 1395 (ashift:DI (match_dup 3) 1396 (minus:DI (const_int 64) 1397 (ashift:DI 1398 (and:DI (match_dup 2) (const_int 7)) 1399 (const_int 3))))) 1400 (set (match_operand:QI 0 "register_operand") 1401 (ashiftrt:DI (match_dup 4) (const_int 56)))] 1402 "" 1403{ 1404 operands[0] = gen_lowpart (DImode, operands[0]); 1405 operands[2] = get_unaligned_offset (operands[1], 1); 1406 operands[3] = gen_reg_rtx (DImode); 1407 operands[4] = gen_reg_rtx (DImode); 1408}) 1409 1410(define_expand "unaligned_extendhidi" 1411 [(set (match_dup 3) 1412 (mem:DI (and:DI (match_operand:DI 1 "address_operand") (const_int -8)))) 1413 (set (match_dup 4) 1414 (ashift:DI (match_dup 3) 1415 (minus:DI (const_int 64) 1416 (ashift:DI 1417 (and:DI (match_dup 2) (const_int 7)) 1418 (const_int 3))))) 1419 (set (match_operand:HI 0 "register_operand") 1420 (ashiftrt:DI (match_dup 4) (const_int 48)))] 1421 "" 1422{ 1423 operands[0] = gen_lowpart (DImode, operands[0]); 1424 operands[2] = get_unaligned_offset (operands[1], 2); 1425 operands[3] = gen_reg_rtx (DImode); 1426 operands[4] = gen_reg_rtx (DImode); 1427}) 1428 1429(define_insn "*extxl_const" 1430 [(set (match_operand:DI 0 "register_operand" "=r") 1431 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 1432 (match_operand:DI 2 "mode_width_operand" "n") 1433 (match_operand:DI 3 "mul8_operand" "I")))] 1434 "" 1435 "ext%M2l %r1,%s3,%0" 1436 [(set_attr "type" "shift")]) 1437 1438(define_insn "extxl" 1439 [(set (match_operand:DI 0 "register_operand" "=r") 1440 (zero_extract:DI 1441 (match_operand:DI 1 "reg_or_0_operand" "rJ") 1442 (match_operand:DI 2 "mode_width_operand" "n") 1443 (ashift:DI (match_operand:DI 3 "reg_or_8bit_operand" "rI") 1444 (const_int 3))))] 1445 "" 1446 "ext%M2l %r1,%3,%0" 1447 [(set_attr "type" "shift")]) 1448 1449;; Combine has some strange notion of preserving existing undefined behavior 1450;; in shifts larger than a word size. So capture these patterns that it 1451;; should have turned into zero_extracts. 1452 1453(define_insn "*extxl_1" 1454 [(set (match_operand:DI 0 "register_operand" "=r") 1455 (and:DI (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 1456 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI") 1457 (const_int 3))) 1458 (match_operand:DI 3 "mode_mask_operand" "n")))] 1459 "" 1460 "ext%U3l %1,%2,%0" 1461 [(set_attr "type" "shift")]) 1462 1463(define_insn "*extql_2" 1464 [(set (match_operand:DI 0 "register_operand" "=r") 1465 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 1466 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI") 1467 (const_int 3))))] 1468 "" 1469 "extql %1,%2,%0" 1470 [(set_attr "type" "shift")]) 1471 1472(define_insn "extqh" 1473 [(set (match_operand:DI 0 "register_operand" "=r") 1474 (ashift:DI 1475 (match_operand:DI 1 "reg_or_0_operand" "rJ") 1476 (minus:DI (const_int 64) 1477 (ashift:DI 1478 (and:DI 1479 (match_operand:DI 2 "reg_or_8bit_operand" "rI") 1480 (const_int 7)) 1481 (const_int 3)))))] 1482 "" 1483 "extqh %r1,%2,%0" 1484 [(set_attr "type" "shift")]) 1485 1486(define_insn "extwh" 1487 [(set (match_operand:DI 0 "register_operand" "=r") 1488 (ashift:DI 1489 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 1490 (const_int 65535)) 1491 (minus:DI (const_int 64) 1492 (ashift:DI 1493 (and:DI 1494 (match_operand:DI 2 "reg_or_8bit_operand" "rI") 1495 (const_int 7)) 1496 (const_int 3)))))] 1497 "" 1498 "extwh %r1,%2,%0" 1499 [(set_attr "type" "shift")]) 1500 1501(define_insn "extlh" 1502 [(set (match_operand:DI 0 "register_operand" "=r") 1503 (ashift:DI 1504 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 1505 (const_int 2147483647)) 1506 (minus:DI (const_int 64) 1507 (ashift:DI 1508 (and:DI 1509 (match_operand:DI 2 "reg_or_8bit_operand" "rI") 1510 (const_int 7)) 1511 (const_int 3)))))] 1512 "" 1513 "extlh %r1,%2,%0" 1514 [(set_attr "type" "shift")]) 1515 1516;; This converts an extXl into an extXh with an appropriate adjustment 1517;; to the address calculation. 1518 1519;;(define_split 1520;; [(set (match_operand:DI 0 "register_operand") 1521;; (ashift:DI (zero_extract:DI (match_operand:DI 1 "register_operand") 1522;; (match_operand:DI 2 "mode_width_operand") 1523;; (ashift:DI (match_operand:DI 3) 1524;; (const_int 3))) 1525;; (match_operand:DI 4 "const_int_operand"))) 1526;; (clobber (match_operand:DI 5 "register_operand"))] 1527;; "INTVAL (operands[4]) == 64 - INTVAL (operands[2])" 1528;; [(set (match_dup 5) (match_dup 6)) 1529;; (set (match_dup 0) 1530;; (ashift:DI (zero_extract:DI (match_dup 1) (match_dup 2) 1531;; (ashift:DI (plus:DI (match_dup 5) 1532;; (match_dup 7)) 1533;; (const_int 3))) 1534;; (match_dup 4)))] 1535;; " 1536;;{ 1537;; operands[6] = plus_constant (DImode, operands[3], 1538;; INTVAL (operands[2]) / BITS_PER_UNIT); 1539;; operands[7] = GEN_INT (- INTVAL (operands[2]) / BITS_PER_UNIT); 1540;;}") 1541 1542(define_insn "ins<modesuffix>l_const" 1543 [(set (match_operand:DI 0 "register_operand" "=r") 1544 (ashift:DI (zero_extend:DI 1545 (match_operand:I124MODE 1 "register_operand" "r")) 1546 (match_operand:DI 2 "mul8_operand" "I")))] 1547 "" 1548 "ins<modesuffix>l %1,%s2,%0" 1549 [(set_attr "type" "shift")]) 1550 1551(define_insn "ins<modesuffix>l" 1552 [(set (match_operand:DI 0 "register_operand" "=r") 1553 (ashift:DI (zero_extend:DI 1554 (match_operand:I124MODE 1 "register_operand" "r")) 1555 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI") 1556 (const_int 3))))] 1557 "" 1558 "ins<modesuffix>l %1,%2,%0" 1559 [(set_attr "type" "shift")]) 1560 1561(define_insn "insql" 1562 [(set (match_operand:DI 0 "register_operand" "=r") 1563 (ashift:DI (match_operand:DI 1 "register_operand" "r") 1564 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI") 1565 (const_int 3))))] 1566 "" 1567 "insql %1,%2,%0" 1568 [(set_attr "type" "shift")]) 1569 1570;; Combine has this sometimes habit of moving the and outside of the 1571;; shift, making life more interesting. 1572 1573(define_insn "*insxl" 1574 [(set (match_operand:DI 0 "register_operand" "=r") 1575 (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r") 1576 (match_operand:DI 2 "mul8_operand" "I")) 1577 (match_operand:DI 3 "const_int_operand" "i")))] 1578 "((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2]) 1579 == (unsigned HOST_WIDE_INT) INTVAL (operands[3])) 1580 || ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2]) 1581 == (unsigned HOST_WIDE_INT) INTVAL (operands[3])) 1582 || ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2]) 1583 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))" 1584{ 1585 if ((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2]) 1586 == (unsigned HOST_WIDE_INT) INTVAL (operands[3])) 1587 return "insbl %1,%s2,%0"; 1588 if ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2]) 1589 == (unsigned HOST_WIDE_INT) INTVAL (operands[3])) 1590 return "inswl %1,%s2,%0"; 1591 if ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2]) 1592 == (unsigned HOST_WIDE_INT) INTVAL (operands[3])) 1593 return "insll %1,%s2,%0"; 1594 1595 gcc_unreachable (); 1596} 1597 [(set_attr "type" "shift")]) 1598 1599;; We do not include the insXh insns because they are complex to express 1600;; and it does not appear that we would ever want to generate them. 1601;; 1602;; Since we need them for block moves, though, cop out and use unspec. 1603 1604(define_insn "insxh" 1605 [(set (match_operand:DI 0 "register_operand" "=r") 1606 (unspec:DI [(match_operand:DI 1 "register_operand" "r") 1607 (match_operand:DI 2 "mode_width_operand" "n") 1608 (match_operand:DI 3 "reg_or_8bit_operand" "rI")] 1609 UNSPEC_INSXH))] 1610 "" 1611 "ins%M2h %1,%3,%0" 1612 [(set_attr "type" "shift")]) 1613 1614(define_insn "mskxl" 1615 [(set (match_operand:DI 0 "register_operand" "=r") 1616 (and:DI (not:DI (ashift:DI 1617 (match_operand:DI 2 "mode_mask_operand" "n") 1618 (ashift:DI 1619 (match_operand:DI 3 "reg_or_8bit_operand" "rI") 1620 (const_int 3)))) 1621 (match_operand:DI 1 "reg_or_0_operand" "rJ")))] 1622 "" 1623 "msk%U2l %r1,%3,%0" 1624 [(set_attr "type" "shift")]) 1625 1626;; We do not include the mskXh insns because it does not appear we would 1627;; ever generate one. 1628;; 1629;; Again, we do for block moves and we use unspec again. 1630 1631(define_insn "mskxh" 1632 [(set (match_operand:DI 0 "register_operand" "=r") 1633 (unspec:DI [(match_operand:DI 1 "register_operand" "r") 1634 (match_operand:DI 2 "mode_width_operand" "n") 1635 (match_operand:DI 3 "reg_or_8bit_operand" "rI")] 1636 UNSPEC_MSKXH))] 1637 "" 1638 "msk%M2h %1,%3,%0" 1639 [(set_attr "type" "shift")]) 1640 1641;; Prefer AND + NE over LSHIFTRT + AND. 1642 1643(define_insn_and_split "*ze_and_ne" 1644 [(set (match_operand:DI 0 "register_operand" "=r") 1645 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 1646 (const_int 1) 1647 (match_operand 2 "const_int_operand" "I")))] 1648 "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 8" 1649 "#" 1650 "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 8" 1651 [(set (match_dup 0) 1652 (and:DI (match_dup 1) (match_dup 3))) 1653 (set (match_dup 0) 1654 (ne:DI (match_dup 0) (const_int 0)))] 1655 "operands[3] = GEN_INT (1 << INTVAL (operands[2]));") 1656 1657;; Floating-point operations. All the double-precision insns can extend 1658;; from single, so indicate that. The exception are the ones that simply 1659;; play with the sign bits; it's not clear what to do there. 1660 1661(define_mode_iterator FMODE [SF DF]) 1662 1663(define_mode_attr opmode [(SF "si") (DF "di")]) 1664 1665(define_insn "abs<mode>2" 1666 [(set (match_operand:FMODE 0 "register_operand" "=f") 1667 (abs:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG")))] 1668 "TARGET_FP" 1669 "cpys $f31,%R1,%0" 1670 [(set_attr "type" "fcpys")]) 1671 1672(define_insn "*nabs<mode>2" 1673 [(set (match_operand:FMODE 0 "register_operand" "=f") 1674 (neg:FMODE 1675 (abs:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG"))))] 1676 "TARGET_FP" 1677 "cpysn $f31,%R1,%0" 1678 [(set_attr "type" "fadd")]) 1679 1680(define_expand "abstf2" 1681 [(parallel [(set (match_operand:TF 0 "register_operand") 1682 (abs:TF (match_operand:TF 1 "reg_or_0_operand"))) 1683 (use (match_dup 2))])] 1684 "TARGET_HAS_XFLOATING_LIBS" 1685 "operands[2] = force_reg (DImode, GEN_INT (HOST_WIDE_INT_1U << 63));") 1686 1687(define_insn_and_split "*abstf_internal" 1688 [(set (match_operand:TF 0 "register_operand" "=r") 1689 (abs:TF (match_operand:TF 1 "reg_or_0_operand" "rG"))) 1690 (use (match_operand:DI 2 "register_operand" "r"))] 1691 "TARGET_HAS_XFLOATING_LIBS" 1692 "#" 1693 "&& reload_completed" 1694 [(const_int 0)] 1695 "alpha_split_tfmode_frobsign (operands, gen_andnotdi3); DONE;") 1696 1697(define_insn "neg<mode>2" 1698 [(set (match_operand:FMODE 0 "register_operand" "=f") 1699 (neg:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG")))] 1700 "TARGET_FP" 1701 "cpysn %R1,%R1,%0" 1702 [(set_attr "type" "fadd")]) 1703 1704(define_expand "negtf2" 1705 [(parallel [(set (match_operand:TF 0 "register_operand") 1706 (neg:TF (match_operand:TF 1 "reg_or_0_operand"))) 1707 (use (match_dup 2))])] 1708 "TARGET_HAS_XFLOATING_LIBS" 1709 "operands[2] = force_reg (DImode, GEN_INT (HOST_WIDE_INT_1U << 63));") 1710 1711(define_insn_and_split "*negtf_internal" 1712 [(set (match_operand:TF 0 "register_operand" "=r") 1713 (neg:TF (match_operand:TF 1 "reg_or_0_operand" "rG"))) 1714 (use (match_operand:DI 2 "register_operand" "r"))] 1715 "TARGET_HAS_XFLOATING_LIBS" 1716 "#" 1717 "&& reload_completed" 1718 [(const_int 0)] 1719 "alpha_split_tfmode_frobsign (operands, gen_xordi3); DONE;") 1720 1721(define_insn "copysign<mode>3" 1722 [(set (match_operand:FMODE 0 "register_operand" "=f") 1723 (unspec:FMODE [(match_operand:FMODE 1 "reg_or_0_operand" "fG") 1724 (match_operand:FMODE 2 "reg_or_0_operand" "fG")] 1725 UNSPEC_COPYSIGN))] 1726 "TARGET_FP" 1727 "cpys %R2,%R1,%0" 1728 [(set_attr "type" "fadd")]) 1729 1730(define_insn "*ncopysign<mode>3" 1731 [(set (match_operand:FMODE 0 "register_operand" "=f") 1732 (neg:FMODE 1733 (unspec:FMODE [(match_operand:FMODE 1 "reg_or_0_operand" "fG") 1734 (match_operand:FMODE 2 "reg_or_0_operand" "fG")] 1735 UNSPEC_COPYSIGN)))] 1736 "TARGET_FP" 1737 "cpysn %R2,%R1,%0" 1738 [(set_attr "type" "fadd")]) 1739 1740(define_insn "add<mode>3" 1741 [(set (match_operand:FMODE 0 "register_operand" "=f,&f") 1742 (plus:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "%fG,fG") 1743 (match_operand:FMODE 2 "reg_or_0_operand" "fG,fG")))] 1744 "TARGET_FP" 1745 "add<modesuffix>%/ %R1,%R2,%0" 1746 [(set_attr "type" "fadd") 1747 (set_attr "trap" "yes") 1748 (set_attr "round_suffix" "normal") 1749 (set_attr "trap_suffix" "u_su_sui") 1750 (set (attr "enabled") 1751 (cond [(eq_attr "alternative" "0") 1752 (symbol_ref "alpha_fptm < ALPHA_FPTM_SU") 1753 ] 1754 (symbol_ref "true")))]) 1755 1756(define_insn "*adddf_ext1" 1757 [(set (match_operand:DF 0 "register_operand" "=f") 1758 (plus:DF (float_extend:DF 1759 (match_operand:SF 1 "reg_or_0_operand" "fG")) 1760 (match_operand:DF 2 "reg_or_0_operand" "fG")))] 1761 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 1762 "add%-%/ %R1,%R2,%0" 1763 [(set_attr "type" "fadd") 1764 (set_attr "trap" "yes") 1765 (set_attr "round_suffix" "normal") 1766 (set_attr "trap_suffix" "u_su_sui")]) 1767 1768(define_insn "*adddf_ext2" 1769 [(set (match_operand:DF 0 "register_operand" "=f") 1770 (plus:DF (float_extend:DF 1771 (match_operand:SF 1 "reg_or_0_operand" "%fG")) 1772 (float_extend:DF 1773 (match_operand:SF 2 "reg_or_0_operand" "fG"))))] 1774 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 1775 "add%-%/ %R1,%R2,%0" 1776 [(set_attr "type" "fadd") 1777 (set_attr "trap" "yes") 1778 (set_attr "round_suffix" "normal") 1779 (set_attr "trap_suffix" "u_su_sui")]) 1780 1781(define_expand "addtf3" 1782 [(use (match_operand:TF 0 "register_operand")) 1783 (use (match_operand:TF 1 "general_operand")) 1784 (use (match_operand:TF 2 "general_operand"))] 1785 "TARGET_HAS_XFLOATING_LIBS" 1786 "alpha_emit_xfloating_arith (PLUS, operands); DONE;") 1787 1788(define_insn "sub<mode>3" 1789 [(set (match_operand:FMODE 0 "register_operand" "=f,&f") 1790 (minus:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG,fG") 1791 (match_operand:FMODE 2 "reg_or_0_operand" "fG,fG")))] 1792 "TARGET_FP" 1793 "sub<modesuffix>%/ %R1,%R2,%0" 1794 [(set_attr "type" "fadd") 1795 (set_attr "trap" "yes") 1796 (set_attr "round_suffix" "normal") 1797 (set_attr "trap_suffix" "u_su_sui") 1798 (set (attr "enabled") 1799 (cond [(eq_attr "alternative" "0") 1800 (symbol_ref "alpha_fptm < ALPHA_FPTM_SU") 1801 ] 1802 (symbol_ref "true")))]) 1803 1804(define_insn "*subdf_ext1" 1805 [(set (match_operand:DF 0 "register_operand" "=f") 1806 (minus:DF (float_extend:DF 1807 (match_operand:SF 1 "reg_or_0_operand" "fG")) 1808 (match_operand:DF 2 "reg_or_0_operand" "fG")))] 1809 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 1810 "sub%-%/ %R1,%R2,%0" 1811 [(set_attr "type" "fadd") 1812 (set_attr "trap" "yes") 1813 (set_attr "round_suffix" "normal") 1814 (set_attr "trap_suffix" "u_su_sui")]) 1815 1816(define_insn "*subdf_ext2" 1817 [(set (match_operand:DF 0 "register_operand" "=f") 1818 (minus:DF (match_operand:DF 1 "reg_or_0_operand" "fG") 1819 (float_extend:DF 1820 (match_operand:SF 2 "reg_or_0_operand" "fG"))))] 1821 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 1822 "sub%-%/ %R1,%R2,%0" 1823 [(set_attr "type" "fadd") 1824 (set_attr "trap" "yes") 1825 (set_attr "round_suffix" "normal") 1826 (set_attr "trap_suffix" "u_su_sui")]) 1827 1828(define_insn "*subdf_ext3" 1829 [(set (match_operand:DF 0 "register_operand" "=f") 1830 (minus:DF (float_extend:DF 1831 (match_operand:SF 1 "reg_or_0_operand" "fG")) 1832 (float_extend:DF 1833 (match_operand:SF 2 "reg_or_0_operand" "fG"))))] 1834 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 1835 "sub%-%/ %R1,%R2,%0" 1836 [(set_attr "type" "fadd") 1837 (set_attr "trap" "yes") 1838 (set_attr "round_suffix" "normal") 1839 (set_attr "trap_suffix" "u_su_sui")]) 1840 1841(define_expand "subtf3" 1842 [(use (match_operand:TF 0 "register_operand")) 1843 (use (match_operand:TF 1 "general_operand")) 1844 (use (match_operand:TF 2 "general_operand"))] 1845 "TARGET_HAS_XFLOATING_LIBS" 1846 "alpha_emit_xfloating_arith (MINUS, operands); DONE;") 1847 1848(define_insn "mul<mode>3" 1849 [(set (match_operand:FMODE 0 "register_operand" "=f,&f") 1850 (mult:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "%fG,fG") 1851 (match_operand:FMODE 2 "reg_or_0_operand" "fG,fG")))] 1852 "TARGET_FP" 1853 "mul<modesuffix>%/ %R1,%R2,%0" 1854 [(set_attr "type" "fmul") 1855 (set_attr "trap" "yes") 1856 (set_attr "round_suffix" "normal") 1857 (set_attr "trap_suffix" "u_su_sui") 1858 (set (attr "enabled") 1859 (cond [(eq_attr "alternative" "0") 1860 (symbol_ref "alpha_fptm < ALPHA_FPTM_SU") 1861 ] 1862 (symbol_ref "true")))]) 1863 1864(define_insn "*muldf_ext1" 1865 [(set (match_operand:DF 0 "register_operand" "=f") 1866 (mult:DF (float_extend:DF 1867 (match_operand:SF 1 "reg_or_0_operand" "fG")) 1868 (match_operand:DF 2 "reg_or_0_operand" "fG")))] 1869 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 1870 "mul%-%/ %R1,%R2,%0" 1871 [(set_attr "type" "fmul") 1872 (set_attr "trap" "yes") 1873 (set_attr "round_suffix" "normal") 1874 (set_attr "trap_suffix" "u_su_sui")]) 1875 1876(define_insn "*muldf_ext2" 1877 [(set (match_operand:DF 0 "register_operand" "=f") 1878 (mult:DF (float_extend:DF 1879 (match_operand:SF 1 "reg_or_0_operand" "%fG")) 1880 (float_extend:DF 1881 (match_operand:SF 2 "reg_or_0_operand" "fG"))))] 1882 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 1883 "mul%-%/ %R1,%R2,%0" 1884 [(set_attr "type" "fmul") 1885 (set_attr "trap" "yes") 1886 (set_attr "round_suffix" "normal") 1887 (set_attr "trap_suffix" "u_su_sui")]) 1888 1889(define_expand "multf3" 1890 [(use (match_operand:TF 0 "register_operand")) 1891 (use (match_operand:TF 1 "general_operand")) 1892 (use (match_operand:TF 2 "general_operand"))] 1893 "TARGET_HAS_XFLOATING_LIBS" 1894 "alpha_emit_xfloating_arith (MULT, operands); DONE;") 1895 1896(define_insn "div<mode>3" 1897 [(set (match_operand:FMODE 0 "register_operand" "=f,&f") 1898 (div:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG,fG") 1899 (match_operand:FMODE 2 "reg_or_0_operand" "fG,fG")))] 1900 "TARGET_FP" 1901 "div<modesuffix>%/ %R1,%R2,%0" 1902 [(set_attr "type" "fdiv") 1903 (set_attr "opsize" "<opmode>") 1904 (set_attr "trap" "yes") 1905 (set_attr "round_suffix" "normal") 1906 (set_attr "trap_suffix" "u_su_sui") 1907 (set (attr "enabled") 1908 (cond [(eq_attr "alternative" "0") 1909 (symbol_ref "alpha_fptm < ALPHA_FPTM_SU") 1910 ] 1911 (symbol_ref "true")))]) 1912 1913(define_insn "*divdf_ext1" 1914 [(set (match_operand:DF 0 "register_operand" "=f") 1915 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG")) 1916 (match_operand:DF 2 "reg_or_0_operand" "fG")))] 1917 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 1918 "div%-%/ %R1,%R2,%0" 1919 [(set_attr "type" "fdiv") 1920 (set_attr "trap" "yes") 1921 (set_attr "round_suffix" "normal") 1922 (set_attr "trap_suffix" "u_su_sui")]) 1923 1924(define_insn "*divdf_ext2" 1925 [(set (match_operand:DF 0 "register_operand" "=f") 1926 (div:DF (match_operand:DF 1 "reg_or_0_operand" "fG") 1927 (float_extend:DF 1928 (match_operand:SF 2 "reg_or_0_operand" "fG"))))] 1929 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 1930 "div%-%/ %R1,%R2,%0" 1931 [(set_attr "type" "fdiv") 1932 (set_attr "trap" "yes") 1933 (set_attr "round_suffix" "normal") 1934 (set_attr "trap_suffix" "u_su_sui")]) 1935 1936(define_insn "*divdf_ext3" 1937 [(set (match_operand:DF 0 "register_operand" "=f") 1938 (div:DF (float_extend:DF 1939 (match_operand:SF 1 "reg_or_0_operand" "fG")) 1940 (float_extend:DF 1941 (match_operand:SF 2 "reg_or_0_operand" "fG"))))] 1942 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 1943 "div%-%/ %R1,%R2,%0" 1944 [(set_attr "type" "fdiv") 1945 (set_attr "trap" "yes") 1946 (set_attr "round_suffix" "normal") 1947 (set_attr "trap_suffix" "u_su_sui")]) 1948 1949(define_expand "divtf3" 1950 [(use (match_operand:TF 0 "register_operand")) 1951 (use (match_operand:TF 1 "general_operand")) 1952 (use (match_operand:TF 2 "general_operand"))] 1953 "TARGET_HAS_XFLOATING_LIBS" 1954 "alpha_emit_xfloating_arith (DIV, operands); DONE;") 1955 1956(define_insn "sqrt<mode>2" 1957 [(set (match_operand:FMODE 0 "register_operand" "=f,&f") 1958 (sqrt:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG,fG")))] 1959 "TARGET_FP && TARGET_FIX" 1960 "sqrt<modesuffix>%/ %R1,%0" 1961 [(set_attr "type" "fsqrt") 1962 (set_attr "opsize" "<opmode>") 1963 (set_attr "trap" "yes") 1964 (set_attr "round_suffix" "normal") 1965 (set_attr "trap_suffix" "u_su_sui") 1966 (set (attr "enabled") 1967 (cond [(eq_attr "alternative" "0") 1968 (symbol_ref "alpha_fptm < ALPHA_FPTM_SU") 1969 ] 1970 (symbol_ref "true")))]) 1971 1972;; Define conversion operators between DFmode and SImode, using the cvtql 1973;; instruction. To allow combine et al to do useful things, we keep the 1974;; operation as a unit until after reload, at which point we split the 1975;; instructions. 1976;; 1977;; Note that we (attempt to) only consider this optimization when the 1978;; ultimate destination is memory. If we will be doing further integer 1979;; processing, it is cheaper to do the truncation in the int regs. 1980 1981(define_insn "*cvtql" 1982 [(set (match_operand:SF 0 "register_operand" "=f") 1983 (unspec:SF [(match_operand:DI 1 "reg_or_0_operand" "fG")] 1984 UNSPEC_CVTQL))] 1985 "TARGET_FP" 1986 "cvtql%/ %R1,%0" 1987 [(set_attr "type" "fadd") 1988 (set_attr "trap" "yes") 1989 (set_attr "trap_suffix" "v_sv")]) 1990 1991(define_insn_and_split "*fix_truncdfsi_ieee" 1992 [(set (match_operand:SI 0 "memory_operand" "=m") 1993 (subreg:SI 1994 (match_operator:DI 4 "fix_operator" 1995 [(match_operand:DF 1 "reg_or_0_operand" "fG")]) 0)) 1996 (clobber (match_scratch:DI 2 "=&f")) 1997 (clobber (match_scratch:SF 3 "=&f"))] 1998 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" 1999 "#" 2000 "&& reload_completed" 2001 [(set (match_dup 2) (match_op_dup 4 [(match_dup 1)])) 2002 (set (match_dup 3) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL)) 2003 (set (match_dup 5) (match_dup 3))] 2004{ 2005 operands[5] = adjust_address (operands[0], SFmode, 0); 2006} 2007 [(set_attr "type" "fadd") 2008 (set_attr "trap" "yes")]) 2009 2010(define_insn_and_split "*fix_truncdfsi_internal" 2011 [(set (match_operand:SI 0 "memory_operand" "=m") 2012 (subreg:SI 2013 (match_operator:DI 3 "fix_operator" 2014 [(match_operand:DF 1 "reg_or_0_operand" "fG")]) 0)) 2015 (clobber (match_scratch:DI 2 "=f"))] 2016 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2017 "#" 2018 "&& reload_completed" 2019 [(set (match_dup 2) (match_op_dup 3 [(match_dup 1)])) 2020 (set (match_dup 4) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL)) 2021 (set (match_dup 5) (match_dup 4))] 2022{ 2023 operands[4] = gen_rtx_REG (SFmode, REGNO (operands[2])); 2024 operands[5] = adjust_address (operands[0], SFmode, 0); 2025} 2026 [(set_attr "type" "fadd") 2027 (set_attr "trap" "yes")]) 2028 2029(define_insn "*fix_truncdfdi2" 2030 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f,&f") 2031 (match_operator:DI 2 "fix_operator" 2032 [(match_operand:DF 1 "reg_or_0_operand" "fG,fG")]))] 2033 "TARGET_FP" 2034 "cvt%-q%/ %R1,%0" 2035 [(set_attr "type" "fadd") 2036 (set_attr "trap" "yes") 2037 (set_attr "round_suffix" "c") 2038 (set_attr "trap_suffix" "v_sv_svi") 2039 (set (attr "enabled") 2040 (cond [(eq_attr "alternative" "0") 2041 (symbol_ref "alpha_fptm < ALPHA_FPTM_SU") 2042 ] 2043 (symbol_ref "true")))]) 2044 2045(define_expand "fix_truncdfdi2" 2046 [(set (match_operand:DI 0 "reg_no_subreg_operand") 2047 (fix:DI (match_operand:DF 1 "reg_or_0_operand")))] 2048 "TARGET_FP") 2049 2050(define_expand "fixuns_truncdfdi2" 2051 [(set (match_operand:DI 0 "reg_no_subreg_operand") 2052 (unsigned_fix:DI (match_operand:DF 1 "reg_or_0_operand")))] 2053 "TARGET_FP") 2054 2055;; Likewise between SFmode and SImode. 2056 2057(define_insn_and_split "*fix_truncsfsi_ieee" 2058 [(set (match_operand:SI 0 "memory_operand" "=m") 2059 (subreg:SI 2060 (match_operator:DI 4 "fix_operator" 2061 [(float_extend:DF 2062 (match_operand:SF 1 "reg_or_0_operand" "fG"))]) 0)) 2063 (clobber (match_scratch:DI 2 "=&f")) 2064 (clobber (match_scratch:SF 3 "=&f"))] 2065 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" 2066 "#" 2067 "&& reload_completed" 2068 [(set (match_dup 2) (match_op_dup 4 [(float_extend:DF (match_dup 1))])) 2069 (set (match_dup 3) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL)) 2070 (set (match_dup 5) (match_dup 3))] 2071 "operands[5] = adjust_address (operands[0], SFmode, 0);" 2072 [(set_attr "type" "fadd") 2073 (set_attr "trap" "yes")]) 2074 2075(define_insn_and_split "*fix_truncsfsi_internal" 2076 [(set (match_operand:SI 0 "memory_operand" "=m") 2077 (subreg:SI 2078 (match_operator:DI 3 "fix_operator" 2079 [(float_extend:DF 2080 (match_operand:SF 1 "reg_or_0_operand" "fG"))]) 0)) 2081 (clobber (match_scratch:DI 2 "=f"))] 2082 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2083 "#" 2084 "&& reload_completed" 2085 [(set (match_dup 2) (match_op_dup 3 [(float_extend:DF (match_dup 1))])) 2086 (set (match_dup 4) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL)) 2087 (set (match_dup 5) (match_dup 4))] 2088{ 2089 operands[4] = gen_rtx_REG (SFmode, REGNO (operands[2])); 2090 operands[5] = adjust_address (operands[0], SFmode, 0); 2091} 2092 [(set_attr "type" "fadd") 2093 (set_attr "trap" "yes")]) 2094 2095(define_insn "*fix_truncsfdi2" 2096 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f,&f") 2097 (match_operator:DI 2 "fix_operator" 2098 [(float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG,fG"))]))] 2099 "TARGET_FP" 2100 "cvt%-q%/ %R1,%0" 2101 [(set_attr "type" "fadd") 2102 (set_attr "trap" "yes") 2103 (set_attr "round_suffix" "c") 2104 (set_attr "trap_suffix" "v_sv_svi") 2105 (set (attr "enabled") 2106 (cond [(eq_attr "alternative" "0") 2107 (symbol_ref "alpha_fptm < ALPHA_FPTM_SU") 2108 ] 2109 (symbol_ref "true")))]) 2110 2111(define_expand "fix_truncsfdi2" 2112 [(set (match_operand:DI 0 "reg_no_subreg_operand") 2113 (fix:DI (float_extend:DF (match_operand:SF 1 "reg_or_0_operand"))))] 2114 "TARGET_FP") 2115 2116(define_expand "fixuns_truncsfdi2" 2117 [(set (match_operand:DI 0 "reg_no_subreg_operand") 2118 (unsigned_fix:DI 2119 (float_extend:DF (match_operand:SF 1 "reg_or_0_operand"))))] 2120 "TARGET_FP") 2121 2122(define_expand "fix_trunctfdi2" 2123 [(use (match_operand:DI 0 "register_operand")) 2124 (use (match_operand:TF 1 "general_operand"))] 2125 "TARGET_HAS_XFLOATING_LIBS" 2126 "alpha_emit_xfloating_cvt (FIX, operands); DONE;") 2127 2128(define_expand "fixuns_trunctfdi2" 2129 [(use (match_operand:DI 0 "register_operand")) 2130 (use (match_operand:TF 1 "general_operand"))] 2131 "TARGET_HAS_XFLOATING_LIBS" 2132 "alpha_emit_xfloating_cvt (UNSIGNED_FIX, operands); DONE;") 2133 2134(define_insn "floatdisf2" 2135 [(set (match_operand:SF 0 "register_operand" "=f,&f") 2136 (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f,f")))] 2137 "TARGET_FP" 2138 "cvtq%,%/ %1,%0" 2139 [(set_attr "type" "fadd") 2140 (set_attr "trap" "yes") 2141 (set_attr "round_suffix" "normal") 2142 (set_attr "trap_suffix" "sui") 2143 (set (attr "enabled") 2144 (cond [(eq_attr "alternative" "0") 2145 (symbol_ref "alpha_fptm < ALPHA_FPTM_SU") 2146 ] 2147 (symbol_ref "true")))]) 2148 2149(define_insn_and_split "*floatsisf2_ieee" 2150 [(set (match_operand:SF 0 "register_operand" "=&f") 2151 (float:SF (match_operand:SI 1 "memory_operand" "m"))) 2152 (clobber (match_scratch:DI 2 "=&f")) 2153 (clobber (match_scratch:SF 3 "=&f"))] 2154 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" 2155 "#" 2156 "&& reload_completed" 2157 [(set (match_dup 3) (match_dup 1)) 2158 (set (match_dup 2) (unspec:DI [(match_dup 3)] UNSPEC_CVTLQ)) 2159 (set (match_dup 0) (float:SF (match_dup 2)))] 2160 "operands[1] = adjust_address (operands[1], SFmode, 0);") 2161 2162(define_insn_and_split "*floatsisf2" 2163 [(set (match_operand:SF 0 "register_operand" "=f") 2164 (float:SF (match_operand:SI 1 "memory_operand" "m")))] 2165 "TARGET_FP" 2166 "#" 2167 "&& reload_completed" 2168 [(set (match_dup 0) (match_dup 1)) 2169 (set (match_dup 2) (unspec:DI [(match_dup 0)] UNSPEC_CVTLQ)) 2170 (set (match_dup 0) (float:SF (match_dup 2)))] 2171{ 2172 operands[1] = adjust_address (operands[1], SFmode, 0); 2173 operands[2] = gen_rtx_REG (DImode, REGNO (operands[0])); 2174}) 2175 2176(define_insn "floatdidf2" 2177 [(set (match_operand:DF 0 "register_operand" "=f,&f") 2178 (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f,f")))] 2179 "TARGET_FP" 2180 "cvtq%-%/ %1,%0" 2181 [(set_attr "type" "fadd") 2182 (set_attr "trap" "yes") 2183 (set_attr "round_suffix" "normal") 2184 (set_attr "trap_suffix" "sui") 2185 (set (attr "enabled") 2186 (cond [(eq_attr "alternative" "0") 2187 (symbol_ref "alpha_fptm < ALPHA_FPTM_SU") 2188 ] 2189 (symbol_ref "true")))]) 2190 2191(define_insn_and_split "*floatsidf2_ieee" 2192 [(set (match_operand:DF 0 "register_operand" "=&f") 2193 (float:DF (match_operand:SI 1 "memory_operand" "m"))) 2194 (clobber (match_scratch:DI 2 "=&f")) 2195 (clobber (match_scratch:SF 3 "=&f"))] 2196 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" 2197 "#" 2198 "&& reload_completed" 2199 [(set (match_dup 3) (match_dup 1)) 2200 (set (match_dup 2) (unspec:DI [(match_dup 3)] UNSPEC_CVTLQ)) 2201 (set (match_dup 0) (float:DF (match_dup 2)))] 2202 "operands[1] = adjust_address (operands[1], SFmode, 0);") 2203 2204(define_insn_and_split "*floatsidf2" 2205 [(set (match_operand:DF 0 "register_operand" "=f") 2206 (float:DF (match_operand:SI 1 "memory_operand" "m")))] 2207 "TARGET_FP" 2208 "#" 2209 "&& reload_completed" 2210 [(set (match_dup 3) (match_dup 1)) 2211 (set (match_dup 2) (unspec:DI [(match_dup 3)] UNSPEC_CVTLQ)) 2212 (set (match_dup 0) (float:DF (match_dup 2)))] 2213{ 2214 operands[1] = adjust_address (operands[1], SFmode, 0); 2215 operands[2] = gen_rtx_REG (DImode, REGNO (operands[0])); 2216 operands[3] = gen_rtx_REG (SFmode, REGNO (operands[0])); 2217}) 2218 2219(define_expand "floatditf2" 2220 [(use (match_operand:TF 0 "register_operand")) 2221 (use (match_operand:DI 1 "general_operand"))] 2222 "TARGET_HAS_XFLOATING_LIBS" 2223 "alpha_emit_xfloating_cvt (FLOAT, operands); DONE;") 2224 2225(define_expand "floatunsdisf2" 2226 [(use (match_operand:SF 0 "register_operand")) 2227 (use (match_operand:DI 1 "register_operand"))] 2228 "TARGET_FP" 2229 "alpha_emit_floatuns (operands); DONE;") 2230 2231(define_expand "floatunsdidf2" 2232 [(use (match_operand:DF 0 "register_operand")) 2233 (use (match_operand:DI 1 "register_operand"))] 2234 "TARGET_FP" 2235 "alpha_emit_floatuns (operands); DONE;") 2236 2237(define_expand "floatunsditf2" 2238 [(use (match_operand:TF 0 "register_operand")) 2239 (use (match_operand:DI 1 "general_operand"))] 2240 "TARGET_HAS_XFLOATING_LIBS" 2241 "alpha_emit_xfloating_cvt (UNSIGNED_FLOAT, operands); DONE;") 2242 2243(define_expand "extendsfdf2" 2244 [(set (match_operand:DF 0 "register_operand") 2245 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand")))] 2246 "TARGET_FP" 2247{ 2248 if (alpha_fptm >= ALPHA_FPTM_SU) 2249 operands[1] = force_reg (SFmode, operands[1]); 2250}) 2251 2252;; The Unicos/Mk assembler doesn't support cvtst, but we've already 2253;; asserted that alpha_fptm == ALPHA_FPTM_N. 2254 2255(define_insn "*extendsfdf2_ieee" 2256 [(set (match_operand:DF 0 "register_operand" "=&f") 2257 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))] 2258 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" 2259 "cvtsts %1,%0" 2260 [(set_attr "type" "fadd") 2261 (set_attr "trap" "yes")]) 2262 2263(define_insn "*extendsfdf2_internal" 2264 [(set (match_operand:DF 0 "register_operand" "=f,f,m") 2265 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m,f")))] 2266 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2267 "@ 2268 cpys %1,%1,%0 2269 ld%, %0,%1 2270 st%- %1,%0" 2271 [(set_attr "type" "fcpys,fld,fst")]) 2272 2273;; Use register_operand for operand 1 to prevent compress_float_constant 2274;; from doing something silly. When optimizing we'll put things back 2275;; together anyway. 2276(define_expand "extendsftf2" 2277 [(use (match_operand:TF 0 "register_operand")) 2278 (use (match_operand:SF 1 "register_operand"))] 2279 "TARGET_HAS_XFLOATING_LIBS" 2280{ 2281 rtx tmp = gen_reg_rtx (DFmode); 2282 emit_insn (gen_extendsfdf2 (tmp, operands[1])); 2283 emit_insn (gen_extenddftf2 (operands[0], tmp)); 2284 DONE; 2285}) 2286 2287(define_expand "extenddftf2" 2288 [(use (match_operand:TF 0 "register_operand")) 2289 (use (match_operand:DF 1 "register_operand"))] 2290 "TARGET_HAS_XFLOATING_LIBS" 2291 "alpha_emit_xfloating_cvt (FLOAT_EXTEND, operands); DONE;") 2292 2293(define_insn "truncdfsf2" 2294 [(set (match_operand:SF 0 "register_operand" "=f,&f") 2295 (float_truncate:SF (match_operand:DF 1 "reg_or_0_operand" "fG,fG")))] 2296 "TARGET_FP" 2297 "cvt%-%,%/ %R1,%0" 2298 [(set_attr "type" "fadd") 2299 (set_attr "trap" "yes") 2300 (set_attr "round_suffix" "normal") 2301 (set_attr "trap_suffix" "u_su_sui") 2302 (set (attr "enabled") 2303 (cond [(eq_attr "alternative" "0") 2304 (symbol_ref "alpha_fptm < ALPHA_FPTM_SU") 2305 ] 2306 (symbol_ref "true")))]) 2307 2308(define_expand "trunctfdf2" 2309 [(use (match_operand:DF 0 "register_operand")) 2310 (use (match_operand:TF 1 "general_operand"))] 2311 "TARGET_HAS_XFLOATING_LIBS" 2312 "alpha_emit_xfloating_cvt (FLOAT_TRUNCATE, operands); DONE;") 2313 2314(define_expand "trunctfsf2" 2315 [(use (match_operand:SF 0 "register_operand")) 2316 (use (match_operand:TF 1 "general_operand"))] 2317 "TARGET_FP && TARGET_HAS_XFLOATING_LIBS" 2318{ 2319 rtx tmpf, sticky, arg, lo, hi; 2320 2321 tmpf = gen_reg_rtx (DFmode); 2322 sticky = gen_reg_rtx (DImode); 2323 arg = copy_to_mode_reg (TFmode, operands[1]); 2324 lo = gen_lowpart (DImode, arg); 2325 hi = gen_highpart (DImode, arg); 2326 2327 /* Convert the low word of the TFmode value into a sticky rounding bit, 2328 then or it into the low bit of the high word. This leaves the sticky 2329 bit at bit 48 of the fraction, which is representable in DFmode, 2330 which prevents rounding error in the final conversion to SFmode. */ 2331 2332 emit_insn (gen_rtx_SET (sticky, gen_rtx_NE (DImode, lo, const0_rtx))); 2333 emit_insn (gen_iordi3 (hi, hi, sticky)); 2334 emit_insn (gen_trunctfdf2 (tmpf, arg)); 2335 emit_insn (gen_truncdfsf2 (operands[0], tmpf)); 2336 DONE; 2337}) 2338 2339;; Next are all the integer comparisons, and conditional moves and branches 2340;; and some of the related define_expand's and define_split's. 2341 2342(define_insn "*setcc_internal" 2343 [(set (match_operand 0 "register_operand" "=r") 2344 (match_operator 1 "alpha_comparison_operator" 2345 [(match_operand:DI 2 "register_operand" "r") 2346 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]))] 2347 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT 2348 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8 2349 && GET_MODE (operands[0]) == GET_MODE (operands[1])" 2350 "cmp%C1 %2,%3,%0" 2351 [(set_attr "type" "icmp")]) 2352 2353;; Yes, we can technically support reg_or_8bit_operand in operand 2, 2354;; but that's non-canonical rtl and allowing that causes inefficiencies 2355;; from cse on. 2356(define_insn "*setcc_swapped_internal" 2357 [(set (match_operand 0 "register_operand" "=r") 2358 (match_operator 1 "alpha_swapped_comparison_operator" 2359 [(match_operand:DI 2 "register_operand" "r") 2360 (match_operand:DI 3 "reg_or_0_operand" "rJ")]))] 2361 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT 2362 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8 2363 && GET_MODE (operands[0]) == GET_MODE (operands[1])" 2364 "cmp%c1 %r3,%2,%0" 2365 [(set_attr "type" "icmp")]) 2366 2367;; Use match_operator rather than ne directly so that we can match 2368;; multiple integer modes. 2369(define_insn "*setne_internal" 2370 [(set (match_operand 0 "register_operand" "=r") 2371 (match_operator 1 "signed_comparison_operator" 2372 [(match_operand:DI 2 "register_operand" "r") 2373 (const_int 0)]))] 2374 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT 2375 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8 2376 && GET_CODE (operands[1]) == NE 2377 && GET_MODE (operands[0]) == GET_MODE (operands[1])" 2378 "cmpult $31,%2,%0" 2379 [(set_attr "type" "icmp")]) 2380 2381;; The mode folding trick can't be used with const_int operands, since 2382;; reload needs to know the proper mode. 2383;; 2384;; Use add_operand instead of the more seemingly natural reg_or_8bit_operand 2385;; in order to create more pairs of constants. As long as we're allowing 2386;; two constants at the same time, and will have to reload one of them... 2387 2388(define_insn "*mov<mode>cc_internal" 2389 [(set (match_operand:IMODE 0 "register_operand" "=r,r,r,r") 2390 (if_then_else:IMODE 2391 (match_operator 2 "signed_comparison_operator" 2392 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J") 2393 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")]) 2394 (match_operand:IMODE 1 "add_operand" "rI,0,rI,0") 2395 (match_operand:IMODE 5 "add_operand" "0,rI,0,rI")))] 2396 "(operands[3] == const0_rtx) ^ (operands[4] == const0_rtx)" 2397 "@ 2398 cmov%C2 %r3,%1,%0 2399 cmov%D2 %r3,%5,%0 2400 cmov%c2 %r4,%1,%0 2401 cmov%d2 %r4,%5,%0" 2402 [(set_attr "type" "icmov")]) 2403 2404(define_insn "*mov<mode>cc_lbc" 2405 [(set (match_operand:IMODE 0 "register_operand" "=r,r") 2406 (if_then_else:IMODE 2407 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ") 2408 (const_int 1) 2409 (const_int 0)) 2410 (const_int 0)) 2411 (match_operand:IMODE 1 "reg_or_8bit_operand" "rI,0") 2412 (match_operand:IMODE 3 "reg_or_8bit_operand" "0,rI")))] 2413 "" 2414 "@ 2415 cmovlbc %r2,%1,%0 2416 cmovlbs %r2,%3,%0" 2417 [(set_attr "type" "icmov")]) 2418 2419(define_insn "*mov<mode>cc_lbs" 2420 [(set (match_operand:IMODE 0 "register_operand" "=r,r") 2421 (if_then_else:IMODE 2422 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ") 2423 (const_int 1) 2424 (const_int 0)) 2425 (const_int 0)) 2426 (match_operand:IMODE 1 "reg_or_8bit_operand" "rI,0") 2427 (match_operand:IMODE 3 "reg_or_8bit_operand" "0,rI")))] 2428 "" 2429 "@ 2430 cmovlbs %r2,%1,%0 2431 cmovlbc %r2,%3,%0" 2432 [(set_attr "type" "icmov")]) 2433 2434;; For ABS, we have two choices, depending on whether the input and output 2435;; registers are the same or not. 2436(define_expand "absdi2" 2437 [(set (match_operand:DI 0 "register_operand") 2438 (abs:DI (match_operand:DI 1 "register_operand")))] 2439 "" 2440{ 2441 if (rtx_equal_p (operands[0], operands[1])) 2442 emit_insn (gen_absdi2_same (operands[0], gen_reg_rtx (DImode))); 2443 else 2444 emit_insn (gen_absdi2_diff (operands[0], operands[1])); 2445 DONE; 2446}) 2447 2448(define_expand "absdi2_same" 2449 [(set (match_operand:DI 1 "register_operand") 2450 (neg:DI (match_operand:DI 0 "register_operand"))) 2451 (set (match_dup 0) 2452 (if_then_else:DI (ge (match_dup 0) (const_int 0)) 2453 (match_dup 0) 2454 (match_dup 1)))]) 2455 2456(define_expand "absdi2_diff" 2457 [(set (match_operand:DI 0 "register_operand") 2458 (neg:DI (match_operand:DI 1 "register_operand"))) 2459 (set (match_dup 0) 2460 (if_then_else:DI (lt (match_dup 1) (const_int 0)) 2461 (match_dup 0) 2462 (match_dup 1)))]) 2463 2464(define_split 2465 [(set (match_operand:DI 0 "register_operand") 2466 (abs:DI (match_dup 0))) 2467 (clobber (match_operand:DI 1 "register_operand"))] 2468 "" 2469 [(set (match_dup 1) (neg:DI (match_dup 0))) 2470 (set (match_dup 0) (if_then_else:DI (ge (match_dup 0) (const_int 0)) 2471 (match_dup 0) (match_dup 1)))]) 2472 2473(define_split 2474 [(set (match_operand:DI 0 "register_operand") 2475 (abs:DI (match_operand:DI 1 "register_operand")))] 2476 "! rtx_equal_p (operands[0], operands[1])" 2477 [(set (match_dup 0) (neg:DI (match_dup 1))) 2478 (set (match_dup 0) (if_then_else:DI (lt (match_dup 1) (const_int 0)) 2479 (match_dup 0) (match_dup 1)))]) 2480 2481(define_split 2482 [(set (match_operand:DI 0 "register_operand") 2483 (neg:DI (abs:DI (match_dup 0)))) 2484 (clobber (match_operand:DI 1 "register_operand"))] 2485 "" 2486 [(set (match_dup 1) (neg:DI (match_dup 0))) 2487 (set (match_dup 0) (if_then_else:DI (le (match_dup 0) (const_int 0)) 2488 (match_dup 0) (match_dup 1)))]) 2489 2490(define_split 2491 [(set (match_operand:DI 0 "register_operand") 2492 (neg:DI (abs:DI (match_operand:DI 1 "register_operand"))))] 2493 "! rtx_equal_p (operands[0], operands[1])" 2494 [(set (match_dup 0) (neg:DI (match_dup 1))) 2495 (set (match_dup 0) (if_then_else:DI (gt (match_dup 1) (const_int 0)) 2496 (match_dup 0) (match_dup 1)))]) 2497 2498(define_insn "<code><mode>3" 2499 [(set (match_operand:I12MODE 0 "register_operand" "=r") 2500 (any_maxmin:I12MODE 2501 (match_operand:I12MODE 1 "reg_or_0_operand" "%rJ") 2502 (match_operand:I12MODE 2 "reg_or_8bit_operand" "rI")))] 2503 "TARGET_MAX" 2504 "<maxmin><vecmodesuffix> %r1,%2,%0" 2505 [(set_attr "type" "mvi")]) 2506 2507(define_expand "smaxdi3" 2508 [(set (match_dup 3) 2509 (le:DI (match_operand:DI 1 "reg_or_0_operand") 2510 (match_operand:DI 2 "reg_or_8bit_operand"))) 2511 (set (match_operand:DI 0 "register_operand") 2512 (if_then_else:DI (eq (match_dup 3) (const_int 0)) 2513 (match_dup 1) (match_dup 2)))] 2514 "" 2515 "operands[3] = gen_reg_rtx (DImode);") 2516 2517(define_split 2518 [(set (match_operand:DI 0 "register_operand") 2519 (smax:DI (match_operand:DI 1 "reg_or_0_operand") 2520 (match_operand:DI 2 "reg_or_8bit_operand"))) 2521 (clobber (match_operand:DI 3 "register_operand"))] 2522 "operands[2] != const0_rtx" 2523 [(set (match_dup 3) (le:DI (match_dup 1) (match_dup 2))) 2524 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0)) 2525 (match_dup 1) (match_dup 2)))]) 2526 2527(define_insn "*smax_const0" 2528 [(set (match_operand:DI 0 "register_operand" "=r") 2529 (smax:DI (match_operand:DI 1 "register_operand" "0") 2530 (const_int 0)))] 2531 "" 2532 "cmovlt %0,0,%0" 2533 [(set_attr "type" "icmov")]) 2534 2535(define_expand "smindi3" 2536 [(set (match_dup 3) 2537 (lt:DI (match_operand:DI 1 "reg_or_0_operand") 2538 (match_operand:DI 2 "reg_or_8bit_operand"))) 2539 (set (match_operand:DI 0 "register_operand") 2540 (if_then_else:DI (ne (match_dup 3) (const_int 0)) 2541 (match_dup 1) (match_dup 2)))] 2542 "" 2543 "operands[3] = gen_reg_rtx (DImode);") 2544 2545(define_split 2546 [(set (match_operand:DI 0 "register_operand") 2547 (smin:DI (match_operand:DI 1 "reg_or_0_operand") 2548 (match_operand:DI 2 "reg_or_8bit_operand"))) 2549 (clobber (match_operand:DI 3 "register_operand"))] 2550 "operands[2] != const0_rtx" 2551 [(set (match_dup 3) (lt:DI (match_dup 1) (match_dup 2))) 2552 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0)) 2553 (match_dup 1) (match_dup 2)))]) 2554 2555(define_insn "*smin_const0" 2556 [(set (match_operand:DI 0 "register_operand" "=r") 2557 (smin:DI (match_operand:DI 1 "register_operand" "0") 2558 (const_int 0)))] 2559 "" 2560 "cmovgt %0,0,%0" 2561 [(set_attr "type" "icmov")]) 2562 2563(define_expand "umaxdi3" 2564 [(set (match_dup 3) 2565 (leu:DI (match_operand:DI 1 "reg_or_0_operand") 2566 (match_operand:DI 2 "reg_or_8bit_operand"))) 2567 (set (match_operand:DI 0 "register_operand") 2568 (if_then_else:DI (eq (match_dup 3) (const_int 0)) 2569 (match_dup 1) (match_dup 2)))] 2570 "" 2571 "operands[3] = gen_reg_rtx (DImode);") 2572 2573(define_split 2574 [(set (match_operand:DI 0 "register_operand") 2575 (umax:DI (match_operand:DI 1 "reg_or_0_operand") 2576 (match_operand:DI 2 "reg_or_8bit_operand"))) 2577 (clobber (match_operand:DI 3 "register_operand"))] 2578 "operands[2] != const0_rtx" 2579 [(set (match_dup 3) (leu:DI (match_dup 1) (match_dup 2))) 2580 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0)) 2581 (match_dup 1) (match_dup 2)))]) 2582 2583(define_expand "umindi3" 2584 [(set (match_dup 3) 2585 (ltu:DI (match_operand:DI 1 "reg_or_0_operand") 2586 (match_operand:DI 2 "reg_or_8bit_operand"))) 2587 (set (match_operand:DI 0 "register_operand") 2588 (if_then_else:DI (ne (match_dup 3) (const_int 0)) 2589 (match_dup 1) (match_dup 2)))] 2590 "" 2591 "operands[3] = gen_reg_rtx (DImode);") 2592 2593(define_split 2594 [(set (match_operand:DI 0 "register_operand") 2595 (umin:DI (match_operand:DI 1 "reg_or_0_operand") 2596 (match_operand:DI 2 "reg_or_8bit_operand"))) 2597 (clobber (match_operand:DI 3 "register_operand"))] 2598 "operands[2] != const0_rtx" 2599 [(set (match_dup 3) (ltu:DI (match_dup 1) (match_dup 2))) 2600 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0)) 2601 (match_dup 1) (match_dup 2)))]) 2602 2603(define_insn "*bcc_normal" 2604 [(set (pc) 2605 (if_then_else 2606 (match_operator 1 "signed_comparison_operator" 2607 [(match_operand:DI 2 "reg_or_0_operand" "rJ") 2608 (const_int 0)]) 2609 (label_ref (match_operand 0)) 2610 (pc)))] 2611 "" 2612 "b%C1 %r2,%0" 2613 [(set_attr "type" "ibr")]) 2614 2615(define_insn "*bcc_reverse" 2616 [(set (pc) 2617 (if_then_else 2618 (match_operator 1 "signed_comparison_operator" 2619 [(match_operand:DI 2 "register_operand" "r") 2620 (const_int 0)]) 2621 2622 (pc) 2623 (label_ref (match_operand 0))))] 2624 "" 2625 "b%c1 %2,%0" 2626 [(set_attr "type" "ibr")]) 2627 2628(define_insn "*blbs_normal" 2629 [(set (pc) 2630 (if_then_else 2631 (ne (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 2632 (const_int 1) 2633 (const_int 0)) 2634 (const_int 0)) 2635 (label_ref (match_operand 0)) 2636 (pc)))] 2637 "" 2638 "blbs %r1,%0" 2639 [(set_attr "type" "ibr")]) 2640 2641(define_insn "*blbc_normal" 2642 [(set (pc) 2643 (if_then_else 2644 (eq (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 2645 (const_int 1) 2646 (const_int 0)) 2647 (const_int 0)) 2648 (label_ref (match_operand 0)) 2649 (pc)))] 2650 "" 2651 "blbc %r1,%0" 2652 [(set_attr "type" "ibr")]) 2653 2654(define_split 2655 [(parallel 2656 [(set (pc) 2657 (if_then_else 2658 (match_operator 1 "comparison_operator" 2659 [(zero_extract:DI (match_operand:DI 2 "register_operand") 2660 (const_int 1) 2661 (match_operand:DI 3 "const_int_operand")) 2662 (const_int 0)]) 2663 (label_ref (match_operand 0)) 2664 (pc))) 2665 (clobber (match_operand:DI 4 "register_operand"))])] 2666 "INTVAL (operands[3]) != 0" 2667 [(set (match_dup 4) 2668 (lshiftrt:DI (match_dup 2) (match_dup 3))) 2669 (set (pc) 2670 (if_then_else (match_op_dup 1 2671 [(zero_extract:DI (match_dup 4) 2672 (const_int 1) 2673 (const_int 0)) 2674 (const_int 0)]) 2675 (label_ref (match_dup 0)) 2676 (pc)))] 2677 ) 2678 2679;; The following are the corresponding floating-point insns. Recall 2680;; we need to have variants that expand the arguments from SFmode 2681;; to DFmode. 2682 2683(define_insn "*cmpdf_internal" 2684 [(set (match_operand:DF 0 "register_operand" "=f,&f") 2685 (match_operator:DF 1 "alpha_fp_comparison_operator" 2686 [(match_operand:DF 2 "reg_or_0_operand" "fG,fG") 2687 (match_operand:DF 3 "reg_or_0_operand" "fG,fG")]))] 2688 "TARGET_FP" 2689 "cmp%-%C1%/ %R2,%R3,%0" 2690 [(set_attr "type" "fadd") 2691 (set_attr "trap" "yes") 2692 (set_attr "trap_suffix" "su") 2693 (set (attr "enabled") 2694 (cond [(eq_attr "alternative" "0") 2695 (symbol_ref "alpha_fptm < ALPHA_FPTM_SU") 2696 ] 2697 (symbol_ref "true")))]) 2698 2699(define_insn "*cmpdf_ext1" 2700 [(set (match_operand:DF 0 "register_operand" "=f") 2701 (match_operator:DF 1 "alpha_fp_comparison_operator" 2702 [(float_extend:DF 2703 (match_operand:SF 2 "reg_or_0_operand" "fG")) 2704 (match_operand:DF 3 "reg_or_0_operand" "fG")]))] 2705 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2706 "cmp%-%C1%/ %R2,%R3,%0" 2707 [(set_attr "type" "fadd") 2708 (set_attr "trap" "yes") 2709 (set_attr "trap_suffix" "su")]) 2710 2711(define_insn "*cmpdf_ext2" 2712 [(set (match_operand:DF 0 "register_operand" "=f") 2713 (match_operator:DF 1 "alpha_fp_comparison_operator" 2714 [(match_operand:DF 2 "reg_or_0_operand" "fG") 2715 (float_extend:DF 2716 (match_operand:SF 3 "reg_or_0_operand" "fG"))]))] 2717 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2718 "cmp%-%C1%/ %R2,%R3,%0" 2719 [(set_attr "type" "fadd") 2720 (set_attr "trap" "yes") 2721 (set_attr "trap_suffix" "su")]) 2722 2723(define_insn "*cmpdf_ext3" 2724 [(set (match_operand:DF 0 "register_operand" "=f") 2725 (match_operator:DF 1 "alpha_fp_comparison_operator" 2726 [(float_extend:DF 2727 (match_operand:SF 2 "reg_or_0_operand" "fG")) 2728 (float_extend:DF 2729 (match_operand:SF 3 "reg_or_0_operand" "fG"))]))] 2730 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2731 "cmp%-%C1%/ %R2,%R3,%0" 2732 [(set_attr "type" "fadd") 2733 (set_attr "trap" "yes") 2734 (set_attr "trap_suffix" "su")]) 2735 2736(define_insn "*mov<mode>cc_internal" 2737 [(set (match_operand:FMODE 0 "register_operand" "=f,f") 2738 (if_then_else:FMODE 2739 (match_operator 3 "signed_comparison_operator" 2740 [(match_operand:DF 4 "reg_or_0_operand" "fG,fG") 2741 (match_operand:DF 2 "const0_operand" "G,G")]) 2742 (match_operand:FMODE 1 "reg_or_0_operand" "fG,0") 2743 (match_operand:FMODE 5 "reg_or_0_operand" "0,fG")))] 2744 "TARGET_FP" 2745 "@ 2746 fcmov%C3 %R4,%R1,%0 2747 fcmov%D3 %R4,%R5,%0" 2748 [(set_attr "type" "fcmov")]) 2749 2750(define_insn "*movdfcc_ext1" 2751 [(set (match_operand:DF 0 "register_operand" "=f,f") 2752 (if_then_else:DF 2753 (match_operator 3 "signed_comparison_operator" 2754 [(match_operand:DF 4 "reg_or_0_operand" "fG,fG") 2755 (match_operand:DF 2 "const0_operand" "G,G")]) 2756 (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG,0")) 2757 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))] 2758 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2759 "@ 2760 fcmov%C3 %R4,%R1,%0 2761 fcmov%D3 %R4,%R5,%0" 2762 [(set_attr "type" "fcmov")]) 2763 2764(define_insn "*movdfcc_ext2" 2765 [(set (match_operand:DF 0 "register_operand" "=f,f") 2766 (if_then_else:DF 2767 (match_operator 3 "signed_comparison_operator" 2768 [(float_extend:DF 2769 (match_operand:SF 4 "reg_or_0_operand" "fG,fG")) 2770 (match_operand:DF 2 "const0_operand" "G,G")]) 2771 (match_operand:DF 1 "reg_or_0_operand" "fG,0") 2772 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))] 2773 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2774 "@ 2775 fcmov%C3 %R4,%R1,%0 2776 fcmov%D3 %R4,%R5,%0" 2777 [(set_attr "type" "fcmov")]) 2778 2779(define_insn "*movdfcc_ext3" 2780 [(set (match_operand:SF 0 "register_operand" "=f,f") 2781 (if_then_else:SF 2782 (match_operator 3 "signed_comparison_operator" 2783 [(float_extend:DF 2784 (match_operand:SF 4 "reg_or_0_operand" "fG,fG")) 2785 (match_operand:DF 2 "const0_operand" "G,G")]) 2786 (match_operand:SF 1 "reg_or_0_operand" "fG,0") 2787 (match_operand:SF 5 "reg_or_0_operand" "0,fG")))] 2788 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2789 "@ 2790 fcmov%C3 %R4,%R1,%0 2791 fcmov%D3 %R4,%R5,%0" 2792 [(set_attr "type" "fcmov")]) 2793 2794(define_insn "*movdfcc_ext4" 2795 [(set (match_operand:DF 0 "register_operand" "=f,f") 2796 (if_then_else:DF 2797 (match_operator 3 "signed_comparison_operator" 2798 [(float_extend:DF 2799 (match_operand:SF 4 "reg_or_0_operand" "fG,fG")) 2800 (match_operand:DF 2 "const0_operand" "G,G")]) 2801 (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG,0")) 2802 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))] 2803 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2804 "@ 2805 fcmov%C3 %R4,%R1,%0 2806 fcmov%D3 %R4,%R5,%0" 2807 [(set_attr "type" "fcmov")]) 2808 2809(define_expand "smaxdf3" 2810 [(set (match_dup 3) 2811 (le:DF (match_operand:DF 1 "reg_or_0_operand") 2812 (match_operand:DF 2 "reg_or_0_operand"))) 2813 (set (match_operand:DF 0 "register_operand") 2814 (if_then_else:DF (eq (match_dup 3) (match_dup 4)) 2815 (match_dup 1) (match_dup 2)))] 2816 "TARGET_FP" 2817{ 2818 operands[3] = gen_reg_rtx (DFmode); 2819 operands[4] = CONST0_RTX (DFmode); 2820}) 2821 2822(define_expand "smindf3" 2823 [(set (match_dup 3) 2824 (lt:DF (match_operand:DF 1 "reg_or_0_operand") 2825 (match_operand:DF 2 "reg_or_0_operand"))) 2826 (set (match_operand:DF 0 "register_operand") 2827 (if_then_else:DF (ne (match_dup 3) (match_dup 4)) 2828 (match_dup 1) (match_dup 2)))] 2829 "TARGET_FP" 2830{ 2831 operands[3] = gen_reg_rtx (DFmode); 2832 operands[4] = CONST0_RTX (DFmode); 2833}) 2834 2835(define_expand "smaxsf3" 2836 [(set (match_dup 3) 2837 (le:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand")) 2838 (float_extend:DF (match_operand:SF 2 "reg_or_0_operand")))) 2839 (set (match_operand:SF 0 "register_operand") 2840 (if_then_else:SF (eq (match_dup 3) (match_dup 4)) 2841 (match_dup 1) (match_dup 2)))] 2842 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2843{ 2844 operands[3] = gen_reg_rtx (DFmode); 2845 operands[4] = CONST0_RTX (DFmode); 2846}) 2847 2848(define_expand "sminsf3" 2849 [(set (match_dup 3) 2850 (lt:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand")) 2851 (float_extend:DF (match_operand:SF 2 "reg_or_0_operand")))) 2852 (set (match_operand:SF 0 "register_operand") 2853 (if_then_else:SF (ne (match_dup 3) (match_dup 4)) 2854 (match_dup 1) (match_dup 2)))] 2855 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2856{ 2857 operands[3] = gen_reg_rtx (DFmode); 2858 operands[4] = CONST0_RTX (DFmode); 2859}) 2860 2861(define_insn "*fbcc_normal" 2862 [(set (pc) 2863 (if_then_else 2864 (match_operator 1 "signed_comparison_operator" 2865 [(match_operand:DF 2 "reg_or_0_operand" "fG") 2866 (match_operand:DF 3 "const0_operand" "G")]) 2867 (label_ref (match_operand 0)) 2868 (pc)))] 2869 "TARGET_FP" 2870 "fb%C1 %R2,%0" 2871 [(set_attr "type" "fbr")]) 2872 2873(define_insn "*fbcc_ext_normal" 2874 [(set (pc) 2875 (if_then_else 2876 (match_operator 1 "signed_comparison_operator" 2877 [(float_extend:DF 2878 (match_operand:SF 2 "reg_or_0_operand" "fG")) 2879 (match_operand:DF 3 "const0_operand" "G")]) 2880 (label_ref (match_operand 0)) 2881 (pc)))] 2882 "TARGET_FP" 2883 "fb%C1 %R2,%0" 2884 [(set_attr "type" "fbr")]) 2885 2886;; These are the main define_expand's used to make conditional branches 2887;; and compares. 2888 2889(define_expand "cbranchdf4" 2890 [(use (match_operator 0 "alpha_cbranch_operator" 2891 [(match_operand:DF 1 "reg_or_0_operand") 2892 (match_operand:DF 2 "reg_or_0_operand")])) 2893 (use (match_operand 3))] 2894 "TARGET_FP" 2895 "alpha_emit_conditional_branch (operands, DFmode); DONE;") 2896 2897(define_expand "cbranchtf4" 2898 [(use (match_operator 0 "alpha_cbranch_operator" 2899 [(match_operand:TF 1 "general_operand") 2900 (match_operand:TF 2 "general_operand")])) 2901 (use (match_operand 3))] 2902 "TARGET_HAS_XFLOATING_LIBS" 2903 "alpha_emit_conditional_branch (operands, TFmode); DONE;") 2904 2905(define_expand "cbranchdi4" 2906 [(use (match_operator 0 "alpha_cbranch_operator" 2907 [(match_operand:DI 1 "general_operand") 2908 (match_operand:DI 2 "general_operand")])) 2909 (use (match_operand 3))] 2910 "" 2911 "alpha_emit_conditional_branch (operands, DImode); DONE;") 2912 2913(define_expand "cstoredf4" 2914 [(use (match_operator:DI 1 "alpha_cbranch_operator" 2915 [(match_operand:DF 2 "reg_or_0_operand") 2916 (match_operand:DF 3 "reg_or_0_operand")])) 2917 (clobber (match_operand:DI 0 "register_operand"))] 2918 "TARGET_FP" 2919{ 2920 if (alpha_emit_setcc (operands, DFmode)) 2921 DONE; 2922 else 2923 FAIL; 2924}) 2925 2926(define_expand "cstoretf4" 2927 [(use (match_operator:DI 1 "alpha_cbranch_operator" 2928 [(match_operand:TF 2 "general_operand") 2929 (match_operand:TF 3 "general_operand")])) 2930 (clobber (match_operand:DI 0 "register_operand"))] 2931 "TARGET_HAS_XFLOATING_LIBS" 2932{ 2933 if (alpha_emit_setcc (operands, TFmode)) 2934 DONE; 2935 else 2936 FAIL; 2937}) 2938 2939(define_expand "cstoredi4" 2940 [(use (match_operator:DI 1 "alpha_cbranch_operator" 2941 [(match_operand:DI 2 "general_operand") 2942 (match_operand:DI 3 "general_operand")])) 2943 (clobber (match_operand:DI 0 "register_operand"))] 2944 "" 2945{ 2946 if (alpha_emit_setcc (operands, DImode)) 2947 DONE; 2948 else 2949 FAIL; 2950}) 2951 2952;; These are the main define_expand's used to make conditional moves. 2953 2954(define_expand "mov<mode>cc" 2955 [(set (match_operand:I48MODE 0 "register_operand") 2956 (if_then_else:I48MODE 2957 (match_operand 1 "comparison_operator") 2958 (match_operand:I48MODE 2 "reg_or_8bit_operand") 2959 (match_operand:I48MODE 3 "reg_or_8bit_operand")))] 2960 "" 2961{ 2962 operands[1] = alpha_emit_conditional_move (operands[1], <MODE>mode); 2963 if (operands[1] == 0) 2964 FAIL; 2965}) 2966 2967(define_expand "mov<mode>cc" 2968 [(set (match_operand:FMODE 0 "register_operand") 2969 (if_then_else:FMODE 2970 (match_operand 1 "comparison_operator") 2971 (match_operand:FMODE 2 "reg_or_8bit_operand") 2972 (match_operand:FMODE 3 "reg_or_8bit_operand")))] 2973 "" 2974{ 2975 operands[1] = alpha_emit_conditional_move (operands[1], <MODE>mode); 2976 if (operands[1] == 0) 2977 FAIL; 2978}) 2979 2980;; These define_split definitions are used in cases when comparisons have 2981;; not be stated in the correct way and we need to reverse the second 2982;; comparison. For example, x >= 7 has to be done as x < 6 with the 2983;; comparison that tests the result being reversed. We have one define_split 2984;; for each use of a comparison. They do not match valid insns and need 2985;; not generate valid insns. 2986;; 2987;; We can also handle equality comparisons (and inequality comparisons in 2988;; cases where the resulting add cannot overflow) by doing an add followed by 2989;; a comparison with zero. This is faster since the addition takes one 2990;; less cycle than a compare when feeding into a conditional move. 2991;; For this case, we also have an SImode pattern since we can merge the add 2992;; and sign extend and the order doesn't matter. 2993;; 2994;; We do not do this for floating-point, since it isn't clear how the "wrong" 2995;; operation could have been generated. 2996 2997(define_split 2998 [(set (match_operand:DI 0 "register_operand") 2999 (if_then_else:DI 3000 (match_operator 1 "comparison_operator" 3001 [(match_operand:DI 2 "reg_or_0_operand") 3002 (match_operand:DI 3 "reg_or_cint_operand")]) 3003 (match_operand:DI 4 "reg_or_cint_operand") 3004 (match_operand:DI 5 "reg_or_cint_operand"))) 3005 (clobber (match_operand:DI 6 "register_operand"))] 3006 "operands[3] != const0_rtx" 3007 [(set (match_dup 6) (match_dup 7)) 3008 (set (match_dup 0) 3009 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))] 3010{ 3011 enum rtx_code code = GET_CODE (operands[1]); 3012 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU); 3013 3014 /* If we are comparing for equality with a constant and that constant 3015 appears in the arm when the register equals the constant, use the 3016 register since that is more likely to match (and to produce better code 3017 if both would). */ 3018 3019 if (code == EQ && CONST_INT_P (operands[3]) 3020 && rtx_equal_p (operands[4], operands[3])) 3021 operands[4] = operands[2]; 3022 3023 else if (code == NE && CONST_INT_P (operands[3]) 3024 && rtx_equal_p (operands[5], operands[3])) 3025 operands[5] = operands[2]; 3026 3027 if (code == NE || code == EQ 3028 || (extended_count (operands[2], DImode, unsignedp) >= 1 3029 && extended_count (operands[3], DImode, unsignedp) >= 1)) 3030 { 3031 if (CONST_INT_P (operands[3])) 3032 operands[7] = gen_rtx_PLUS (DImode, operands[2], 3033 GEN_INT (- INTVAL (operands[3]))); 3034 else 3035 operands[7] = gen_rtx_MINUS (DImode, operands[2], operands[3]); 3036 3037 operands[8] = gen_rtx_fmt_ee (code, VOIDmode, operands[6], const0_rtx); 3038 } 3039 3040 else if (code == EQ || code == LE || code == LT 3041 || code == LEU || code == LTU) 3042 { 3043 operands[7] = gen_rtx_fmt_ee (code, DImode, operands[2], operands[3]); 3044 operands[8] = gen_rtx_NE (VOIDmode, operands[6], const0_rtx); 3045 } 3046 else 3047 { 3048 operands[7] = gen_rtx_fmt_ee (reverse_condition (code), DImode, 3049 operands[2], operands[3]); 3050 operands[8] = gen_rtx_EQ (VOIDmode, operands[6], const0_rtx); 3051 } 3052}) 3053 3054(define_split 3055 [(set (match_operand:DI 0 "register_operand") 3056 (if_then_else:DI 3057 (match_operator 1 "comparison_operator" 3058 [(match_operand:SI 2 "reg_or_0_operand") 3059 (match_operand:SI 3 "reg_or_cint_operand")]) 3060 (match_operand:DI 4 "reg_or_8bit_operand") 3061 (match_operand:DI 5 "reg_or_8bit_operand"))) 3062 (clobber (match_operand:DI 6 "register_operand"))] 3063 "operands[3] != const0_rtx 3064 && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)" 3065 [(set (match_dup 6) (match_dup 7)) 3066 (set (match_dup 0) 3067 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))] 3068{ 3069 enum rtx_code code = GET_CODE (operands[1]); 3070 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU); 3071 rtx tem; 3072 3073 if ((code != NE && code != EQ 3074 && ! (extended_count (operands[2], DImode, unsignedp) >= 1 3075 && extended_count (operands[3], DImode, unsignedp) >= 1))) 3076 FAIL; 3077 3078 if (CONST_INT_P (operands[3])) 3079 tem = gen_rtx_PLUS (SImode, operands[2], 3080 GEN_INT (- INTVAL (operands[3]))); 3081 else 3082 tem = gen_rtx_MINUS (SImode, operands[2], operands[3]); 3083 3084 operands[7] = gen_rtx_SIGN_EXTEND (DImode, tem); 3085 operands[8] = gen_rtx_fmt_ee (GET_CODE (operands[1]), VOIDmode, 3086 operands[6], const0_rtx); 3087}) 3088 3089;; Prefer to use cmp and arithmetic when possible instead of a cmove. 3090 3091(define_split 3092 [(set (match_operand 0 "register_operand") 3093 (if_then_else (match_operator 1 "signed_comparison_operator" 3094 [(match_operand:DI 2 "reg_or_0_operand") 3095 (const_int 0)]) 3096 (match_operand 3 "const_int_operand") 3097 (match_operand 4 "const_int_operand")))] 3098 "" 3099 [(const_int 0)] 3100{ 3101 if (alpha_split_conditional_move (GET_CODE (operands[1]), operands[0], 3102 operands[2], operands[3], operands[4])) 3103 DONE; 3104 else 3105 FAIL; 3106}) 3107 3108;; ??? Why combine is allowed to create such non-canonical rtl, I don't know. 3109;; Oh well, we match it in movcc, so it must be partially our fault. 3110(define_split 3111 [(set (match_operand 0 "register_operand") 3112 (if_then_else (match_operator 1 "signed_comparison_operator" 3113 [(const_int 0) 3114 (match_operand:DI 2 "reg_or_0_operand")]) 3115 (match_operand 3 "const_int_operand") 3116 (match_operand 4 "const_int_operand")))] 3117 "" 3118 [(const_int 0)] 3119{ 3120 if (alpha_split_conditional_move (swap_condition (GET_CODE (operands[1])), 3121 operands[0], operands[2], operands[3], 3122 operands[4])) 3123 DONE; 3124 else 3125 FAIL; 3126}) 3127 3128(define_insn_and_split "*cmp_sadd_di" 3129 [(set (match_operand:DI 0 "register_operand" "=r") 3130 (plus:DI (if_then_else:DI 3131 (match_operator 1 "alpha_zero_comparison_operator" 3132 [(match_operand:DI 2 "reg_or_0_operand" "rJ") 3133 (const_int 0)]) 3134 (match_operand:DI 3 "const48_operand" "I") 3135 (const_int 0)) 3136 (match_operand:DI 4 "sext_add_operand" "rIO"))) 3137 (clobber (match_scratch:DI 5 "=r"))] 3138 "" 3139 "#" 3140 "" 3141 [(set (match_dup 5) 3142 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)])) 3143 (set (match_dup 0) 3144 (plus:DI (ashift:DI (match_dup 5) (match_dup 3)) 3145 (match_dup 4)))] 3146{ 3147 operands[3] = GEN_INT (exact_log2 (INTVAL (operands [3]))); 3148 if (can_create_pseudo_p ()) 3149 operands[5] = gen_reg_rtx (DImode); 3150 else if (reg_overlap_mentioned_p (operands[5], operands[4])) 3151 operands[5] = operands[0]; 3152}) 3153 3154(define_insn_and_split "*cmp_sadd_si" 3155 [(set (match_operand:SI 0 "register_operand" "=r") 3156 (plus:SI (if_then_else:SI 3157 (match_operator 1 "alpha_zero_comparison_operator" 3158 [(match_operand:DI 2 "reg_or_0_operand" "rJ") 3159 (const_int 0)]) 3160 (match_operand:SI 3 "const48_operand" "I") 3161 (const_int 0)) 3162 (match_operand:SI 4 "sext_add_operand" "rIO"))) 3163 (clobber (match_scratch:DI 5 "=r"))] 3164 "" 3165 "#" 3166 "" 3167 [(set (match_dup 5) 3168 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)])) 3169 (set (match_dup 0) 3170 (plus:SI (ashift:SI (match_dup 6) (match_dup 3)) 3171 (match_dup 4)))] 3172{ 3173 operands[3] = GEN_INT (exact_log2 (INTVAL (operands [3]))); 3174 if (can_create_pseudo_p ()) 3175 operands[5] = gen_reg_rtx (DImode); 3176 else if (reg_overlap_mentioned_p (operands[5], operands[4])) 3177 operands[5] = gen_lowpart (DImode, operands[0]); 3178 3179 operands[6] = gen_lowpart (SImode, operands[5]); 3180}) 3181 3182(define_insn_and_split "*cmp_sadd_sidi" 3183 [(set (match_operand:DI 0 "register_operand" "=r") 3184 (sign_extend:DI 3185 (plus:SI (if_then_else:SI 3186 (match_operator 1 "alpha_zero_comparison_operator" 3187 [(match_operand:DI 2 "reg_or_0_operand" "rJ") 3188 (const_int 0)]) 3189 (match_operand:SI 3 "const48_operand" "I") 3190 (const_int 0)) 3191 (match_operand:SI 4 "sext_add_operand" "rIO")))) 3192 (clobber (match_scratch:DI 5 "=r"))] 3193 "" 3194 "#" 3195 "" 3196 [(set (match_dup 5) 3197 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)])) 3198 (set (match_dup 0) 3199 (sign_extend:DI (plus:SI (ashift:SI (match_dup 6) (match_dup 3)) 3200 (match_dup 4))))] 3201{ 3202 operands[3] = GEN_INT (exact_log2 (INTVAL (operands [3]))); 3203 if (can_create_pseudo_p ()) 3204 operands[5] = gen_reg_rtx (DImode); 3205 else if (reg_overlap_mentioned_p (operands[5], operands[4])) 3206 operands[5] = operands[0]; 3207 3208 operands[6] = gen_lowpart (SImode, operands[5]); 3209}) 3210 3211(define_insn_and_split "*cmp_ssub_di" 3212 [(set (match_operand:DI 0 "register_operand" "=r") 3213 (minus:DI (if_then_else:DI 3214 (match_operator 1 "alpha_zero_comparison_operator" 3215 [(match_operand:DI 2 "reg_or_0_operand" "rJ") 3216 (const_int 0)]) 3217 (match_operand:DI 3 "const48_operand" "I") 3218 (const_int 0)) 3219 (match_operand:DI 4 "reg_or_8bit_operand" "rI"))) 3220 (clobber (match_scratch:DI 5 "=r"))] 3221 "" 3222 "#" 3223 "" 3224 [(set (match_dup 5) 3225 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)])) 3226 (set (match_dup 0) 3227 (minus:DI (ashift:DI (match_dup 5) (match_dup 3)) 3228 (match_dup 4)))] 3229{ 3230 operands[3] = GEN_INT (exact_log2 (INTVAL (operands [3]))); 3231 if (can_create_pseudo_p ()) 3232 operands[5] = gen_reg_rtx (DImode); 3233 else if (reg_overlap_mentioned_p (operands[5], operands[4])) 3234 operands[5] = operands[0]; 3235}) 3236 3237(define_insn_and_split "*cmp_ssub_si" 3238 [(set (match_operand:SI 0 "register_operand" "=r") 3239 (minus:SI (if_then_else:SI 3240 (match_operator 1 "alpha_zero_comparison_operator" 3241 [(match_operand:DI 2 "reg_or_0_operand" "rJ") 3242 (const_int 0)]) 3243 (match_operand:SI 3 "const48_operand" "I") 3244 (const_int 0)) 3245 (match_operand:SI 4 "reg_or_8bit_operand" "rI"))) 3246 (clobber (match_scratch:DI 5 "=r"))] 3247 "" 3248 "#" 3249 "" 3250 [(set (match_dup 5) 3251 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)])) 3252 (set (match_dup 0) 3253 (minus:SI (ashift:SI (match_dup 6) (match_dup 3)) 3254 (match_dup 4)))] 3255{ 3256 operands[3] = GEN_INT (exact_log2 (INTVAL (operands [3]))); 3257 if (can_create_pseudo_p ()) 3258 operands[5] = gen_reg_rtx (DImode); 3259 else if (reg_overlap_mentioned_p (operands[5], operands[4])) 3260 operands[5] = gen_lowpart (DImode, operands[0]); 3261 3262 operands[6] = gen_lowpart (SImode, operands[5]); 3263}) 3264 3265(define_insn_and_split "*cmp_ssub_sidi" 3266 [(set (match_operand:DI 0 "register_operand" "=r") 3267 (sign_extend:DI 3268 (minus:SI (if_then_else:SI 3269 (match_operator 1 "alpha_zero_comparison_operator" 3270 [(match_operand:DI 2 "reg_or_0_operand" "rJ") 3271 (const_int 0)]) 3272 (match_operand:SI 3 "const48_operand" "I") 3273 (const_int 0)) 3274 (match_operand:SI 4 "reg_or_8bit_operand" "rI")))) 3275 (clobber (match_scratch:DI 5 "=r"))] 3276 "" 3277 "#" 3278 "" 3279 [(set (match_dup 5) 3280 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)])) 3281 (set (match_dup 0) 3282 (sign_extend:DI (minus:SI (ashift:SI (match_dup 6) (match_dup 3)) 3283 (match_dup 4))))] 3284{ 3285 operands[3] = GEN_INT (exact_log2 (INTVAL (operands [3]))); 3286 if (can_create_pseudo_p ()) 3287 operands[5] = gen_reg_rtx (DImode); 3288 else if (reg_overlap_mentioned_p (operands[5], operands[4])) 3289 operands[5] = operands[0]; 3290 3291 operands[6] = gen_lowpart (SImode, operands[5]); 3292}) 3293 3294;; Here are the CALL and unconditional branch insns. Calls on NT and OSF 3295;; work differently, so we have different patterns for each. 3296 3297(define_expand "call" 3298 [(use (match_operand:DI 0)) 3299 (use (match_operand 1)) 3300 (use (match_operand 2)) 3301 (use (match_operand 3))] 3302 "" 3303{ 3304 if (TARGET_ABI_OPEN_VMS) 3305 emit_call_insn (gen_call_vms (operands[0], operands[2])); 3306 else 3307 emit_call_insn (gen_call_osf (operands[0], operands[1])); 3308 DONE; 3309}) 3310 3311(define_expand "sibcall" 3312 [(parallel [(call (mem:DI (match_operand 0)) 3313 (match_operand 1)) 3314 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)])] 3315 "TARGET_ABI_OSF" 3316{ 3317 gcc_assert (MEM_P (operands[0])); 3318 operands[0] = XEXP (operands[0], 0); 3319}) 3320 3321(define_expand "call_osf" 3322 [(parallel [(call (mem:DI (match_operand 0)) 3323 (match_operand 1)) 3324 (use (reg:DI 29)) 3325 (clobber (reg:DI 26))])] 3326 "" 3327{ 3328 gcc_assert (MEM_P (operands[0])); 3329 3330 operands[0] = XEXP (operands[0], 0); 3331 if (! call_operand (operands[0], Pmode)) 3332 operands[0] = copy_to_mode_reg (Pmode, operands[0]); 3333}) 3334 3335;; 3336;; call openvms/alpha 3337;; op 0: symbol ref for called function 3338;; op 1: next_arg_reg (argument information value for R25) 3339;; 3340(define_expand "call_vms" 3341 [(parallel [(call (mem:DI (match_operand 0)) 3342 (match_operand 1)) 3343 (use (match_dup 2)) 3344 (use (reg:DI 25)) 3345 (use (reg:DI 26)) 3346 (clobber (reg:DI 27))])] 3347 "" 3348{ 3349 gcc_assert (MEM_P (operands[0])); 3350 3351 operands[0] = XEXP (operands[0], 0); 3352 3353 /* Always load AI with argument information, then handle symbolic and 3354 indirect call differently. Load RA and set operands[2] to PV in 3355 both cases. */ 3356 3357 emit_move_insn (gen_rtx_REG (DImode, 25), operands[1]); 3358 if (GET_CODE (operands[0]) == SYMBOL_REF) 3359 { 3360 operands[2] = const0_rtx; 3361 } 3362 else 3363 { 3364 emit_move_insn (gen_rtx_REG (Pmode, 26), 3365 gen_rtx_MEM (Pmode, plus_constant (Pmode, 3366 operands[0], 8))); 3367 operands[2] = operands[0]; 3368 } 3369}) 3370 3371(define_expand "call_value" 3372 [(use (match_operand 0)) 3373 (use (match_operand:DI 1)) 3374 (use (match_operand 2)) 3375 (use (match_operand 3)) 3376 (use (match_operand 4))] 3377 "" 3378{ 3379 if (TARGET_ABI_OPEN_VMS) 3380 emit_call_insn (gen_call_value_vms (operands[0], operands[1], 3381 operands[3])); 3382 else 3383 emit_call_insn (gen_call_value_osf (operands[0], operands[1], 3384 operands[2])); 3385 DONE; 3386}) 3387 3388(define_expand "sibcall_value" 3389 [(parallel [(set (match_operand 0) 3390 (call (mem:DI (match_operand 1)) 3391 (match_operand 2))) 3392 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)])] 3393 "TARGET_ABI_OSF" 3394{ 3395 gcc_assert (MEM_P (operands[1])); 3396 operands[1] = XEXP (operands[1], 0); 3397}) 3398 3399(define_expand "call_value_osf" 3400 [(parallel [(set (match_operand 0) 3401 (call (mem:DI (match_operand 1)) 3402 (match_operand 2))) 3403 (use (reg:DI 29)) 3404 (clobber (reg:DI 26))])] 3405 "" 3406{ 3407 gcc_assert (MEM_P (operands[1])); 3408 3409 operands[1] = XEXP (operands[1], 0); 3410 if (! call_operand (operands[1], Pmode)) 3411 operands[1] = copy_to_mode_reg (Pmode, operands[1]); 3412}) 3413 3414(define_expand "call_value_vms" 3415 [(parallel [(set (match_operand 0) 3416 (call (mem:DI (match_operand:DI 1)) 3417 (match_operand 2))) 3418 (use (match_dup 3)) 3419 (use (reg:DI 25)) 3420 (use (reg:DI 26)) 3421 (clobber (reg:DI 27))])] 3422 "" 3423{ 3424 gcc_assert (MEM_P (operands[1])); 3425 3426 operands[1] = XEXP (operands[1], 0); 3427 3428 /* Always load AI with argument information, then handle symbolic and 3429 indirect call differently. Load RA and set operands[3] to PV in 3430 both cases. */ 3431 3432 emit_move_insn (gen_rtx_REG (DImode, 25), operands[2]); 3433 if (GET_CODE (operands[1]) == SYMBOL_REF) 3434 { 3435 operands[3] = const0_rtx; 3436 } 3437 else 3438 { 3439 emit_move_insn (gen_rtx_REG (Pmode, 26), 3440 gen_rtx_MEM (Pmode, plus_constant (Pmode, 3441 operands[1], 8))); 3442 operands[3] = operands[1]; 3443 } 3444}) 3445 3446(define_insn "*call_osf_1_er_noreturn" 3447 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s")) 3448 (match_operand 1)) 3449 (use (reg:DI 29)) 3450 (clobber (reg:DI 26))] 3451 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF 3452 && find_reg_note (insn, REG_NORETURN, NULL_RTX)" 3453 "@ 3454 jsr $26,($27),0 3455 bsr $26,%0\t\t!samegp 3456 ldq $27,%0($29)\t\t!literal!%#\;jsr $26,($27),%0\t\t!lituse_jsr!%#" 3457 [(set_attr "type" "jsr") 3458 (set_attr "length" "*,*,8")]) 3459 3460(define_insn "*call_osf_1_er" 3461 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s")) 3462 (match_operand 1)) 3463 (use (reg:DI 29)) 3464 (clobber (reg:DI 26))] 3465 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 3466 "@ 3467 jsr $26,(%0),0\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%* 3468 bsr $26,%0\t\t!samegp 3469 ldq $27,%0($29)\t\t!literal!%#\;jsr $26,($27),%0\t\t!lituse_jsr!%#\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*" 3470 [(set_attr "type" "jsr") 3471 (set_attr "length" "12,*,16")]) 3472 3473;; We must use peep2 instead of a split because we need accurate life 3474;; information for $gp. Consider the case of { bar(); while (1); }. 3475(define_peephole2 3476 [(parallel [(call (mem:DI (match_operand:DI 0 "call_operand")) 3477 (match_operand 1)) 3478 (use (reg:DI 29)) 3479 (clobber (reg:DI 26))])] 3480 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed 3481 && ! samegp_function_operand (operands[0], Pmode) 3482 && (peep2_regno_dead_p (1, 29) 3483 || find_reg_note (insn, REG_NORETURN, NULL_RTX))" 3484 [(parallel [(call (mem:DI (match_dup 2)) 3485 (match_dup 1)) 3486 (use (reg:DI 29)) 3487 (use (match_dup 0)) 3488 (use (match_dup 3)) 3489 (clobber (reg:DI 26))])] 3490{ 3491 if (CONSTANT_P (operands[0])) 3492 { 3493 operands[2] = gen_rtx_REG (Pmode, 27); 3494 operands[3] = GEN_INT (alpha_next_sequence_number++); 3495 emit_insn (gen_movdi_er_high_g (operands[2], pic_offset_table_rtx, 3496 operands[0], operands[3])); 3497 } 3498 else 3499 { 3500 operands[2] = operands[0]; 3501 operands[0] = const0_rtx; 3502 operands[3] = const0_rtx; 3503 } 3504}) 3505 3506(define_peephole2 3507 [(parallel [(call (mem:DI (match_operand:DI 0 "call_operand")) 3508 (match_operand 1)) 3509 (use (reg:DI 29)) 3510 (clobber (reg:DI 26))])] 3511 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed 3512 && ! samegp_function_operand (operands[0], Pmode) 3513 && ! (peep2_regno_dead_p (1, 29) 3514 || find_reg_note (insn, REG_NORETURN, NULL_RTX))" 3515 [(parallel [(call (mem:DI (match_dup 2)) 3516 (match_dup 1)) 3517 (set (match_dup 5) 3518 (unspec:DI [(match_dup 5) (match_dup 3)] UNSPEC_LDGP1)) 3519 (use (match_dup 0)) 3520 (use (match_dup 4)) 3521 (clobber (reg:DI 26))]) 3522 (set (match_dup 5) 3523 (unspec:DI [(match_dup 5) (match_dup 3)] UNSPEC_LDGP2))] 3524{ 3525 if (CONSTANT_P (operands[0])) 3526 { 3527 operands[2] = gen_rtx_REG (Pmode, 27); 3528 operands[4] = GEN_INT (alpha_next_sequence_number++); 3529 emit_insn (gen_movdi_er_high_g (operands[2], pic_offset_table_rtx, 3530 operands[0], operands[4])); 3531 } 3532 else 3533 { 3534 operands[2] = operands[0]; 3535 operands[0] = const0_rtx; 3536 operands[4] = const0_rtx; 3537 } 3538 operands[3] = GEN_INT (alpha_next_sequence_number++); 3539 operands[5] = pic_offset_table_rtx; 3540}) 3541 3542(define_insn "*call_osf_2_er_nogp" 3543 [(call (mem:DI (match_operand:DI 0 "register_operand" "c")) 3544 (match_operand 1)) 3545 (use (reg:DI 29)) 3546 (use (match_operand 2)) 3547 (use (match_operand 3 "const_int_operand")) 3548 (clobber (reg:DI 26))] 3549 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 3550 "jsr $26,(%0),%2%J3" 3551 [(set_attr "type" "jsr")]) 3552 3553(define_insn "*call_osf_2_er" 3554 [(call (mem:DI (match_operand:DI 0 "register_operand" "c")) 3555 (match_operand 1)) 3556 (set (reg:DI 29) 3557 (unspec:DI [(reg:DI 29) (match_operand 4 "const_int_operand")] 3558 UNSPEC_LDGP1)) 3559 (use (match_operand 2)) 3560 (use (match_operand 3 "const_int_operand")) 3561 (clobber (reg:DI 26))] 3562 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 3563 "jsr $26,(%0),%2%J3\;ldah $29,0($26)\t\t!gpdisp!%4" 3564 [(set_attr "type" "jsr") 3565 (set_attr "cannot_copy" "true") 3566 (set_attr "length" "8")]) 3567 3568(define_insn "*call_osf_1_noreturn" 3569 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s")) 3570 (match_operand 1)) 3571 (use (reg:DI 29)) 3572 (clobber (reg:DI 26))] 3573 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF 3574 && find_reg_note (insn, REG_NORETURN, NULL_RTX)" 3575 "@ 3576 jsr $26,($27),0 3577 bsr $26,$%0..ng 3578 jsr $26,%0" 3579 [(set_attr "type" "jsr") 3580 (set_attr "length" "*,*,8")]) 3581 3582(define_insn "*call_osf_1" 3583 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s")) 3584 (match_operand 1)) 3585 (use (reg:DI 29)) 3586 (clobber (reg:DI 26))] 3587 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 3588 "@ 3589 jsr $26,($27),0\;ldgp $29,0($26) 3590 bsr $26,$%0..ng 3591 jsr $26,%0\;ldgp $29,0($26)" 3592 [(set_attr "type" "jsr") 3593 (set_attr "length" "12,*,16")]) 3594 3595(define_insn "*sibcall_osf_1_er" 3596 [(call (mem:DI (match_operand:DI 0 "symbolic_operand" "R,s")) 3597 (match_operand 1)) 3598 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)] 3599 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 3600 "@ 3601 br $31,%0\t\t!samegp 3602 ldq $27,%0($29)\t\t!literal!%#\;jmp $31,($27),%0\t\t!lituse_jsr!%#" 3603 [(set_attr "type" "jsr") 3604 (set_attr "length" "*,8")]) 3605 3606;; Note that the DEC assembler expands "jmp foo" with $at, which 3607;; doesn't do what we want. 3608(define_insn "*sibcall_osf_1" 3609 [(call (mem:DI (match_operand:DI 0 "symbolic_operand" "R,s")) 3610 (match_operand 1)) 3611 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)] 3612 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 3613 "@ 3614 br $31,$%0..ng 3615 lda $27,%0\;jmp $31,($27),%0" 3616 [(set_attr "type" "jsr") 3617 (set_attr "length" "*,8")]) 3618 3619; GAS relies on the order and position of instructions output below in order 3620; to generate relocs for VMS link to potentially optimize the call. 3621; Please do not molest. 3622(define_insn "*call_vms_1" 3623 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,s")) 3624 (match_operand 1)) 3625 (use (match_operand:DI 2 "nonmemory_operand" "r,n")) 3626 (use (reg:DI 25)) 3627 (use (reg:DI 26)) 3628 (clobber (reg:DI 27))] 3629 "TARGET_ABI_OPEN_VMS" 3630{ 3631 switch (which_alternative) 3632 { 3633 case 0: 3634 return "mov %2,$27\;jsr $26,0\;ldq $27,0($29)"; 3635 case 1: 3636 operands [2] = alpha_use_linkage (operands [0], true, false); 3637 operands [3] = alpha_use_linkage (operands [0], false, false); 3638 return "ldq $26,%3\;ldq $27,%2\;jsr $26,%0\;ldq $27,0($29)"; 3639 default: 3640 gcc_unreachable (); 3641 } 3642} 3643 [(set_attr "type" "jsr") 3644 (set_attr "length" "12,16")]) 3645 3646;; Call subroutine returning any type. 3647 3648(define_expand "untyped_call" 3649 [(parallel [(call (match_operand 0) 3650 (const_int 0)) 3651 (match_operand 1) 3652 (match_operand 2)])] 3653 "" 3654{ 3655 int i; 3656 3657 emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx)); 3658 3659 for (i = 0; i < XVECLEN (operands[2], 0); i++) 3660 { 3661 rtx set = XVECEXP (operands[2], 0, i); 3662 emit_move_insn (SET_DEST (set), SET_SRC (set)); 3663 } 3664 3665 /* The optimizer does not know that the call sets the function value 3666 registers we stored in the result block. We avoid problems by 3667 claiming that all hard registers are used and clobbered at this 3668 point. */ 3669 emit_insn (gen_blockage ()); 3670 3671 DONE; 3672}) 3673 3674;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and 3675;; all of memory. This blocks insns from being moved across this point. 3676 3677(define_insn "blockage" 3678 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)] 3679 "" 3680 "" 3681 [(set_attr "length" "0") 3682 (set_attr "type" "none")]) 3683 3684(define_insn "jump" 3685 [(set (pc) 3686 (label_ref (match_operand 0)))] 3687 "" 3688 "br $31,%l0" 3689 [(set_attr "type" "ibr")]) 3690 3691(define_expand "return" 3692 [(return)] 3693 "direct_return ()") 3694 3695(define_insn "*return_internal" 3696 [(return)] 3697 "reload_completed" 3698 "ret $31,($26),1" 3699 [(set_attr "type" "ibr")]) 3700 3701(define_insn "indirect_jump" 3702 [(set (pc) (match_operand:DI 0 "register_operand" "r"))] 3703 "" 3704 "jmp $31,(%0),0" 3705 [(set_attr "type" "ibr")]) 3706 3707(define_expand "tablejump" 3708 [(parallel [(set (pc) 3709 (match_operand 0 "register_operand")) 3710 (use (label_ref:DI (match_operand 1)))])] 3711 "" 3712{ 3713 if (TARGET_ABI_OSF) 3714 { 3715 rtx dest = gen_reg_rtx (DImode); 3716 emit_insn (gen_extendsidi2 (dest, operands[0])); 3717 emit_insn (gen_adddi3 (dest, pic_offset_table_rtx, dest)); 3718 operands[0] = dest; 3719 } 3720}) 3721 3722(define_insn "*tablejump_internal" 3723 [(set (pc) 3724 (match_operand:DI 0 "register_operand" "r")) 3725 (use (label_ref (match_operand 1)))] 3726 "" 3727 "jmp $31,(%0),0" 3728 [(set_attr "type" "ibr")]) 3729 3730;; Cache flush. Used by alpha_trampoline_init. 0x86 is PAL_imb, but we don't 3731;; want to have to include pal.h in our .s file. 3732(define_insn "imb" 3733 [(unspec_volatile [(const_int 0)] UNSPECV_IMB)] 3734 "" 3735 "call_pal 0x86" 3736 [(set_attr "type" "callpal")]) 3737 3738(define_expand "clear_cache" 3739 [(match_operand:DI 0) ; region start 3740 (match_operand:DI 1)] ; region end 3741 "" 3742{ 3743 emit_insn (gen_imb ()); 3744 DONE; 3745}) 3746 3747;; BUGCHK is documented common to OSF/1 and VMS PALcode. 3748(define_insn "trap" 3749 [(trap_if (const_int 1) (const_int 0)) 3750 (use (reg:DI 29))] 3751 "" 3752 "call_pal 0x81" 3753 [(set_attr "type" "callpal")]) 3754 3755;; For userland, we load the thread pointer from the TCB. 3756;; For the kernel, we load the per-cpu private value. 3757 3758(define_insn "get_thread_pointerdi" 3759 [(set (match_operand:DI 0 "register_operand" "=v") 3760 (unspec:DI [(const_int 0)] UNSPEC_TP))] 3761 "TARGET_ABI_OSF" 3762{ 3763 if (TARGET_TLS_KERNEL) 3764 return "call_pal 0x32"; 3765 else 3766 return "call_pal 0x9e"; 3767} 3768 [(set_attr "type" "callpal")]) 3769 3770;; For completeness, and possibly a __builtin function, here's how to 3771;; set the thread pointer. Since we don't describe enough of this 3772;; quantity for CSE, we have to use a volatile unspec, and then there's 3773;; not much point in creating an R16_REG register class. 3774 3775(define_expand "set_thread_pointerdi" 3776 [(set (reg:DI 16) (match_operand:DI 0 "input_operand")) 3777 (unspec_volatile [(reg:DI 16)] UNSPECV_SET_TP)] 3778 "TARGET_ABI_OSF") 3779 3780(define_insn "*set_tp" 3781 [(unspec_volatile [(reg:DI 16)] UNSPECV_SET_TP)] 3782 "TARGET_ABI_OSF" 3783{ 3784 if (TARGET_TLS_KERNEL) 3785 return "call_pal 0x31"; 3786 else 3787 return "call_pal 0x9f"; 3788} 3789 [(set_attr "type" "callpal")]) 3790 3791;; Special builtins for establishing and reverting VMS condition handlers. 3792 3793(define_expand "builtin_establish_vms_condition_handler" 3794 [(set (reg:DI 0) (match_operand:DI 0 "register_operand")) 3795 (use (match_operand:DI 1 "address_operand"))] 3796 "TARGET_ABI_OPEN_VMS" 3797{ 3798 alpha_expand_builtin_establish_vms_condition_handler (operands[0], 3799 operands[1]); 3800}) 3801 3802(define_expand "builtin_revert_vms_condition_handler" 3803 [(set (reg:DI 0) (match_operand:DI 0 "register_operand"))] 3804 "TARGET_ABI_OPEN_VMS" 3805 "alpha_expand_builtin_revert_vms_condition_handler (operands[0]);") 3806 3807;; Finally, we have the basic data motion insns. The byte and word insns 3808;; are done via define_expand. Start with the floating-point insns, since 3809;; they are simpler. 3810 3811(define_expand "movsf" 3812 [(set (match_operand:SF 0 "nonimmediate_operand") 3813 (match_operand:SF 1 "general_operand"))] 3814 "" 3815{ 3816 if (MEM_P (operands[0]) 3817 && ! reg_or_0_operand (operands[1], SFmode)) 3818 operands[1] = force_reg (SFmode, operands[1]); 3819}) 3820 3821(define_insn "*movsf" 3822 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r") 3823 (match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))] 3824 "register_operand (operands[0], SFmode) 3825 || reg_or_0_operand (operands[1], SFmode)" 3826 "@ 3827 cpys %R1,%R1,%0 3828 ld%, %0,%1 3829 bis $31,%r1,%0 3830 ldl %0,%1 3831 st%, %R1,%0 3832 stl %r1,%0 3833 itofs %1,%0 3834 ftois %1,%0" 3835 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi") 3836 (set_attr "isa" "*,*,*,*,*,*,fix,fix")]) 3837 3838(define_expand "movdf" 3839 [(set (match_operand:DF 0 "nonimmediate_operand") 3840 (match_operand:DF 1 "general_operand"))] 3841 "" 3842{ 3843 if (MEM_P (operands[0]) 3844 && ! reg_or_0_operand (operands[1], DFmode)) 3845 operands[1] = force_reg (DFmode, operands[1]); 3846}) 3847 3848(define_insn "*movdf" 3849 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r") 3850 (match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))] 3851 "register_operand (operands[0], DFmode) 3852 || reg_or_0_operand (operands[1], DFmode)" 3853 "@ 3854 cpys %R1,%R1,%0 3855 ld%- %0,%1 3856 bis $31,%r1,%0 3857 ldq %0,%1 3858 st%- %R1,%0 3859 stq %r1,%0 3860 itoft %1,%0 3861 ftoit %1,%0" 3862 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi") 3863 (set_attr "isa" "*,*,*,*,*,*,fix,fix")]) 3864 3865;; Subregs suck for register allocation. Pretend we can move TFmode 3866;; data between general registers until after reload. 3867;; ??? Is this still true now that we have the lower-subreg pass? 3868 3869(define_expand "movtf" 3870 [(set (match_operand:TF 0 "nonimmediate_operand") 3871 (match_operand:TF 1 "general_operand"))] 3872 "" 3873{ 3874 if (MEM_P (operands[0]) 3875 && ! reg_or_0_operand (operands[1], TFmode)) 3876 operands[1] = force_reg (TFmode, operands[1]); 3877}) 3878 3879(define_insn_and_split "*movtf_internal" 3880 [(set (match_operand:TF 0 "nonimmediate_operand" "=r,o") 3881 (match_operand:TF 1 "input_operand" "roG,rG"))] 3882 "register_operand (operands[0], TFmode) 3883 || reg_or_0_operand (operands[1], TFmode)" 3884 "#" 3885 "reload_completed" 3886 [(set (match_dup 0) (match_dup 2)) 3887 (set (match_dup 1) (match_dup 3))] 3888 "alpha_split_tmode_pair (operands, TFmode, true);") 3889 3890;; We do two major things here: handle mem->mem and construct long 3891;; constants. 3892 3893(define_expand "movsi" 3894 [(set (match_operand:SI 0 "nonimmediate_operand") 3895 (match_operand:SI 1 "general_operand"))] 3896 "" 3897{ 3898 if (alpha_expand_mov (SImode, operands)) 3899 DONE; 3900}) 3901 3902(define_insn "*movsi" 3903 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,m,r") 3904 (match_operand:SI 1 "input_operand" "rJ,K,L,n,m,rJ,s"))] 3905 "register_operand (operands[0], SImode) 3906 || reg_or_0_operand (operands[1], SImode)" 3907 "@ 3908 bis $31,%r1,%0 3909 lda %0,%1($31) 3910 ldah %0,%h1($31) 3911 # 3912 ldl %0,%1 3913 stl %r1,%0 3914 lda %0,%1" 3915 [(set_attr "type" "ilog,iadd,iadd,multi,ild,ist,ldsym") 3916 (set_attr "isa" "*,*,*,*,*,*,vms")]) 3917 3918;; Split a load of a large constant into the appropriate two-insn 3919;; sequence. 3920 3921(define_split 3922 [(set (match_operand:SI 0 "register_operand") 3923 (match_operand:SI 1 "non_add_const_operand"))] 3924 "" 3925 [(const_int 0)] 3926{ 3927 if (alpha_split_const_mov (SImode, operands)) 3928 DONE; 3929 else 3930 FAIL; 3931}) 3932 3933(define_insn "*movdi_er_low_l" 3934 [(set (match_operand:DI 0 "register_operand" "=r") 3935 (lo_sum:DI (match_operand:DI 1 "register_operand" "r") 3936 (match_operand:DI 2 "local_symbolic_operand")))] 3937 "TARGET_EXPLICIT_RELOCS" 3938{ 3939 if (true_regnum (operands[1]) == 29) 3940 return "lda %0,%2(%1)\t\t!gprel"; 3941 else 3942 return "lda %0,%2(%1)\t\t!gprellow"; 3943} 3944 [(set_attr "usegp" "yes")]) 3945 3946(define_split 3947 [(set (match_operand:DI 0 "register_operand") 3948 (match_operand:DI 1 "small_symbolic_operand"))] 3949 "TARGET_EXPLICIT_RELOCS && reload_completed" 3950 [(set (match_dup 0) 3951 (lo_sum:DI (match_dup 2) (match_dup 1)))] 3952 "operands[2] = pic_offset_table_rtx;") 3953 3954(define_split 3955 [(set (match_operand:DI 0 "register_operand") 3956 (match_operand:DI 1 "local_symbolic_operand"))] 3957 "TARGET_EXPLICIT_RELOCS && reload_completed" 3958 [(set (match_dup 0) 3959 (plus:DI (match_dup 2) (high:DI (match_dup 1)))) 3960 (set (match_dup 0) 3961 (lo_sum:DI (match_dup 0) (match_dup 1)))] 3962 "operands[2] = pic_offset_table_rtx;") 3963 3964(define_split 3965 [(match_operand 0 "some_small_symbolic_operand")] 3966 "" 3967 [(match_dup 0)] 3968 "operands[0] = split_small_symbolic_operand (operands[0]);") 3969 3970;; Accepts any symbolic, not just global, since function calls that 3971;; don't go via bsr still use !literal in hopes of linker relaxation. 3972(define_insn "movdi_er_high_g" 3973 [(set (match_operand:DI 0 "register_operand" "=r") 3974 (unspec:DI [(match_operand:DI 1 "register_operand" "r") 3975 (match_operand:DI 2 "symbolic_operand") 3976 (match_operand 3 "const_int_operand")] 3977 UNSPEC_LITERAL))] 3978 "TARGET_EXPLICIT_RELOCS" 3979{ 3980 if (INTVAL (operands[3]) == 0) 3981 return "ldq %0,%2(%1)\t\t!literal"; 3982 else 3983 return "ldq %0,%2(%1)\t\t!literal!%3"; 3984} 3985 [(set_attr "type" "ldsym")]) 3986 3987(define_split 3988 [(set (match_operand:DI 0 "register_operand") 3989 (match_operand:DI 1 "global_symbolic_operand"))] 3990 "TARGET_EXPLICIT_RELOCS && reload_completed" 3991 [(set (match_dup 0) 3992 (unspec:DI [(match_dup 2) 3993 (match_dup 1) 3994 (const_int 0)] UNSPEC_LITERAL))] 3995 "operands[2] = pic_offset_table_rtx;") 3996 3997(define_insn "movdi_er_tlsgd" 3998 [(set (match_operand:DI 0 "register_operand" "=r") 3999 (unspec:DI [(match_operand:DI 1 "register_operand" "r") 4000 (match_operand:DI 2 "symbolic_operand") 4001 (match_operand 3 "const_int_operand")] 4002 UNSPEC_TLSGD))] 4003 "HAVE_AS_TLS" 4004{ 4005 if (INTVAL (operands[3]) == 0) 4006 return "lda %0,%2(%1)\t\t!tlsgd"; 4007 else 4008 return "lda %0,%2(%1)\t\t!tlsgd!%3"; 4009}) 4010 4011(define_insn "movdi_er_tlsldm" 4012 [(set (match_operand:DI 0 "register_operand" "=r") 4013 (unspec:DI [(match_operand:DI 1 "register_operand" "r") 4014 (match_operand 2 "const_int_operand")] 4015 UNSPEC_TLSLDM))] 4016 "HAVE_AS_TLS" 4017{ 4018 if (INTVAL (operands[2]) == 0) 4019 return "lda %0,%&(%1)\t\t!tlsldm"; 4020 else 4021 return "lda %0,%&(%1)\t\t!tlsldm!%2"; 4022}) 4023 4024(define_insn "*movdi_er_gotdtp" 4025 [(set (match_operand:DI 0 "register_operand" "=r") 4026 (unspec:DI [(match_operand:DI 1 "register_operand" "r") 4027 (match_operand:DI 2 "symbolic_operand")] 4028 UNSPEC_DTPREL))] 4029 "HAVE_AS_TLS" 4030 "ldq %0,%2(%1)\t\t!gotdtprel" 4031 [(set_attr "type" "ild") 4032 (set_attr "usegp" "yes")]) 4033 4034(define_split 4035 [(set (match_operand:DI 0 "register_operand") 4036 (match_operand:DI 1 "gotdtp_symbolic_operand"))] 4037 "HAVE_AS_TLS && reload_completed" 4038 [(set (match_dup 0) 4039 (unspec:DI [(match_dup 2) 4040 (match_dup 1)] UNSPEC_DTPREL))] 4041{ 4042 operands[1] = XVECEXP (XEXP (operands[1], 0), 0, 0); 4043 operands[2] = pic_offset_table_rtx; 4044}) 4045 4046(define_insn "*movdi_er_gottp" 4047 [(set (match_operand:DI 0 "register_operand" "=r") 4048 (unspec:DI [(match_operand:DI 1 "register_operand" "r") 4049 (match_operand:DI 2 "symbolic_operand")] 4050 UNSPEC_TPREL))] 4051 "HAVE_AS_TLS" 4052 "ldq %0,%2(%1)\t\t!gottprel" 4053 [(set_attr "type" "ild") 4054 (set_attr "usegp" "yes")]) 4055 4056(define_split 4057 [(set (match_operand:DI 0 "register_operand") 4058 (match_operand:DI 1 "gottp_symbolic_operand"))] 4059 "HAVE_AS_TLS && reload_completed" 4060 [(set (match_dup 0) 4061 (unspec:DI [(match_dup 2) 4062 (match_dup 1)] UNSPEC_TPREL))] 4063{ 4064 operands[1] = XVECEXP (XEXP (operands[1], 0), 0, 0); 4065 operands[2] = pic_offset_table_rtx; 4066}) 4067 4068(define_insn "*movdi" 4069 [(set (match_operand:DI 0 "nonimmediate_operand" 4070 "=r,r,r,r,r,r,r,r, m, *f,*f, Q, r,*f") 4071 (match_operand:DI 1 "input_operand" 4072 "rJ,K,L,T,s,n,s,m,rJ,*fJ, Q,*f,*f, r"))] 4073 "register_operand (operands[0], DImode) 4074 || reg_or_0_operand (operands[1], DImode)" 4075 "@ 4076 mov %r1,%0 4077 lda %0,%1($31) 4078 ldah %0,%h1($31) 4079 # 4080 # 4081 # 4082 lda %0,%1 4083 ldq%A1 %0,%1 4084 stq%A0 %r1,%0 4085 fmov %R1,%0 4086 ldt %0,%1 4087 stt %R1,%0 4088 ftoit %1,%0 4089 itoft %1,%0" 4090 [(set_attr "type" "ilog,iadd,iadd,iadd,ldsym,multi,ldsym,ild,ist,fcpys,fld,fst,ftoi,itof") 4091 (set_attr "isa" "*,*,*,er,er,*,ner,*,*,*,*,*,fix,fix") 4092 (set_attr "usegp" "*,*,*,yes,*,*,*,*,*,*,*,*,*,*")]) 4093 4094;; VMS needs to set up "vms_base_regno" for unwinding. This move 4095;; often appears dead to the life analysis code, at which point we 4096;; die for emitting dead prologue instructions. Force this live. 4097 4098(define_insn "force_movdi" 4099 [(set (match_operand:DI 0 "register_operand" "=r") 4100 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")] 4101 UNSPECV_FORCE_MOV))] 4102 "" 4103 "mov %1,%0" 4104 [(set_attr "type" "ilog")]) 4105 4106;; We do three major things here: handle mem->mem, put 64-bit constants in 4107;; memory, and construct long 32-bit constants. 4108 4109(define_expand "movdi" 4110 [(set (match_operand:DI 0 "nonimmediate_operand") 4111 (match_operand:DI 1 "general_operand"))] 4112 "" 4113{ 4114 if (alpha_expand_mov (DImode, operands)) 4115 DONE; 4116}) 4117 4118;; Split a load of a large constant into the appropriate two-insn 4119;; sequence. 4120 4121(define_split 4122 [(set (match_operand:DI 0 "register_operand") 4123 (match_operand:DI 1 "non_add_const_operand"))] 4124 "" 4125 [(const_int 0)] 4126{ 4127 if (alpha_split_const_mov (DImode, operands)) 4128 DONE; 4129 else 4130 FAIL; 4131}) 4132 4133;; We need to prevent reload from splitting TImode moves, because it 4134;; might decide to overwrite a pointer with the value it points to. 4135;; In that case we have to do the loads in the appropriate order so 4136;; that the pointer is not destroyed too early. 4137 4138(define_insn_and_split "*movti_internal" 4139 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o") 4140 (match_operand:TI 1 "input_operand" "roJ,rJ"))] 4141 "(register_operand (operands[0], TImode) 4142 /* Prevent rematerialization of constants. */ 4143 && ! CONSTANT_P (operands[1])) 4144 || reg_or_0_operand (operands[1], TImode)" 4145 "#" 4146 "reload_completed" 4147 [(set (match_dup 0) (match_dup 2)) 4148 (set (match_dup 1) (match_dup 3))] 4149 "alpha_split_tmode_pair (operands, TImode, true);") 4150 4151(define_expand "movti" 4152 [(set (match_operand:TI 0 "nonimmediate_operand") 4153 (match_operand:TI 1 "general_operand"))] 4154 "" 4155{ 4156 if (MEM_P (operands[0]) 4157 && ! reg_or_0_operand (operands[1], TImode)) 4158 operands[1] = force_reg (TImode, operands[1]); 4159 4160 if (operands[1] == const0_rtx) 4161 ; 4162 /* We must put 64-bit constants in memory. We could keep the 4163 32-bit constants in TImode and rely on the splitter, but 4164 this doesn't seem to be worth the pain. */ 4165 else if (CONST_SCALAR_INT_P (operands[1])) 4166 { 4167 rtx in[2], out[2], target; 4168 4169 gcc_assert (can_create_pseudo_p ()); 4170 4171 split_double (operands[1], &in[0], &in[1]); 4172 4173 if (in[0] == const0_rtx) 4174 out[0] = const0_rtx; 4175 else 4176 { 4177 out[0] = gen_reg_rtx (DImode); 4178 emit_insn (gen_movdi (out[0], in[0])); 4179 } 4180 4181 if (in[1] == const0_rtx) 4182 out[1] = const0_rtx; 4183 else 4184 { 4185 out[1] = gen_reg_rtx (DImode); 4186 emit_insn (gen_movdi (out[1], in[1])); 4187 } 4188 4189 if (!REG_P (operands[0])) 4190 target = gen_reg_rtx (TImode); 4191 else 4192 target = operands[0]; 4193 4194 emit_insn (gen_movdi (operand_subword (target, 0, 0, TImode), out[0])); 4195 emit_insn (gen_movdi (operand_subword (target, 1, 0, TImode), out[1])); 4196 4197 if (target != operands[0]) 4198 emit_insn (gen_rtx_SET (operands[0], target)); 4199 4200 DONE; 4201 } 4202}) 4203 4204;; These are the partial-word cases. 4205;; 4206;; First we have the code to load an aligned word. Operand 0 is the register 4207;; in which to place the result. It's mode is QImode or HImode. Operand 1 4208;; is an SImode MEM at the low-order byte of the proper word. Operand 2 is the 4209;; number of bits within the word that the value is. Operand 3 is an SImode 4210;; scratch register. If operand 0 is a hard register, operand 3 may be the 4211;; same register. It is allowed to conflict with operand 1 as well. 4212 4213(define_expand "aligned_loadqi" 4214 [(set (match_operand:SI 3 "register_operand") 4215 (match_operand:SI 1 "memory_operand")) 4216 (set (match_operand:DI 0 "register_operand") 4217 (zero_extract:DI (subreg:DI (match_dup 3) 0) 4218 (const_int 8) 4219 (match_operand:DI 2 "const_int_operand")))]) 4220 4221(define_expand "aligned_loadhi" 4222 [(set (match_operand:SI 3 "register_operand") 4223 (match_operand:SI 1 "memory_operand")) 4224 (set (match_operand:DI 0 "register_operand") 4225 (zero_extract:DI (subreg:DI (match_dup 3) 0) 4226 (const_int 16) 4227 (match_operand:DI 2 "const_int_operand")))]) 4228 4229;; Similar for unaligned loads, where we use the sequence from the 4230;; Alpha Architecture manual. We have to distinguish between little-endian 4231;; and big-endian systems as the sequences are different. 4232;; 4233;; Operand 1 is the address. Operands 2 and 3 are temporaries, where 4234;; operand 3 can overlap the input and output registers. 4235 4236(define_expand "unaligned_loadqi" 4237 [(set (match_operand:DI 2 "register_operand") 4238 (mem:DI (and:DI (match_operand:DI 1 "address_operand") 4239 (const_int -8)))) 4240 (set (match_operand:DI 3 "register_operand") 4241 (match_dup 1)) 4242 (set (match_operand:DI 0 "register_operand") 4243 (zero_extract:DI (match_dup 2) 4244 (const_int 8) 4245 (ashift:DI (match_dup 3) (const_int 3))))]) 4246 4247(define_expand "unaligned_loadhi" 4248 [(set (match_operand:DI 2 "register_operand") 4249 (mem:DI (and:DI (match_operand:DI 1 "address_operand") 4250 (const_int -8)))) 4251 (set (match_operand:DI 3 "register_operand") 4252 (match_dup 1)) 4253 (set (match_operand:DI 0 "register_operand") 4254 (zero_extract:DI (match_dup 2) 4255 (const_int 16) 4256 (ashift:DI (match_dup 3) (const_int 3))))]) 4257 4258;; Storing an aligned byte or word requires two temporaries. Operand 0 is the 4259;; aligned SImode MEM. Operand 1 is the register containing the 4260;; byte or word to store. Operand 2 is the number of bits within the word that 4261;; the value should be placed. Operands 3 and 4 are SImode temporaries. 4262 4263(define_expand "aligned_store" 4264 [(set (match_operand:SI 3 "register_operand") 4265 (match_operand:SI 0 "memory_operand")) 4266 (set (subreg:DI (match_dup 3) 0) 4267 (and:DI (subreg:DI (match_dup 3) 0) (match_dup 5))) 4268 (set (subreg:DI (match_operand:SI 4 "register_operand") 0) 4269 (ashift:DI (zero_extend:DI (match_operand 1 "register_operand")) 4270 (match_operand:DI 2 "const_int_operand"))) 4271 (set (subreg:DI (match_dup 4) 0) 4272 (ior:DI (subreg:DI (match_dup 4) 0) (subreg:DI (match_dup 3) 0))) 4273 (set (match_dup 0) (match_dup 4))] 4274 "" 4275{ 4276 operands[5] = GEN_INT (~ (GET_MODE_MASK (GET_MODE (operands[1])) 4277 << INTVAL (operands[2]))); 4278}) 4279 4280;; For the unaligned byte and halfword cases, we use code similar to that 4281;; in the ;; Architecture book, but reordered to lower the number of registers 4282;; required. Operand 0 is the address. Operand 1 is the data to store. 4283;; Operands 2, 3, and 4 are DImode temporaries, where operands 2 and 4 may 4284;; be the same temporary, if desired. If the address is in a register, 4285;; operand 2 can be that register. 4286 4287(define_expand "unaligned_store<mode>" 4288 [(set (match_operand:DI 3 "register_operand") 4289 (mem:DI (and:DI (match_operand:DI 0 "address_operand") 4290 (const_int -8)))) 4291 (set (match_operand:DI 2 "register_operand") 4292 (match_dup 0)) 4293 (set (match_dup 3) 4294 (and:DI (not:DI (ashift:DI (match_dup 5) 4295 (ashift:DI (match_dup 2) (const_int 3)))) 4296 (match_dup 3))) 4297 (set (match_operand:DI 4 "register_operand") 4298 (ashift:DI (zero_extend:DI 4299 (match_operand:I12MODE 1 "register_operand")) 4300 (ashift:DI (match_dup 2) (const_int 3)))) 4301 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3))) 4302 (set (mem:DI (and:DI (match_dup 0) (const_int -8))) 4303 (match_dup 4))] 4304 "" 4305 "operands[5] = GEN_INT (GET_MODE_MASK (<MODE>mode));") 4306 4307;; Here are the define_expand's for QI and HI moves that use the above 4308;; patterns. We have the normal sets, plus the ones that need scratch 4309;; registers for reload. 4310 4311(define_expand "mov<mode>" 4312 [(set (match_operand:I12MODE 0 "nonimmediate_operand") 4313 (match_operand:I12MODE 1 "general_operand"))] 4314 "" 4315{ 4316 if (TARGET_BWX 4317 ? alpha_expand_mov (<MODE>mode, operands) 4318 : alpha_expand_mov_nobwx (<MODE>mode, operands)) 4319 DONE; 4320}) 4321 4322(define_insn "*movqi" 4323 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,m") 4324 (match_operand:QI 1 "input_operand" "rJ,n,m,rJ"))] 4325 "register_operand (operands[0], QImode) 4326 || reg_or_0_operand (operands[1], QImode)" 4327 "@ 4328 bis $31,%r1,%0 4329 lda %0,%L1($31) 4330 ldbu %0,%1 4331 stb %r1,%0" 4332 [(set_attr "type" "ilog,iadd,ild,ist") 4333 (set_attr "isa" "*,*,bwx,bwx")]) 4334 4335(define_insn "*movhi" 4336 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m") 4337 (match_operand:HI 1 "input_operand" "rJ,n,m,rJ"))] 4338 "register_operand (operands[0], HImode) 4339 || reg_or_0_operand (operands[1], HImode)" 4340 "@ 4341 bis $31,%r1,%0 4342 lda %0,%L1($31) 4343 ldwu %0,%1 4344 stw %r1,%0" 4345 [(set_attr "type" "ilog,iadd,ild,ist") 4346 (set_attr "isa" "*,*,bwx,bwx")]) 4347 4348;; We need to hook into the extra support that we have for HImode 4349;; reloads when BWX insns are not available. 4350(define_expand "movcqi" 4351 [(set (match_operand:CQI 0 "nonimmediate_operand") 4352 (match_operand:CQI 1 "general_operand"))] 4353 "!TARGET_BWX" 4354{ 4355 if (GET_CODE (operands[0]) == CONCAT || GET_CODE (operands[1]) == CONCAT) 4356 ; 4357 else if (!any_memory_operand (operands[0], CQImode)) 4358 { 4359 if (!any_memory_operand (operands[1], CQImode)) 4360 { 4361 emit_move_insn (gen_lowpart (HImode, operands[0]), 4362 gen_lowpart (HImode, operands[1])); 4363 DONE; 4364 } 4365 if (aligned_memory_operand (operands[1], CQImode)) 4366 { 4367 bool done; 4368 do_aligned1: 4369 operands[1] = gen_lowpart (HImode, operands[1]); 4370 do_aligned2: 4371 operands[0] = gen_lowpart (HImode, operands[0]); 4372 done = alpha_expand_mov_nobwx (HImode, operands); 4373 gcc_assert (done); 4374 DONE; 4375 } 4376 } 4377 else if (aligned_memory_operand (operands[0], CQImode)) 4378 { 4379 if (MEM_P (operands[1])) 4380 { 4381 rtx x = gen_reg_rtx (HImode); 4382 emit_move_insn (gen_lowpart (CQImode, x), operands[1]); 4383 operands[1] = x; 4384 goto do_aligned2; 4385 } 4386 goto do_aligned1; 4387 } 4388 4389 gcc_assert (!reload_in_progress); 4390 emit_move_complex_parts (operands[0], operands[1]); 4391 DONE; 4392}) 4393 4394;; Here are the versions for reload. 4395;; 4396;; The aligned input case is recognized early in alpha_secondary_reload 4397;; in order to avoid allocating an unnecessary scratch register. 4398;; 4399;; Note that in the unaligned cases we know that the operand must not be 4400;; a pseudo-register because stack slots are always aligned references. 4401 4402(define_expand "reload_in<mode>" 4403 [(parallel [(match_operand:RELOAD12 0 "register_operand" "=r") 4404 (match_operand:RELOAD12 1 "any_memory_operand" "m") 4405 (match_operand:TI 2 "register_operand" "=&r")])] 4406 "!TARGET_BWX" 4407{ 4408 rtx scratch, seq, addr; 4409 unsigned regno = REGNO (operands[2]); 4410 4411 /* It is possible that one of the registers we got for operands[2] 4412 might coincide with that of operands[0] (which is why we made 4413 it TImode). Pick the other one to use as our scratch. */ 4414 if (regno == REGNO (operands[0])) 4415 regno++; 4416 scratch = gen_rtx_REG (DImode, regno); 4417 4418 addr = get_unaligned_address (operands[1]); 4419 operands[0] = gen_rtx_REG (DImode, REGNO (operands[0])); 4420 seq = gen_unaligned_load<reloadmode> (operands[0], addr, 4421 scratch, operands[0]); 4422 alpha_set_memflags (seq, operands[1]); 4423 4424 emit_insn (seq); 4425 DONE; 4426}) 4427 4428(define_expand "reload_out<mode>" 4429 [(parallel [(match_operand:RELOAD12 0 "any_memory_operand" "=m") 4430 (match_operand:RELOAD12 1 "register_operand" "r") 4431 (match_operand:TI 2 "register_operand" "=&r")])] 4432 "!TARGET_BWX" 4433{ 4434 unsigned regno = REGNO (operands[2]); 4435 4436 if (<MODE>mode == CQImode) 4437 { 4438 operands[0] = gen_lowpart (HImode, operands[0]); 4439 operands[1] = gen_lowpart (HImode, operands[1]); 4440 } 4441 4442 if (aligned_memory_operand (operands[0], <MODE>mode)) 4443 { 4444 emit_insn (gen_reload_out<reloadmode>_aligned 4445 (operands[0], operands[1], 4446 gen_rtx_REG (SImode, regno), 4447 gen_rtx_REG (SImode, regno + 1))); 4448 } 4449 else 4450 { 4451 rtx addr = get_unaligned_address (operands[0]); 4452 rtx scratch1 = gen_rtx_REG (DImode, regno); 4453 rtx scratch2 = gen_rtx_REG (DImode, regno + 1); 4454 rtx scratch3 = scratch1; 4455 rtx seq; 4456 4457 if (REG_P (addr)) 4458 scratch1 = addr; 4459 4460 seq = gen_unaligned_store<reloadmode> (addr, operands[1], scratch1, 4461 scratch2, scratch3); 4462 alpha_set_memflags (seq, operands[0]); 4463 emit_insn (seq); 4464 } 4465 DONE; 4466}) 4467 4468;; Helpers for the above. The way reload is structured, we can't 4469;; always get a proper address for a stack slot during reload_foo 4470;; expansion, so we must delay our address manipulations until after. 4471 4472(define_insn_and_split "reload_in<mode>_aligned" 4473 [(set (match_operand:I12MODE 0 "register_operand" "=r") 4474 (match_operand:I12MODE 1 "memory_operand" "m"))] 4475 "!TARGET_BWX && (reload_in_progress || reload_completed)" 4476 "#" 4477 "!TARGET_BWX && reload_completed" 4478 [(const_int 0)] 4479{ 4480 rtx aligned_mem, bitnum; 4481 get_aligned_mem (operands[1], &aligned_mem, &bitnum); 4482 emit_insn (gen_aligned_load<reloadmode> 4483 (gen_lowpart (DImode, operands[0]), aligned_mem, bitnum, 4484 gen_rtx_REG (SImode, REGNO (operands[0])))); 4485 DONE; 4486}) 4487 4488(define_insn_and_split "reload_out<mode>_aligned" 4489 [(set (match_operand:I12MODE 0 "memory_operand" "=m") 4490 (match_operand:I12MODE 1 "register_operand" "r")) 4491 (clobber (match_operand:SI 2 "register_operand" "=&r")) 4492 (clobber (match_operand:SI 3 "register_operand" "=&r"))] 4493 "!TARGET_BWX && (reload_in_progress || reload_completed)" 4494 "#" 4495 "!TARGET_BWX && reload_completed" 4496 [(const_int 0)] 4497{ 4498 rtx aligned_mem, bitnum; 4499 get_aligned_mem (operands[0], &aligned_mem, &bitnum); 4500 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum, 4501 operands[2], operands[3])); 4502 DONE; 4503}) 4504 4505;; Vector operations 4506 4507(define_mode_iterator VEC [V8QI V4HI V2SI]) 4508(define_mode_iterator VEC12 [V8QI V4HI]) 4509 4510(define_expand "mov<mode>" 4511 [(set (match_operand:VEC 0 "nonimmediate_operand") 4512 (match_operand:VEC 1 "general_operand"))] 4513 "" 4514{ 4515 if (alpha_expand_mov (<MODE>mode, operands)) 4516 DONE; 4517}) 4518 4519(define_split 4520 [(set (match_operand:VEC 0 "register_operand") 4521 (match_operand:VEC 1 "non_zero_const_operand"))] 4522 "" 4523 [(const_int 0)] 4524{ 4525 if (alpha_split_const_mov (<MODE>mode, operands)) 4526 DONE; 4527 else 4528 FAIL; 4529}) 4530 4531 4532(define_expand "movmisalign<mode>" 4533 [(set (match_operand:VEC 0 "nonimmediate_operand") 4534 (match_operand:VEC 1 "general_operand"))] 4535 "" 4536{ 4537 alpha_expand_movmisalign (<MODE>mode, operands); 4538 DONE; 4539}) 4540 4541(define_insn "*mov<mode>_fix" 4542 [(set (match_operand:VEC 0 "nonimmediate_operand" "=r,r,r,m,*f,*f,m,r,*f") 4543 (match_operand:VEC 1 "input_operand" "rW,i,m,rW,*fW,m,*f,*f,r"))] 4544 "register_operand (operands[0], <MODE>mode) 4545 || reg_or_0_operand (operands[1], <MODE>mode)" 4546 "@ 4547 bis $31,%r1,%0 4548 # 4549 ldq %0,%1 4550 stq %r1,%0 4551 cpys %R1,%R1,%0 4552 ldt %0,%1 4553 stt %R1,%0 4554 ftoit %1,%0 4555 itoft %1,%0" 4556 [(set_attr "type" "ilog,multi,ild,ist,fcpys,fld,fst,ftoi,itof") 4557 (set_attr "isa" "*,*,*,*,*,*,*,fix,fix")]) 4558 4559(define_insn "<code><mode>3" 4560 [(set (match_operand:VEC12 0 "register_operand" "=r") 4561 (any_maxmin:VEC12 4562 (match_operand:VEC12 1 "reg_or_0_operand" "rW") 4563 (match_operand:VEC12 2 "reg_or_0_operand" "rW")))] 4564 "TARGET_MAX" 4565 "<maxmin><modesuffix> %r1,%r2,%0" 4566 [(set_attr "type" "mvi")]) 4567 4568(define_insn "one_cmpl<mode>2" 4569 [(set (match_operand:VEC 0 "register_operand" "=r") 4570 (not:VEC (match_operand:VEC 1 "register_operand" "r")))] 4571 "" 4572 "ornot $31,%1,%0" 4573 [(set_attr "type" "ilog")]) 4574 4575(define_insn "and<mode>3" 4576 [(set (match_operand:VEC 0 "register_operand" "=r") 4577 (and:VEC (match_operand:VEC 1 "register_operand" "r") 4578 (match_operand:VEC 2 "register_operand" "r")))] 4579 "" 4580 "and %1,%2,%0" 4581 [(set_attr "type" "ilog")]) 4582 4583(define_insn "*andnot<mode>3" 4584 [(set (match_operand:VEC 0 "register_operand" "=r") 4585 (and:VEC (not:VEC (match_operand:VEC 1 "register_operand" "r")) 4586 (match_operand:VEC 2 "register_operand" "r")))] 4587 "" 4588 "bic %2,%1,%0" 4589 [(set_attr "type" "ilog")]) 4590 4591(define_insn "ior<mode>3" 4592 [(set (match_operand:VEC 0 "register_operand" "=r") 4593 (ior:VEC (match_operand:VEC 1 "register_operand" "r") 4594 (match_operand:VEC 2 "register_operand" "r")))] 4595 "" 4596 "bis %1,%2,%0" 4597 [(set_attr "type" "ilog")]) 4598 4599(define_insn "*iornot<mode>3" 4600 [(set (match_operand:VEC 0 "register_operand" "=r") 4601 (ior:VEC (not:DI (match_operand:VEC 1 "register_operand" "r")) 4602 (match_operand:VEC 2 "register_operand" "r")))] 4603 "" 4604 "ornot %2,%1,%0" 4605 [(set_attr "type" "ilog")]) 4606 4607(define_insn "xor<mode>3" 4608 [(set (match_operand:VEC 0 "register_operand" "=r") 4609 (xor:VEC (match_operand:VEC 1 "register_operand" "r") 4610 (match_operand:VEC 2 "register_operand" "r")))] 4611 "" 4612 "xor %1,%2,%0" 4613 [(set_attr "type" "ilog")]) 4614 4615(define_insn "*xornot<mode>3" 4616 [(set (match_operand:VEC 0 "register_operand" "=r") 4617 (not:VEC (xor:VEC (match_operand:VEC 1 "register_operand" "r") 4618 (match_operand:VEC 2 "register_operand" "r"))))] 4619 "" 4620 "eqv %1,%2,%0" 4621 [(set_attr "type" "ilog")]) 4622 4623(define_expand "vec_shl_<mode>" 4624 [(set (match_operand:VEC 0 "register_operand") 4625 (ashift:DI (match_operand:VEC 1 "register_operand") 4626 (match_operand:DI 2 "reg_or_6bit_operand")))] 4627 "" 4628{ 4629 operands[0] = gen_lowpart (DImode, operands[0]); 4630 operands[1] = gen_lowpart (DImode, operands[1]); 4631}) 4632 4633(define_expand "vec_shr_<mode>" 4634 [(set (match_operand:VEC 0 "register_operand") 4635 (lshiftrt:DI (match_operand:VEC 1 "register_operand") 4636 (match_operand:DI 2 "reg_or_6bit_operand")))] 4637 "" 4638{ 4639 operands[0] = gen_lowpart (DImode, operands[0]); 4640 operands[1] = gen_lowpart (DImode, operands[1]); 4641}) 4642 4643;; Bit field extract patterns which use ext[wlq][lh] 4644 4645(define_expand "extvmisaligndi" 4646 [(set (match_operand:DI 0 "register_operand") 4647 (sign_extract:DI (match_operand:BLK 1 "memory_operand") 4648 (match_operand:DI 2 "const_int_operand") 4649 (match_operand:DI 3 "const_int_operand")))] 4650 "" 4651{ 4652 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */ 4653 if (INTVAL (operands[3]) % 8 != 0 4654 || (INTVAL (operands[2]) != 16 4655 && INTVAL (operands[2]) != 32 4656 && INTVAL (operands[2]) != 64)) 4657 FAIL; 4658 4659 alpha_expand_unaligned_load (operands[0], operands[1], 4660 INTVAL (operands[2]) / 8, 4661 INTVAL (operands[3]) / 8, 1); 4662 DONE; 4663}) 4664 4665(define_expand "extzvdi" 4666 [(set (match_operand:DI 0 "register_operand") 4667 (zero_extract:DI (match_operand:DI 1 "register_operand") 4668 (match_operand:DI 2 "const_int_operand") 4669 (match_operand:DI 3 "const_int_operand")))] 4670 "" 4671{ 4672 /* We can do 8, 16, 32 and 64 bit fields, if aligned on byte boundaries. */ 4673 if (INTVAL (operands[3]) % 8 != 0 4674 || (INTVAL (operands[2]) != 8 4675 && INTVAL (operands[2]) != 16 4676 && INTVAL (operands[2]) != 32 4677 && INTVAL (operands[2]) != 64)) 4678 FAIL; 4679}) 4680 4681(define_expand "extzvmisaligndi" 4682 [(set (match_operand:DI 0 "register_operand") 4683 (zero_extract:DI (match_operand:BLK 1 "memory_operand") 4684 (match_operand:DI 2 "const_int_operand") 4685 (match_operand:DI 3 "const_int_operand")))] 4686 "" 4687{ 4688 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. 4689 We fail 8-bit fields, falling back on a simple byte load. */ 4690 if (INTVAL (operands[3]) % 8 != 0 4691 || (INTVAL (operands[2]) != 16 4692 && INTVAL (operands[2]) != 32 4693 && INTVAL (operands[2]) != 64)) 4694 FAIL; 4695 4696 alpha_expand_unaligned_load (operands[0], operands[1], 4697 INTVAL (operands[2]) / 8, 4698 INTVAL (operands[3]) / 8, 0); 4699 DONE; 4700}) 4701 4702(define_expand "insvmisaligndi" 4703 [(set (zero_extract:DI (match_operand:BLK 0 "memory_operand") 4704 (match_operand:DI 1 "const_int_operand") 4705 (match_operand:DI 2 "const_int_operand")) 4706 (match_operand:DI 3 "register_operand"))] 4707 "" 4708{ 4709 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */ 4710 if (INTVAL (operands[2]) % 8 != 0 4711 || (INTVAL (operands[1]) != 16 4712 && INTVAL (operands[1]) != 32 4713 && INTVAL (operands[1]) != 64)) 4714 FAIL; 4715 4716 alpha_expand_unaligned_store (operands[0], operands[3], 4717 INTVAL (operands[1]) / 8, 4718 INTVAL (operands[2]) / 8); 4719 DONE; 4720}) 4721 4722;; Block move/clear, see alpha.c for more details. 4723;; Argument 0 is the destination 4724;; Argument 1 is the source 4725;; Argument 2 is the length 4726;; Argument 3 is the alignment 4727 4728(define_expand "movmemqi" 4729 [(parallel [(set (match_operand:BLK 0 "memory_operand") 4730 (match_operand:BLK 1 "memory_operand")) 4731 (use (match_operand:DI 2 "immediate_operand")) 4732 (use (match_operand:DI 3 "immediate_operand"))])] 4733 "" 4734{ 4735 if (alpha_expand_block_move (operands)) 4736 DONE; 4737 else 4738 FAIL; 4739}) 4740 4741(define_expand "movmemdi" 4742 [(parallel [(set (match_operand:BLK 0 "memory_operand") 4743 (match_operand:BLK 1 "memory_operand")) 4744 (use (match_operand:DI 2 "immediate_operand")) 4745 (use (match_operand:DI 3 "immediate_operand")) 4746 (use (match_dup 4)) 4747 (clobber (reg:DI 25)) 4748 (clobber (reg:DI 16)) 4749 (clobber (reg:DI 17)) 4750 (clobber (reg:DI 18)) 4751 (clobber (reg:DI 19)) 4752 (clobber (reg:DI 20)) 4753 (clobber (reg:DI 26)) 4754 (clobber (reg:DI 27))])] 4755 "TARGET_ABI_OPEN_VMS" 4756 "operands[4] = gen_rtx_SYMBOL_REF (Pmode, \"OTS$MOVE\");") 4757 4758(define_insn "*movmemdi_1" 4759 [(set (match_operand:BLK 0 "memory_operand" "=m,m") 4760 (match_operand:BLK 1 "memory_operand" "m,m")) 4761 (use (match_operand:DI 2 "nonmemory_operand" "r,i")) 4762 (use (match_operand:DI 3 "immediate_operand")) 4763 (use (match_operand:DI 4 "call_operand" "i,i")) 4764 (clobber (reg:DI 25)) 4765 (clobber (reg:DI 16)) 4766 (clobber (reg:DI 17)) 4767 (clobber (reg:DI 18)) 4768 (clobber (reg:DI 19)) 4769 (clobber (reg:DI 20)) 4770 (clobber (reg:DI 26)) 4771 (clobber (reg:DI 27))] 4772 "TARGET_ABI_OPEN_VMS" 4773{ 4774 operands [5] = alpha_use_linkage (operands [4], false, true); 4775 switch (which_alternative) 4776 { 4777 case 0: 4778 return "lda $16,%0\;bis $31,%2,$17\;lda $18,%1\;ldq $26,%5\;lda $25,3($31)\;jsr $26,%4\;ldq $27,0($29)"; 4779 case 1: 4780 return "lda $16,%0\;lda $17,%2($31)\;lda $18,%1\;ldq $26,%5\;lda $25,3($31)\;jsr $26,%4\;ldq $27,0($29)"; 4781 default: 4782 gcc_unreachable (); 4783 } 4784} 4785 [(set_attr "type" "multi") 4786 (set_attr "length" "28")]) 4787 4788(define_expand "setmemqi" 4789 [(parallel [(set (match_operand:BLK 0 "memory_operand") 4790 (match_operand 2 "const_int_operand")) 4791 (use (match_operand:DI 1 "immediate_operand")) 4792 (use (match_operand:DI 3 "immediate_operand"))])] 4793 "" 4794{ 4795 /* If value to set is not zero, use the library routine. */ 4796 if (operands[2] != const0_rtx) 4797 FAIL; 4798 4799 if (alpha_expand_block_clear (operands)) 4800 DONE; 4801 else 4802 FAIL; 4803}) 4804 4805(define_expand "setmemdi" 4806 [(parallel [(set (match_operand:BLK 0 "memory_operand") 4807 (match_operand 2 "const_int_operand")) 4808 (use (match_operand:DI 1 "immediate_operand")) 4809 (use (match_operand:DI 3 "immediate_operand")) 4810 (use (match_dup 4)) 4811 (clobber (reg:DI 25)) 4812 (clobber (reg:DI 16)) 4813 (clobber (reg:DI 17)) 4814 (clobber (reg:DI 26)) 4815 (clobber (reg:DI 27))])] 4816 "TARGET_ABI_OPEN_VMS" 4817{ 4818 /* If value to set is not zero, use the library routine. */ 4819 if (operands[2] != const0_rtx) 4820 FAIL; 4821 4822 operands[4] = gen_rtx_SYMBOL_REF (Pmode, "OTS$ZERO"); 4823}) 4824 4825(define_insn "*clrmemdi_1" 4826 [(set (match_operand:BLK 0 "memory_operand" "=m,m") 4827 (const_int 0)) 4828 (use (match_operand:DI 1 "nonmemory_operand" "r,i")) 4829 (use (match_operand:DI 2 "immediate_operand")) 4830 (use (match_operand:DI 3 "call_operand" "i,i")) 4831 (clobber (reg:DI 25)) 4832 (clobber (reg:DI 16)) 4833 (clobber (reg:DI 17)) 4834 (clobber (reg:DI 26)) 4835 (clobber (reg:DI 27))] 4836 "TARGET_ABI_OPEN_VMS" 4837{ 4838 operands [4] = alpha_use_linkage (operands [3], false, true); 4839 switch (which_alternative) 4840 { 4841 case 0: 4842 return "lda $16,%0\;bis $31,%1,$17\;ldq $26,%4\;lda $25,2($31)\;jsr $26,%3\;ldq $27,0($29)"; 4843 case 1: 4844 return "lda $16,%0\;lda $17,%1($31)\;ldq $26,%4\;lda $25,2($31)\;jsr $26,%3\;ldq $27,0($29)"; 4845 default: 4846 gcc_unreachable (); 4847 } 4848} 4849 [(set_attr "type" "multi") 4850 (set_attr "length" "24")]) 4851 4852 4853;; Subroutine of stack space allocation. Perform a stack probe. 4854(define_expand "stack_probe_internal" 4855 [(set (match_dup 1) (match_operand:DI 0 "const_int_operand"))] 4856 "" 4857{ 4858 operands[1] = gen_rtx_MEM (DImode, plus_constant (Pmode, stack_pointer_rtx, 4859 INTVAL (operands[0]))); 4860 MEM_VOLATILE_P (operands[1]) = 1; 4861 4862 operands[0] = const0_rtx; 4863}) 4864 4865;; This is how we allocate stack space. If we are allocating a 4866;; constant amount of space and we know it is less than 4096 4867;; bytes, we need do nothing. 4868;; 4869;; If it is more than 4096 bytes, we need to probe the stack 4870;; periodically. 4871(define_expand "allocate_stack" 4872 [(set (reg:DI 30) 4873 (plus:DI (reg:DI 30) 4874 (match_operand:DI 1 "reg_or_cint_operand"))) 4875 (set (match_operand:DI 0 "register_operand" "=r") 4876 (match_dup 2))] 4877 "" 4878{ 4879 if (CONST_INT_P (operands[1]) 4880 && INTVAL (operands[1]) < 32768) 4881 { 4882 if (INTVAL (operands[1]) >= 4096) 4883 { 4884 /* We do this the same way as in the prologue and generate explicit 4885 probes. Then we update the stack by the constant. */ 4886 4887 int probed = 4096; 4888 4889 emit_insn (gen_stack_probe_internal (GEN_INT (- probed))); 4890 while (probed + 8192 < INTVAL (operands[1])) 4891 emit_insn (gen_stack_probe_internal 4892 (GEN_INT (- (probed += 8192)))); 4893 4894 if (probed + 4096 < INTVAL (operands[1])) 4895 emit_insn (gen_stack_probe_internal 4896 (GEN_INT (- INTVAL(operands[1])))); 4897 } 4898 4899 operands[1] = GEN_INT (- INTVAL (operands[1])); 4900 operands[2] = virtual_stack_dynamic_rtx; 4901 } 4902 else 4903 { 4904 rtx_code_label *out_label = 0; 4905 rtx_code_label *loop_label = gen_label_rtx (); 4906 rtx want = gen_reg_rtx (Pmode); 4907 rtx tmp = gen_reg_rtx (Pmode); 4908 rtx memref, test; 4909 4910 emit_insn (gen_subdi3 (want, stack_pointer_rtx, 4911 force_reg (Pmode, operands[1]))); 4912 4913 if (!CONST_INT_P (operands[1])) 4914 { 4915 rtx limit = GEN_INT (4096); 4916 out_label = gen_label_rtx (); 4917 test = gen_rtx_LTU (VOIDmode, operands[1], limit); 4918 emit_jump_insn 4919 (gen_cbranchdi4 (test, operands[1], limit, out_label)); 4920 } 4921 4922 emit_insn (gen_adddi3 (tmp, stack_pointer_rtx, GEN_INT (-4096))); 4923 emit_label (loop_label); 4924 memref = gen_rtx_MEM (DImode, tmp); 4925 MEM_VOLATILE_P (memref) = 1; 4926 emit_move_insn (memref, const0_rtx); 4927 emit_insn (gen_adddi3 (tmp, tmp, GEN_INT(-8192))); 4928 test = gen_rtx_GTU (VOIDmode, tmp, want); 4929 emit_jump_insn (gen_cbranchdi4 (test, tmp, want, loop_label)); 4930 4931 memref = gen_rtx_MEM (DImode, want); 4932 MEM_VOLATILE_P (memref) = 1; 4933 emit_move_insn (memref, const0_rtx); 4934 4935 if (out_label) 4936 emit_label (out_label); 4937 4938 emit_move_insn (stack_pointer_rtx, want); 4939 emit_move_insn (operands[0], virtual_stack_dynamic_rtx); 4940 DONE; 4941 } 4942}) 4943 4944;; This is used by alpha_expand_prolog to do the same thing as above, 4945;; except we cannot at that time generate new basic blocks, so we hide 4946;; the loop in this one insn. 4947 4948(define_insn "prologue_stack_probe_loop" 4949 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r") 4950 (match_operand:DI 1 "register_operand" "r")] 4951 UNSPECV_PSPL)] 4952 "" 4953{ 4954 operands[2] = gen_label_rtx (); 4955 (*targetm.asm_out.internal_label) (asm_out_file, "L", 4956 CODE_LABEL_NUMBER (operands[2])); 4957 4958 return "stq $31,-8192(%1)\;subq %0,1,%0\;lda %1,-8192(%1)\;bne %0,%l2"; 4959} 4960 [(set_attr "length" "16") 4961 (set_attr "type" "multi")]) 4962 4963(define_expand "prologue" 4964 [(const_int 0)] 4965 "" 4966{ 4967 alpha_expand_prologue (); 4968 DONE; 4969}) 4970 4971;; These take care of emitting the ldgp insn in the prologue. This will be 4972;; an lda/ldah pair and we want to align them properly. So we have two 4973;; unspec_volatile insns, the first of which emits the ldgp assembler macro 4974;; and the second of which emits nothing. However, both are marked as type 4975;; IADD (the default) so the alignment code in alpha.c does the right thing 4976;; with them. 4977 4978(define_expand "prologue_ldgp" 4979 [(set (match_dup 0) 4980 (unspec_volatile:DI [(match_dup 1) (match_dup 2)] UNSPECV_LDGP1)) 4981 (set (match_dup 0) 4982 (unspec_volatile:DI [(match_dup 0) (match_dup 2)] UNSPECV_PLDGP2))] 4983 "" 4984{ 4985 operands[0] = pic_offset_table_rtx; 4986 operands[1] = gen_rtx_REG (Pmode, 27); 4987 operands[2] = (TARGET_EXPLICIT_RELOCS 4988 ? GEN_INT (alpha_next_sequence_number++) 4989 : const0_rtx); 4990}) 4991 4992(define_insn "*ldgp_er_1" 4993 [(set (match_operand:DI 0 "register_operand" "=r") 4994 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r") 4995 (match_operand 2 "const_int_operand")] 4996 UNSPECV_LDGP1))] 4997 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 4998 "ldah %0,0(%1)\t\t!gpdisp!%2" 4999 [(set_attr "cannot_copy" "true")]) 5000 5001(define_insn "*ldgp_er_2" 5002 [(set (match_operand:DI 0 "register_operand" "=r") 5003 (unspec:DI [(match_operand:DI 1 "register_operand" "r") 5004 (match_operand 2 "const_int_operand")] 5005 UNSPEC_LDGP2))] 5006 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 5007 "lda %0,0(%1)\t\t!gpdisp!%2" 5008 [(set_attr "cannot_copy" "true")]) 5009 5010(define_insn "*prologue_ldgp_er_2" 5011 [(set (match_operand:DI 0 "register_operand" "=r") 5012 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r") 5013 (match_operand 2 "const_int_operand")] 5014 UNSPECV_PLDGP2))] 5015 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 5016 "lda %0,0(%1)\t\t!gpdisp!%2\n$%~..ng:" 5017 [(set_attr "cannot_copy" "true")]) 5018 5019(define_insn "*prologue_ldgp_1" 5020 [(set (match_operand:DI 0 "register_operand" "=r") 5021 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r") 5022 (match_operand 2 "const_int_operand")] 5023 UNSPECV_LDGP1))] 5024 "" 5025 "ldgp %0,0(%1)\n$%~..ng:" 5026 [(set_attr "cannot_copy" "true")]) 5027 5028(define_insn "*prologue_ldgp_2" 5029 [(set (match_operand:DI 0 "register_operand" "=r") 5030 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r") 5031 (match_operand 2 "const_int_operand")] 5032 UNSPECV_PLDGP2))] 5033 "" 5034 ) 5035 5036;; The _mcount profiling hook has special calling conventions, and 5037;; does not clobber all the registers that a normal call would. So 5038;; hide the fact this is a call at all. 5039 5040(define_insn "prologue_mcount" 5041 [(unspec_volatile [(const_int 0)] UNSPECV_MCOUNT)] 5042 "" 5043{ 5044 if (TARGET_EXPLICIT_RELOCS) 5045 /* Note that we cannot use a lituse_jsr reloc, since _mcount 5046 cannot be called via the PLT. */ 5047 return "ldq $28,_mcount($29)\t\t!literal\;jsr $28,($28),_mcount"; 5048 else 5049 return "lda $28,_mcount\;jsr $28,($28),_mcount"; 5050} 5051 [(set_attr "type" "multi") 5052 (set_attr "length" "8")]) 5053 5054(define_insn "init_fp" 5055 [(set (match_operand:DI 0 "register_operand" "=r") 5056 (match_operand:DI 1 "register_operand" "r")) 5057 (clobber (mem:BLK (match_operand:DI 2 "register_operand" "=r")))] 5058 "" 5059 "bis $31,%1,%0") 5060 5061(define_expand "epilogue" 5062 [(return)] 5063 "" 5064 "alpha_expand_epilogue ();") 5065 5066(define_expand "sibcall_epilogue" 5067 [(return)] 5068 "TARGET_ABI_OSF" 5069{ 5070 alpha_expand_epilogue (); 5071 DONE; 5072}) 5073 5074(define_expand "builtin_longjmp" 5075 [(use (match_operand:DI 0 "register_operand" "r"))] 5076 "TARGET_ABI_OSF" 5077{ 5078 /* The elements of the buffer are, in order: */ 5079 rtx fp = gen_rtx_MEM (Pmode, operands[0]); 5080 rtx lab = gen_rtx_MEM (Pmode, plus_constant (Pmode, operands[0], 8)); 5081 rtx stack = gen_rtx_MEM (Pmode, plus_constant (Pmode, operands[0], 16)); 5082 rtx pv = gen_rtx_REG (Pmode, 27); 5083 5084 /* This bit is the same as expand_builtin_longjmp. */ 5085 emit_move_insn (hard_frame_pointer_rtx, fp); 5086 emit_move_insn (pv, lab); 5087 emit_stack_restore (SAVE_NONLOCAL, stack); 5088 emit_use (hard_frame_pointer_rtx); 5089 emit_use (stack_pointer_rtx); 5090 5091 /* Load the label we are jumping through into $27 so that we know 5092 where to look for it when we get back to setjmp's function for 5093 restoring the gp. */ 5094 emit_jump_insn (gen_builtin_longjmp_internal (pv)); 5095 emit_barrier (); 5096 DONE; 5097}) 5098 5099;; This is effectively a copy of indirect_jump, but constrained such 5100;; that register renaming cannot foil our cunning plan with $27. 5101(define_insn "builtin_longjmp_internal" 5102 [(set (pc) 5103 (unspec_volatile [(match_operand:DI 0 "register_operand" "c")] 5104 UNSPECV_LONGJMP))] 5105 "" 5106 "jmp $31,(%0),0" 5107 [(set_attr "type" "ibr")]) 5108 5109(define_expand "builtin_setjmp_receiver" 5110 [(unspec_volatile [(label_ref (match_operand 0))] UNSPECV_SETJMPR)] 5111 "TARGET_ABI_OSF") 5112 5113(define_insn_and_split "*builtin_setjmp_receiver_1" 5114 [(unspec_volatile [(match_operand 0)] UNSPECV_SETJMPR)] 5115 "TARGET_ABI_OSF" 5116{ 5117 if (TARGET_EXPLICIT_RELOCS) 5118 return "#"; 5119 else 5120 return "br $27,$LSJ%=\n$LSJ%=:\;ldgp $29,0($27)"; 5121} 5122 "&& TARGET_EXPLICIT_RELOCS && reload_completed" 5123 [(set (match_dup 1) 5124 (unspec_volatile:DI [(match_dup 2) (match_dup 3)] UNSPECV_LDGP1)) 5125 (set (match_dup 1) 5126 (unspec:DI [(match_dup 1) (match_dup 3)] UNSPEC_LDGP2))] 5127{ 5128 if (prev_nonnote_insn (curr_insn) != XEXP (operands[0], 0)) 5129 emit_insn (gen_rtx_UNSPEC_VOLATILE (VOIDmode, gen_rtvec (1, operands[0]), 5130 UNSPECV_SETJMPR_ER)); 5131 operands[1] = pic_offset_table_rtx; 5132 operands[2] = gen_rtx_REG (Pmode, 27); 5133 operands[3] = GEN_INT (alpha_next_sequence_number++); 5134} 5135 [(set_attr "length" "12") 5136 (set_attr "type" "multi")]) 5137 5138(define_insn "*builtin_setjmp_receiver_er_sl_1" 5139 [(unspec_volatile [(match_operand 0)] UNSPECV_SETJMPR_ER)] 5140 "TARGET_ABI_OSF && TARGET_EXPLICIT_RELOCS" 5141 "lda $27,$LSJ%=-%l0($27)\n$LSJ%=:") 5142 5143;; When flag_reorder_blocks_and_partition is in effect, compiler puts 5144;; exception landing pads in a cold section. To prevent inter-section offset 5145;; calculation, a jump to original landing pad is emitted in the place of the 5146;; original landing pad. Since landing pad is moved, RA-relative GP 5147;; calculation in the prologue of landing pad breaks. To solve this problem, 5148;; we use alternative GP load approach. 5149 5150(define_expand "exception_receiver" 5151 [(unspec_volatile [(match_dup 0)] UNSPECV_EHR)] 5152 "TARGET_ABI_OSF" 5153{ 5154 if (flag_reorder_blocks_and_partition) 5155 operands[0] = copy_rtx (alpha_gp_save_rtx ()); 5156 else 5157 operands[0] = const0_rtx; 5158}) 5159 5160(define_insn "*exception_receiver_2" 5161 [(unspec_volatile [(match_operand:DI 0 "memory_operand" "m")] UNSPECV_EHR)] 5162 "TARGET_ABI_OSF && flag_reorder_blocks_and_partition" 5163 "ldq $29,%0" 5164 [(set_attr "type" "ild")]) 5165 5166(define_insn_and_split "*exception_receiver_1" 5167 [(unspec_volatile [(const_int 0)] UNSPECV_EHR)] 5168 "TARGET_ABI_OSF" 5169{ 5170 if (TARGET_EXPLICIT_RELOCS) 5171 return "#"; 5172 else 5173 return "ldgp $29,0($26)"; 5174} 5175 "&& TARGET_EXPLICIT_RELOCS && reload_completed" 5176 [(set (match_dup 0) 5177 (unspec_volatile:DI [(match_dup 1) (match_dup 2)] UNSPECV_LDGP1)) 5178 (set (match_dup 0) 5179 (unspec:DI [(match_dup 0) (match_dup 2)] UNSPEC_LDGP2))] 5180{ 5181 operands[0] = pic_offset_table_rtx; 5182 operands[1] = gen_rtx_REG (Pmode, 26); 5183 operands[2] = GEN_INT (alpha_next_sequence_number++); 5184} 5185 [(set_attr "length" "8") 5186 (set_attr "type" "multi")]) 5187 5188(define_expand "nonlocal_goto_receiver" 5189 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE) 5190 (set (reg:DI 27) (mem:DI (reg:DI 29))) 5191 (unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE) 5192 (use (reg:DI 27))] 5193 "TARGET_ABI_OPEN_VMS") 5194 5195(define_insn "arg_home" 5196 [(unspec [(const_int 0)] UNSPEC_ARG_HOME) 5197 (use (reg:DI 1)) 5198 (use (reg:DI 25)) 5199 (use (reg:DI 16)) 5200 (use (reg:DI 17)) 5201 (use (reg:DI 18)) 5202 (use (reg:DI 19)) 5203 (use (reg:DI 20)) 5204 (use (reg:DI 21)) 5205 (use (reg:DI 48)) 5206 (use (reg:DI 49)) 5207 (use (reg:DI 50)) 5208 (use (reg:DI 51)) 5209 (use (reg:DI 52)) 5210 (use (reg:DI 53)) 5211 (clobber (mem:BLK (const_int 0))) 5212 (clobber (reg:DI 24)) 5213 (clobber (reg:DI 25)) 5214 (clobber (reg:DI 0))] 5215 "TARGET_ABI_OPEN_VMS" 5216 "lda $0,OTS$HOME_ARGS\;ldq $0,8($0)\;jsr $0,OTS$HOME_ARGS" 5217 [(set_attr "length" "16") 5218 (set_attr "type" "multi")]) 5219 5220;; Prefetch data. 5221;; 5222;; On EV4, these instructions are nops -- no load occurs. 5223;; 5224;; On EV5, these instructions act as a normal load, and thus can trap 5225;; if the address is invalid. The OS may (or may not) handle this in 5226;; the entMM fault handler and suppress the fault. If so, then this 5227;; has the effect of a read prefetch instruction. 5228;; 5229;; On EV6, these become official prefetch instructions. 5230 5231(define_insn "prefetch" 5232 [(prefetch (match_operand:DI 0 "address_operand" "p") 5233 (match_operand:DI 1 "const_int_operand" "n") 5234 (match_operand:DI 2 "const_int_operand" "n"))] 5235 "TARGET_FIXUP_EV5_PREFETCH || alpha_cpu == PROCESSOR_EV6" 5236{ 5237 /* Interpret "no temporal locality" as this data should be evicted once 5238 it is used. The "evict next" alternatives load the data into the cache 5239 and leave the LRU eviction counter pointing to that block. */ 5240 static const char * const alt[2][2] = { 5241 { 5242 "ldq $31,%a0", /* read, evict next */ 5243 "ldl $31,%a0", /* read, evict last */ 5244 }, 5245 { 5246 "ldt $f31,%a0", /* write, evict next */ 5247 "lds $f31,%a0", /* write, evict last */ 5248 } 5249 }; 5250 5251 bool write = INTVAL (operands[1]) != 0; 5252 bool lru = INTVAL (operands[2]) != 0; 5253 5254 return alt[write][lru]; 5255} 5256 [(set_attr "type" "ild")]) 5257 5258;; Close the trap shadow of preceding instructions. This is generated 5259;; by alpha_reorg. 5260 5261(define_insn "trapb" 5262 [(unspec_volatile [(const_int 0)] UNSPECV_TRAPB)] 5263 "" 5264 "trapb" 5265 [(set_attr "type" "misc")]) 5266 5267;; No-op instructions used by machine-dependent reorg to preserve 5268;; alignment for instruction issue. 5269;; The Unicos/Mk assembler does not support these opcodes. 5270 5271(define_insn "nop" 5272 [(const_int 0)] 5273 "" 5274 "bis $31,$31,$31" 5275 [(set_attr "type" "ilog")]) 5276 5277(define_insn "fnop" 5278 [(const_int 1)] 5279 "TARGET_FP" 5280 "cpys $f31,$f31,$f31" 5281 [(set_attr "type" "fcpys")]) 5282 5283(define_insn "unop" 5284 [(const_int 2)] 5285 "" 5286 "ldq_u $31,0($30)") 5287 5288(define_insn "realign" 5289 [(unspec_volatile [(match_operand 0 "immediate_operand" "i")] 5290 UNSPECV_REALIGN)] 5291 "" 5292 ".align %0 #realign") 5293 5294;; Instructions to be emitted from __builtins. 5295 5296(define_insn "builtin_cmpbge" 5297 [(set (match_operand:DI 0 "register_operand" "=r") 5298 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rJ") 5299 (match_operand:DI 2 "reg_or_8bit_operand" "rI")] 5300 UNSPEC_CMPBGE))] 5301 "" 5302 "cmpbge %r1,%2,%0" 5303 ;; The EV6 data sheets list this as ILOG. OTOH, EV6 doesn't 5304 ;; actually differentiate between ILOG and ICMP in the schedule. 5305 [(set_attr "type" "icmp")]) 5306 5307(define_expand "extbl" 5308 [(match_operand:DI 0 "register_operand") 5309 (match_operand:DI 1 "reg_or_0_operand") 5310 (match_operand:DI 2 "reg_or_8bit_operand")] 5311 "" 5312{ 5313 emit_insn (gen_extxl (operands[0], operands[1], GEN_INT (8), operands[2])); 5314 DONE; 5315}) 5316 5317(define_expand "extwl" 5318 [(match_operand:DI 0 "register_operand") 5319 (match_operand:DI 1 "reg_or_0_operand") 5320 (match_operand:DI 2 "reg_or_8bit_operand")] 5321 "" 5322{ 5323 emit_insn (gen_extxl (operands[0], operands[1], GEN_INT (16), operands[2])); 5324 DONE; 5325}) 5326 5327(define_expand "extll" 5328 [(match_operand:DI 0 "register_operand") 5329 (match_operand:DI 1 "reg_or_0_operand") 5330 (match_operand:DI 2 "reg_or_8bit_operand")] 5331 "" 5332{ 5333 emit_insn (gen_extxl (operands[0], operands[1], GEN_INT (32), operands[2])); 5334 DONE; 5335}) 5336 5337(define_expand "extql" 5338 [(match_operand:DI 0 "register_operand") 5339 (match_operand:DI 1 "reg_or_0_operand") 5340 (match_operand:DI 2 "reg_or_8bit_operand")] 5341 "" 5342{ 5343 emit_insn (gen_extxl (operands[0], operands[1], GEN_INT (64), operands[2])); 5344 DONE; 5345}) 5346 5347(define_expand "builtin_insbl" 5348 [(match_operand:DI 0 "register_operand") 5349 (match_operand:DI 1 "register_operand") 5350 (match_operand:DI 2 "reg_or_8bit_operand")] 5351 "" 5352{ 5353 operands[1] = gen_lowpart (QImode, operands[1]); 5354 emit_insn (gen_insbl (operands[0], operands[1], operands[2])); 5355 DONE; 5356}) 5357 5358(define_expand "builtin_inswl" 5359 [(match_operand:DI 0 "register_operand") 5360 (match_operand:DI 1 "register_operand") 5361 (match_operand:DI 2 "reg_or_8bit_operand")] 5362 "" 5363{ 5364 operands[1] = gen_lowpart (HImode, operands[1]); 5365 emit_insn (gen_inswl (operands[0], operands[1], operands[2])); 5366 DONE; 5367}) 5368 5369(define_expand "builtin_insll" 5370 [(match_operand:DI 0 "register_operand") 5371 (match_operand:DI 1 "register_operand") 5372 (match_operand:DI 2 "reg_or_8bit_operand")] 5373 "" 5374{ 5375 operands[1] = gen_lowpart (SImode, operands[1]); 5376 emit_insn (gen_insll (operands[0], operands[1], operands[2])); 5377 DONE; 5378}) 5379 5380(define_expand "inswh" 5381 [(match_operand:DI 0 "register_operand") 5382 (match_operand:DI 1 "register_operand") 5383 (match_operand:DI 2 "reg_or_8bit_operand")] 5384 "" 5385{ 5386 emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (16), operands[2])); 5387 DONE; 5388}) 5389 5390(define_expand "inslh" 5391 [(match_operand:DI 0 "register_operand") 5392 (match_operand:DI 1 "register_operand") 5393 (match_operand:DI 2 "reg_or_8bit_operand")] 5394 "" 5395{ 5396 emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (32), operands[2])); 5397 DONE; 5398}) 5399 5400(define_expand "insqh" 5401 [(match_operand:DI 0 "register_operand") 5402 (match_operand:DI 1 "register_operand") 5403 (match_operand:DI 2 "reg_or_8bit_operand")] 5404 "" 5405{ 5406 emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (64), operands[2])); 5407 DONE; 5408}) 5409 5410(define_expand "mskbl" 5411 [(match_operand:DI 0 "register_operand") 5412 (match_operand:DI 1 "reg_or_0_operand") 5413 (match_operand:DI 2 "reg_or_8bit_operand")] 5414 "" 5415{ 5416 rtx mask = GEN_INT (0xff); 5417 emit_insn (gen_mskxl (operands[0], operands[1], mask, operands[2])); 5418 DONE; 5419}) 5420 5421(define_expand "mskwl" 5422 [(match_operand:DI 0 "register_operand") 5423 (match_operand:DI 1 "reg_or_0_operand") 5424 (match_operand:DI 2 "reg_or_8bit_operand")] 5425 "" 5426{ 5427 rtx mask = GEN_INT (0xffff); 5428 emit_insn (gen_mskxl (operands[0], operands[1], mask, operands[2])); 5429 DONE; 5430}) 5431 5432(define_expand "mskll" 5433 [(match_operand:DI 0 "register_operand") 5434 (match_operand:DI 1 "reg_or_0_operand") 5435 (match_operand:DI 2 "reg_or_8bit_operand")] 5436 "" 5437{ 5438 rtx mask = gen_int_mode (0xffffffff, DImode); 5439 emit_insn (gen_mskxl (operands[0], operands[1], mask, operands[2])); 5440 DONE; 5441}) 5442 5443(define_expand "mskql" 5444 [(match_operand:DI 0 "register_operand") 5445 (match_operand:DI 1 "reg_or_0_operand") 5446 (match_operand:DI 2 "reg_or_8bit_operand")] 5447 "" 5448{ 5449 rtx mask = constm1_rtx; 5450 emit_insn (gen_mskxl (operands[0], operands[1], mask, operands[2])); 5451 DONE; 5452}) 5453 5454(define_expand "mskwh" 5455 [(match_operand:DI 0 "register_operand") 5456 (match_operand:DI 1 "register_operand") 5457 (match_operand:DI 2 "reg_or_8bit_operand")] 5458 "" 5459{ 5460 emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (16), operands[2])); 5461 DONE; 5462}) 5463 5464(define_expand "msklh" 5465 [(match_operand:DI 0 "register_operand") 5466 (match_operand:DI 1 "register_operand") 5467 (match_operand:DI 2 "reg_or_8bit_operand")] 5468 "" 5469{ 5470 emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (32), operands[2])); 5471 DONE; 5472}) 5473 5474(define_expand "mskqh" 5475 [(match_operand:DI 0 "register_operand") 5476 (match_operand:DI 1 "register_operand") 5477 (match_operand:DI 2 "reg_or_8bit_operand")] 5478 "" 5479{ 5480 emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (64), operands[2])); 5481 DONE; 5482}) 5483 5484(define_expand "builtin_zap" 5485 [(set (match_operand:DI 0 "register_operand") 5486 (and:DI (unspec:DI 5487 [(match_operand:DI 2 "reg_or_cint_operand")] 5488 UNSPEC_ZAP) 5489 (match_operand:DI 1 "reg_or_cint_operand")))] 5490 "" 5491{ 5492 if (CONST_INT_P (operands[2])) 5493 { 5494 rtx mask = alpha_expand_zap_mask (INTVAL (operands[2])); 5495 5496 if (mask == const0_rtx) 5497 { 5498 emit_move_insn (operands[0], const0_rtx); 5499 DONE; 5500 } 5501 if (mask == constm1_rtx) 5502 { 5503 emit_move_insn (operands[0], operands[1]); 5504 DONE; 5505 } 5506 5507 operands[1] = force_reg (DImode, operands[1]); 5508 emit_insn (gen_anddi3 (operands[0], operands[1], mask)); 5509 DONE; 5510 } 5511 5512 operands[1] = force_reg (DImode, operands[1]); 5513 operands[2] = gen_lowpart (QImode, operands[2]); 5514}) 5515 5516(define_insn "*builtin_zap_1" 5517 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r") 5518 (and:DI (unspec:DI 5519 [(match_operand:QI 2 "reg_or_cint_operand" "n,n,r,r")] 5520 UNSPEC_ZAP) 5521 (match_operand:DI 1 "reg_or_cint_operand" "n,r,J,r")))] 5522 "" 5523 "@ 5524 # 5525 # 5526 bis $31,$31,%0 5527 zap %r1,%2,%0" 5528 [(set_attr "type" "shift,shift,ilog,shift")]) 5529 5530(define_split 5531 [(set (match_operand:DI 0 "register_operand") 5532 (and:DI (unspec:DI 5533 [(match_operand:QI 2 "const_int_operand")] 5534 UNSPEC_ZAP) 5535 (match_operand:DI 1 "const_int_operand")))] 5536 "" 5537 [(const_int 0)] 5538{ 5539 rtx mask = alpha_expand_zap_mask (INTVAL (operands[2])); 5540 5541 operands[1] = gen_int_mode (INTVAL (operands[1]) & INTVAL (mask), DImode); 5542 emit_move_insn (operands[0], operands[1]); 5543 DONE; 5544}) 5545 5546(define_split 5547 [(set (match_operand:DI 0 "register_operand") 5548 (and:DI (unspec:DI 5549 [(match_operand:QI 2 "const_int_operand")] 5550 UNSPEC_ZAP) 5551 (match_operand:DI 1 "register_operand")))] 5552 "" 5553 [(set (match_dup 0) 5554 (and:DI (match_dup 1) (match_dup 2)))] 5555{ 5556 operands[2] = alpha_expand_zap_mask (INTVAL (operands[2])); 5557 if (operands[2] == const0_rtx) 5558 { 5559 emit_move_insn (operands[0], const0_rtx); 5560 DONE; 5561 } 5562 if (operands[2] == constm1_rtx) 5563 { 5564 emit_move_insn (operands[0], operands[1]); 5565 DONE; 5566 } 5567}) 5568 5569(define_expand "builtin_zapnot" 5570 [(set (match_operand:DI 0 "register_operand") 5571 (and:DI (unspec:DI 5572 [(not:QI (match_operand:DI 2 "reg_or_cint_operand"))] 5573 UNSPEC_ZAP) 5574 (match_operand:DI 1 "reg_or_cint_operand")))] 5575 "" 5576{ 5577 if (CONST_INT_P (operands[2])) 5578 { 5579 rtx mask = alpha_expand_zap_mask (~ INTVAL (operands[2])); 5580 5581 if (mask == const0_rtx) 5582 { 5583 emit_move_insn (operands[0], const0_rtx); 5584 DONE; 5585 } 5586 if (mask == constm1_rtx) 5587 { 5588 emit_move_insn (operands[0], operands[1]); 5589 DONE; 5590 } 5591 5592 operands[1] = force_reg (DImode, operands[1]); 5593 emit_insn (gen_anddi3 (operands[0], operands[1], mask)); 5594 DONE; 5595 } 5596 5597 operands[1] = force_reg (DImode, operands[1]); 5598 operands[2] = gen_lowpart (QImode, operands[2]); 5599}) 5600 5601(define_insn "*builtin_zapnot_1" 5602 [(set (match_operand:DI 0 "register_operand" "=r") 5603 (and:DI (unspec:DI 5604 [(not:QI (match_operand:QI 2 "register_operand" "r"))] 5605 UNSPEC_ZAP) 5606 (match_operand:DI 1 "reg_or_0_operand" "rJ")))] 5607 "" 5608 "zapnot %r1,%2,%0" 5609 [(set_attr "type" "shift")]) 5610 5611(define_insn "builtin_amask" 5612 [(set (match_operand:DI 0 "register_operand" "=r") 5613 (unspec:DI [(match_operand:DI 1 "reg_or_8bit_operand" "rI")] 5614 UNSPEC_AMASK))] 5615 "" 5616 "amask %1,%0" 5617 [(set_attr "type" "ilog")]) 5618 5619(define_insn "builtin_implver" 5620 [(set (match_operand:DI 0 "register_operand" "=r") 5621 (unspec:DI [(const_int 0)] UNSPEC_IMPLVER))] 5622 "" 5623 "implver %0" 5624 [(set_attr "type" "ilog")]) 5625 5626(define_insn "builtin_rpcc" 5627 [(set (match_operand:DI 0 "register_operand" "=r") 5628 (unspec_volatile:DI [(const_int 0)] UNSPECV_RPCC))] 5629 "" 5630 "rpcc %0" 5631 [(set_attr "type" "ilog")]) 5632 5633(define_expand "builtin_minub8" 5634 [(match_operand:DI 0 "register_operand") 5635 (match_operand:DI 1 "reg_or_0_operand") 5636 (match_operand:DI 2 "reg_or_0_operand")] 5637 "TARGET_MAX" 5638{ 5639 alpha_expand_builtin_vector_binop (gen_uminv8qi3, V8QImode, operands[0], 5640 operands[1], operands[2]); 5641 DONE; 5642}) 5643 5644(define_expand "builtin_minsb8" 5645 [(match_operand:DI 0 "register_operand") 5646 (match_operand:DI 1 "reg_or_0_operand") 5647 (match_operand:DI 2 "reg_or_0_operand")] 5648 "TARGET_MAX" 5649{ 5650 alpha_expand_builtin_vector_binop (gen_sminv8qi3, V8QImode, operands[0], 5651 operands[1], operands[2]); 5652 DONE; 5653}) 5654 5655(define_expand "builtin_minuw4" 5656 [(match_operand:DI 0 "register_operand") 5657 (match_operand:DI 1 "reg_or_0_operand") 5658 (match_operand:DI 2 "reg_or_0_operand")] 5659 "TARGET_MAX" 5660{ 5661 alpha_expand_builtin_vector_binop (gen_uminv4hi3, V4HImode, operands[0], 5662 operands[1], operands[2]); 5663 DONE; 5664}) 5665 5666(define_expand "builtin_minsw4" 5667 [(match_operand:DI 0 "register_operand") 5668 (match_operand:DI 1 "reg_or_0_operand") 5669 (match_operand:DI 2 "reg_or_0_operand")] 5670 "TARGET_MAX" 5671{ 5672 alpha_expand_builtin_vector_binop (gen_sminv4hi3, V4HImode, operands[0], 5673 operands[1], operands[2]); 5674 DONE; 5675}) 5676 5677(define_expand "builtin_maxub8" 5678 [(match_operand:DI 0 "register_operand") 5679 (match_operand:DI 1 "reg_or_0_operand") 5680 (match_operand:DI 2 "reg_or_0_operand")] 5681 "TARGET_MAX" 5682{ 5683 alpha_expand_builtin_vector_binop (gen_umaxv8qi3, V8QImode, operands[0], 5684 operands[1], operands[2]); 5685 DONE; 5686}) 5687 5688(define_expand "builtin_maxsb8" 5689 [(match_operand:DI 0 "register_operand") 5690 (match_operand:DI 1 "reg_or_0_operand") 5691 (match_operand:DI 2 "reg_or_0_operand")] 5692 "TARGET_MAX" 5693{ 5694 alpha_expand_builtin_vector_binop (gen_smaxv8qi3, V8QImode, operands[0], 5695 operands[1], operands[2]); 5696 DONE; 5697}) 5698 5699(define_expand "builtin_maxuw4" 5700 [(match_operand:DI 0 "register_operand") 5701 (match_operand:DI 1 "reg_or_0_operand") 5702 (match_operand:DI 2 "reg_or_0_operand")] 5703 "TARGET_MAX" 5704{ 5705 alpha_expand_builtin_vector_binop (gen_umaxv4hi3, V4HImode, operands[0], 5706 operands[1], operands[2]); 5707 DONE; 5708}) 5709 5710(define_expand "builtin_maxsw4" 5711 [(match_operand:DI 0 "register_operand") 5712 (match_operand:DI 1 "reg_or_0_operand") 5713 (match_operand:DI 2 "reg_or_0_operand")] 5714 "TARGET_MAX" 5715{ 5716 alpha_expand_builtin_vector_binop (gen_smaxv4hi3, V4HImode, operands[0], 5717 operands[1], operands[2]); 5718 DONE; 5719}) 5720 5721(define_insn "builtin_perr" 5722 [(set (match_operand:DI 0 "register_operand" "=r") 5723 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "%rJ") 5724 (match_operand:DI 2 "reg_or_8bit_operand" "rJ")] 5725 UNSPEC_PERR))] 5726 "TARGET_MAX" 5727 "perr %r1,%r2,%0" 5728 [(set_attr "type" "mvi")]) 5729 5730(define_expand "builtin_pklb" 5731 [(set (match_operand:DI 0 "register_operand") 5732 (vec_concat:V8QI 5733 (vec_concat:V4QI 5734 (truncate:V2QI (match_operand:DI 1 "register_operand")) 5735 (match_dup 2)) 5736 (match_dup 3)))] 5737 "TARGET_MAX" 5738{ 5739 operands[0] = gen_lowpart (V8QImode, operands[0]); 5740 operands[1] = gen_lowpart (V2SImode, operands[1]); 5741 operands[2] = CONST0_RTX (V2QImode); 5742 operands[3] = CONST0_RTX (V4QImode); 5743}) 5744 5745(define_insn "*pklb" 5746 [(set (match_operand:V8QI 0 "register_operand" "=r") 5747 (vec_concat:V8QI 5748 (vec_concat:V4QI 5749 (truncate:V2QI (match_operand:V2SI 1 "register_operand" "r")) 5750 (match_operand:V2QI 2 "const0_operand")) 5751 (match_operand:V4QI 3 "const0_operand")))] 5752 "TARGET_MAX" 5753 "pklb %r1,%0" 5754 [(set_attr "type" "mvi")]) 5755 5756(define_expand "builtin_pkwb" 5757 [(set (match_operand:DI 0 "register_operand") 5758 (vec_concat:V8QI 5759 (truncate:V4QI (match_operand:DI 1 "register_operand")) 5760 (match_dup 2)))] 5761 "TARGET_MAX" 5762{ 5763 operands[0] = gen_lowpart (V8QImode, operands[0]); 5764 operands[1] = gen_lowpart (V4HImode, operands[1]); 5765 operands[2] = CONST0_RTX (V4QImode); 5766}) 5767 5768(define_insn "*pkwb" 5769 [(set (match_operand:V8QI 0 "register_operand" "=r") 5770 (vec_concat:V8QI 5771 (truncate:V4QI (match_operand:V4HI 1 "register_operand" "r")) 5772 (match_operand:V4QI 2 "const0_operand")))] 5773 "TARGET_MAX" 5774 "pkwb %r1,%0" 5775 [(set_attr "type" "mvi")]) 5776 5777(define_expand "builtin_unpkbl" 5778 [(set (match_operand:DI 0 "register_operand") 5779 (zero_extend:V2SI 5780 (vec_select:V2QI (match_operand:DI 1 "register_operand") 5781 (parallel [(const_int 0) (const_int 1)]))))] 5782 "TARGET_MAX" 5783{ 5784 operands[0] = gen_lowpart (V2SImode, operands[0]); 5785 operands[1] = gen_lowpart (V8QImode, operands[1]); 5786}) 5787 5788(define_insn "*unpkbl" 5789 [(set (match_operand:V2SI 0 "register_operand" "=r") 5790 (zero_extend:V2SI 5791 (vec_select:V2QI (match_operand:V8QI 1 "reg_or_0_operand" "rW") 5792 (parallel [(const_int 0) (const_int 1)]))))] 5793 "TARGET_MAX" 5794 "unpkbl %r1,%0" 5795 [(set_attr "type" "mvi")]) 5796 5797(define_expand "builtin_unpkbw" 5798 [(set (match_operand:DI 0 "register_operand") 5799 (zero_extend:V4HI 5800 (vec_select:V4QI (match_operand:DI 1 "register_operand") 5801 (parallel [(const_int 0) 5802 (const_int 1) 5803 (const_int 2) 5804 (const_int 3)]))))] 5805 "TARGET_MAX" 5806{ 5807 operands[0] = gen_lowpart (V4HImode, operands[0]); 5808 operands[1] = gen_lowpart (V8QImode, operands[1]); 5809}) 5810 5811(define_insn "*unpkbw" 5812 [(set (match_operand:V4HI 0 "register_operand" "=r") 5813 (zero_extend:V4HI 5814 (vec_select:V4QI (match_operand:V8QI 1 "reg_or_0_operand" "rW") 5815 (parallel [(const_int 0) 5816 (const_int 1) 5817 (const_int 2) 5818 (const_int 3)]))))] 5819 "TARGET_MAX" 5820 "unpkbw %r1,%0" 5821 [(set_attr "type" "mvi")]) 5822 5823(include "sync.md") 5824 5825;; The call patterns are at the end of the file because their 5826;; wildcard operand0 interferes with nice recognition. 5827 5828(define_insn "*call_value_osf_1_er_noreturn" 5829 [(set (match_operand 0) 5830 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s")) 5831 (match_operand 2))) 5832 (use (reg:DI 29)) 5833 (clobber (reg:DI 26))] 5834 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF 5835 && find_reg_note (insn, REG_NORETURN, NULL_RTX)" 5836 "@ 5837 jsr $26,($27),0 5838 bsr $26,%1\t\t!samegp 5839 ldq $27,%1($29)\t\t!literal!%#\;jsr $26,($27),%1\t\t!lituse_jsr!%#" 5840 [(set_attr "type" "jsr") 5841 (set_attr "length" "*,*,8")]) 5842 5843(define_insn "*call_value_osf_1_er" 5844 [(set (match_operand 0) 5845 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s")) 5846 (match_operand 2))) 5847 (use (reg:DI 29)) 5848 (clobber (reg:DI 26))] 5849 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 5850 "@ 5851 jsr $26,(%1),0\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%* 5852 bsr $26,%1\t\t!samegp 5853 ldq $27,%1($29)\t\t!literal!%#\;jsr $26,($27),0\t\t!lituse_jsr!%#\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*" 5854 [(set_attr "type" "jsr") 5855 (set_attr "length" "12,*,16")]) 5856 5857;; We must use peep2 instead of a split because we need accurate life 5858;; information for $gp. Consider the case of { bar(); while (1); }. 5859(define_peephole2 5860 [(parallel [(set (match_operand 0) 5861 (call (mem:DI (match_operand:DI 1 "call_operand")) 5862 (match_operand 2))) 5863 (use (reg:DI 29)) 5864 (clobber (reg:DI 26))])] 5865 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed 5866 && ! samegp_function_operand (operands[1], Pmode) 5867 && (peep2_regno_dead_p (1, 29) 5868 || find_reg_note (insn, REG_NORETURN, NULL_RTX))" 5869 [(parallel [(set (match_dup 0) 5870 (call (mem:DI (match_dup 3)) 5871 (match_dup 2))) 5872 (use (reg:DI 29)) 5873 (use (match_dup 1)) 5874 (use (match_dup 4)) 5875 (clobber (reg:DI 26))])] 5876{ 5877 if (CONSTANT_P (operands[1])) 5878 { 5879 operands[3] = gen_rtx_REG (Pmode, 27); 5880 operands[4] = GEN_INT (alpha_next_sequence_number++); 5881 emit_insn (gen_movdi_er_high_g (operands[3], pic_offset_table_rtx, 5882 operands[1], operands[4])); 5883 } 5884 else 5885 { 5886 operands[3] = operands[1]; 5887 operands[1] = const0_rtx; 5888 operands[4] = const0_rtx; 5889 } 5890}) 5891 5892(define_peephole2 5893 [(parallel [(set (match_operand 0) 5894 (call (mem:DI (match_operand:DI 1 "call_operand")) 5895 (match_operand 2))) 5896 (use (reg:DI 29)) 5897 (clobber (reg:DI 26))])] 5898 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed 5899 && ! samegp_function_operand (operands[1], Pmode) 5900 && ! (peep2_regno_dead_p (1, 29) 5901 || find_reg_note (insn, REG_NORETURN, NULL_RTX))" 5902 [(parallel [(set (match_dup 0) 5903 (call (mem:DI (match_dup 3)) 5904 (match_dup 2))) 5905 (set (match_dup 6) 5906 (unspec:DI [(match_dup 6) (match_dup 4)] UNSPEC_LDGP1)) 5907 (use (match_dup 1)) 5908 (use (match_dup 5)) 5909 (clobber (reg:DI 26))]) 5910 (set (match_dup 6) 5911 (unspec:DI [(match_dup 6) (match_dup 4)] UNSPEC_LDGP2))] 5912{ 5913 if (CONSTANT_P (operands[1])) 5914 { 5915 operands[3] = gen_rtx_REG (Pmode, 27); 5916 operands[5] = GEN_INT (alpha_next_sequence_number++); 5917 emit_insn (gen_movdi_er_high_g (operands[3], pic_offset_table_rtx, 5918 operands[1], operands[5])); 5919 } 5920 else 5921 { 5922 operands[3] = operands[1]; 5923 operands[1] = const0_rtx; 5924 operands[5] = const0_rtx; 5925 } 5926 operands[4] = GEN_INT (alpha_next_sequence_number++); 5927 operands[6] = pic_offset_table_rtx; 5928}) 5929 5930(define_insn "*call_value_osf_2_er_nogp" 5931 [(set (match_operand 0) 5932 (call (mem:DI (match_operand:DI 1 "register_operand" "c")) 5933 (match_operand 2))) 5934 (use (reg:DI 29)) 5935 (use (match_operand 3)) 5936 (use (match_operand 4)) 5937 (clobber (reg:DI 26))] 5938 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 5939 "jsr $26,(%1),%3%J4" 5940 [(set_attr "type" "jsr")]) 5941 5942(define_insn "*call_value_osf_2_er" 5943 [(set (match_operand 0) 5944 (call (mem:DI (match_operand:DI 1 "register_operand" "c")) 5945 (match_operand 2))) 5946 (set (reg:DI 29) 5947 (unspec:DI [(reg:DI 29) (match_operand 5 "const_int_operand")] 5948 UNSPEC_LDGP1)) 5949 (use (match_operand 3)) 5950 (use (match_operand 4)) 5951 (clobber (reg:DI 26))] 5952 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 5953 "jsr $26,(%1),%3%J4\;ldah $29,0($26)\t\t!gpdisp!%5" 5954 [(set_attr "type" "jsr") 5955 (set_attr "cannot_copy" "true") 5956 (set_attr "length" "8")]) 5957 5958(define_insn "*call_value_osf_1_noreturn" 5959 [(set (match_operand 0) 5960 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s")) 5961 (match_operand 2))) 5962 (use (reg:DI 29)) 5963 (clobber (reg:DI 26))] 5964 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF 5965 && find_reg_note (insn, REG_NORETURN, NULL_RTX)" 5966 "@ 5967 jsr $26,($27),0 5968 bsr $26,$%1..ng 5969 jsr $26,%1" 5970 [(set_attr "type" "jsr") 5971 (set_attr "length" "*,*,8")]) 5972 5973(define_int_iterator TLS_CALL 5974 [UNSPEC_TLSGD_CALL 5975 UNSPEC_TLSLDM_CALL]) 5976 5977(define_int_attr tls 5978 [(UNSPEC_TLSGD_CALL "tlsgd") 5979 (UNSPEC_TLSLDM_CALL "tlsldm")]) 5980 5981(define_insn "call_value_osf_<tls>" 5982 [(set (match_operand 0) 5983 (call (mem:DI (match_operand:DI 1 "symbolic_operand")) 5984 (const_int 0))) 5985 (unspec [(match_operand:DI 2 "const_int_operand")] TLS_CALL) 5986 (use (reg:DI 29)) 5987 (clobber (reg:DI 26))] 5988 "HAVE_AS_TLS" 5989 "ldq $27,%1($29)\t\t!literal!%2\;jsr $26,($27),%1\t\t!lituse_<tls>!%2\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*" 5990 [(set_attr "type" "jsr") 5991 (set_attr "length" "16")]) 5992 5993;; We must use peep2 instead of a split because we need accurate life 5994;; information for $gp. 5995(define_peephole2 5996 [(parallel 5997 [(set (match_operand 0) 5998 (call (mem:DI (match_operand:DI 1 "symbolic_operand")) 5999 (const_int 0))) 6000 (unspec [(match_operand:DI 2 "const_int_operand")] TLS_CALL) 6001 (use (reg:DI 29)) 6002 (clobber (reg:DI 26))])] 6003 "HAVE_AS_TLS && reload_completed 6004 && peep2_regno_dead_p (1, 29)" 6005 [(set (match_dup 3) 6006 (unspec:DI [(match_dup 5) 6007 (match_dup 1) 6008 (match_dup 2)] UNSPEC_LITERAL)) 6009 (parallel [(set (match_dup 0) 6010 (call (mem:DI (match_dup 3)) 6011 (const_int 0))) 6012 (use (match_dup 5)) 6013 (use (match_dup 1)) 6014 (use (unspec [(match_dup 2)] TLS_CALL)) 6015 (clobber (reg:DI 26))]) 6016 (set (match_dup 5) 6017 (unspec:DI [(match_dup 5) (match_dup 4)] UNSPEC_LDGP2))] 6018{ 6019 operands[3] = gen_rtx_REG (Pmode, 27); 6020 operands[4] = GEN_INT (alpha_next_sequence_number++); 6021 operands[5] = pic_offset_table_rtx; 6022}) 6023 6024(define_peephole2 6025 [(parallel 6026 [(set (match_operand 0) 6027 (call (mem:DI (match_operand:DI 1 "symbolic_operand")) 6028 (const_int 0))) 6029 (unspec [(match_operand:DI 2 "const_int_operand")] TLS_CALL) 6030 (use (reg:DI 29)) 6031 (clobber (reg:DI 26))])] 6032 "HAVE_AS_TLS && reload_completed 6033 && !peep2_regno_dead_p (1, 29)" 6034 [(set (match_dup 3) 6035 (unspec:DI [(match_dup 5) 6036 (match_dup 1) 6037 (match_dup 2)] UNSPEC_LITERAL)) 6038 (parallel [(set (match_dup 0) 6039 (call (mem:DI (match_dup 3)) 6040 (const_int 0))) 6041 (set (match_dup 5) 6042 (unspec:DI [(match_dup 5) (match_dup 4)] UNSPEC_LDGP1)) 6043 (use (match_dup 1)) 6044 (use (unspec [(match_dup 2)] TLS_CALL)) 6045 (clobber (reg:DI 26))]) 6046 (set (match_dup 5) 6047 (unspec:DI [(match_dup 5) (match_dup 4)] UNSPEC_LDGP2))] 6048{ 6049 operands[3] = gen_rtx_REG (Pmode, 27); 6050 operands[4] = GEN_INT (alpha_next_sequence_number++); 6051 operands[5] = pic_offset_table_rtx; 6052}) 6053 6054(define_insn "*call_value_osf_1" 6055 [(set (match_operand 0) 6056 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s")) 6057 (match_operand 2))) 6058 (use (reg:DI 29)) 6059 (clobber (reg:DI 26))] 6060 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 6061 "@ 6062 jsr $26,($27),0\;ldgp $29,0($26) 6063 bsr $26,$%1..ng 6064 jsr $26,%1\;ldgp $29,0($26)" 6065 [(set_attr "type" "jsr") 6066 (set_attr "length" "12,*,16")]) 6067 6068(define_insn "*sibcall_value_osf_1_er" 6069 [(set (match_operand 0) 6070 (call (mem:DI (match_operand:DI 1 "symbolic_operand" "R,s")) 6071 (match_operand 2))) 6072 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)] 6073 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 6074 "@ 6075 br $31,%1\t\t!samegp 6076 ldq $27,%1($29)\t\t!literal!%#\;jmp $31,($27),%1\t\t!lituse_jsr!%#" 6077 [(set_attr "type" "jsr") 6078 (set_attr "length" "*,8")]) 6079 6080(define_insn "*sibcall_value_osf_1" 6081 [(set (match_operand 0) 6082 (call (mem:DI (match_operand:DI 1 "symbolic_operand" "R,s")) 6083 (match_operand 2))) 6084 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)] 6085 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 6086 "@ 6087 br $31,$%1..ng 6088 lda $27,%1\;jmp $31,($27),%1" 6089 [(set_attr "type" "jsr") 6090 (set_attr "length" "*,8")]) 6091 6092; GAS relies on the order and position of instructions output below in order 6093; to generate relocs for VMS link to potentially optimize the call. 6094; Please do not molest. 6095(define_insn "*call_value_vms_1" 6096 [(set (match_operand 0) 6097 (call (mem:DI (match_operand:DI 1 "call_operand" "r,s")) 6098 (match_operand 2))) 6099 (use (match_operand:DI 3 "nonmemory_operand" "r,n")) 6100 (use (reg:DI 25)) 6101 (use (reg:DI 26)) 6102 (clobber (reg:DI 27))] 6103 "TARGET_ABI_OPEN_VMS" 6104{ 6105 switch (which_alternative) 6106 { 6107 case 0: 6108 return "mov %3,$27\;jsr $26,0\;ldq $27,0($29)"; 6109 case 1: 6110 operands [3] = alpha_use_linkage (operands [1], true, false); 6111 operands [4] = alpha_use_linkage (operands [1], false, false); 6112 return "ldq $26,%4\;ldq $27,%3\;jsr $26,%1\;ldq $27,0($29)"; 6113 default: 6114 gcc_unreachable (); 6115 } 6116} 6117 [(set_attr "type" "jsr") 6118 (set_attr "length" "12,16")]) 6119