1 /* ---------------------------------------------------------------------------- 2 * SAM Software Package License 3 * ---------------------------------------------------------------------------- 4 * Copyright (c) 2012, Atmel Corporation 5 * 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following condition is met: 10 * 11 * - Redistributions of source code must retain the above copyright notice, 12 * this list of conditions and the disclaimer below. 13 * 14 * Atmel's name may not be used to endorse or promote products derived from 15 * this software without specific prior written permission. 16 * 17 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE 20 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, 23 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 24 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 25 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 26 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * ---------------------------------------------------------------------------- 28 */ 29 30 #ifndef _SAM3XA_WDT_COMPONENT_ 31 #define _SAM3XA_WDT_COMPONENT_ 32 33 /* ============================================================================= */ 34 /** SOFTWARE API DEFINITION FOR Watchdog Timer */ 35 /* ============================================================================= */ 36 /** \addtogroup SAM3XA_WDT Watchdog Timer */ 37 /*@{*/ 38 39 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 40 /** \brief Wdt hardware registers */ 41 typedef struct { 42 WoReg WDT_CR; /**< \brief (Wdt Offset: 0x00) Control Register */ 43 RwReg WDT_MR; /**< \brief (Wdt Offset: 0x04) Mode Register */ 44 RoReg WDT_SR; /**< \brief (Wdt Offset: 0x08) Status Register */ 45 } Wdt; 46 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 47 /* -------- WDT_CR : (WDT Offset: 0x00) Control Register -------- */ 48 #define WDT_CR_WDRSTT (0x1u << 0) /**< \brief (WDT_CR) Watchdog Restart */ 49 #define WDT_CR_KEY_Pos 24 50 #define WDT_CR_KEY_Msk (0xffu << WDT_CR_KEY_Pos) /**< \brief (WDT_CR) Password */ 51 #define WDT_CR_KEY(value) ((WDT_CR_KEY_Msk & ((value) << WDT_CR_KEY_Pos))) 52 /* -------- WDT_MR : (WDT Offset: 0x04) Mode Register -------- */ 53 #define WDT_MR_WDV_Pos 0 54 #define WDT_MR_WDV_Msk (0xfffu << WDT_MR_WDV_Pos) /**< \brief (WDT_MR) Watchdog Counter Value */ 55 #define WDT_MR_WDV(value) ((WDT_MR_WDV_Msk & ((value) << WDT_MR_WDV_Pos))) 56 #define WDT_MR_WDFIEN (0x1u << 12) /**< \brief (WDT_MR) Watchdog Fault Interrupt Enable */ 57 #define WDT_MR_WDRSTEN (0x1u << 13) /**< \brief (WDT_MR) Watchdog Reset Enable */ 58 #define WDT_MR_WDRPROC (0x1u << 14) /**< \brief (WDT_MR) Watchdog Reset Processor */ 59 #define WDT_MR_WDDIS (0x1u << 15) /**< \brief (WDT_MR) Watchdog Disable */ 60 #define WDT_MR_WDD_Pos 16 61 #define WDT_MR_WDD_Msk (0xfffu << WDT_MR_WDD_Pos) /**< \brief (WDT_MR) Watchdog Delta Value */ 62 #define WDT_MR_WDD(value) ((WDT_MR_WDD_Msk & ((value) << WDT_MR_WDD_Pos))) 63 #define WDT_MR_WDDBGHLT (0x1u << 28) /**< \brief (WDT_MR) Watchdog Debug Halt */ 64 #define WDT_MR_WDIDLEHLT (0x1u << 29) /**< \brief (WDT_MR) Watchdog Idle Halt */ 65 /* -------- WDT_SR : (WDT Offset: 0x08) Status Register -------- */ 66 #define WDT_SR_WDUNF (0x1u << 0) /**< \brief (WDT_SR) Watchdog Underflow */ 67 #define WDT_SR_WDERR (0x1u << 1) /**< \brief (WDT_SR) Watchdog Error */ 68 69 /*@}*/ 70 71 72 #endif /* _SAM3XA_WDT_COMPONENT_ */ 73