1 /* ---------------------------------------------------------------------------- 2 * SAM Software Package License 3 * ---------------------------------------------------------------------------- 4 * Copyright (c) 2012, Atmel Corporation 5 * 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following condition is met: 10 * 11 * - Redistributions of source code must retain the above copyright notice, 12 * this list of conditions and the disclaimer below. 13 * 14 * Atmel's name may not be used to endorse or promote products derived from 15 * this software without specific prior written permission. 16 * 17 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE 20 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, 23 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 24 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 25 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 26 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * ---------------------------------------------------------------------------- 28 */ 29 30 #ifndef _SAM4S_PDC_COMPONENT_ 31 #define _SAM4S_PDC_COMPONENT_ 32 33 /* ============================================================================= */ 34 /** SOFTWARE API DEFINITION FOR Peripheral DMA Controller */ 35 /* ============================================================================= */ 36 /** \addtogroup SAM4S_PDC Peripheral DMA Controller */ 37 /*@{*/ 38 39 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 40 /** \brief Pdc hardware registers */ 41 typedef struct { 42 RwReg PERIPH_RPR; /**< \brief (Pdc Offset: 0x0) Receive Pointer Register */ 43 RwReg PERIPH_RCR; /**< \brief (Pdc Offset: 0x4) Receive Counter Register */ 44 RwReg PERIPH_TPR; /**< \brief (Pdc Offset: 0x8) Transmit Pointer Register */ 45 RwReg PERIPH_TCR; /**< \brief (Pdc Offset: 0xC) Transmit Counter Register */ 46 RwReg PERIPH_RNPR; /**< \brief (Pdc Offset: 0x10) Receive Next Pointer Register */ 47 RwReg PERIPH_RNCR; /**< \brief (Pdc Offset: 0x14) Receive Next Counter Register */ 48 RwReg PERIPH_TNPR; /**< \brief (Pdc Offset: 0x18) Transmit Next Pointer Register */ 49 RwReg PERIPH_TNCR; /**< \brief (Pdc Offset: 0x1C) Transmit Next Counter Register */ 50 WoReg PERIPH_PTCR; /**< \brief (Pdc Offset: 0x20) Transfer Control Register */ 51 RoReg PERIPH_PTSR; /**< \brief (Pdc Offset: 0x24) Transfer Status Register */ 52 } Pdc; 53 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 54 /* -------- PERIPH_RPR : (PDC Offset: 0x0) Receive Pointer Register -------- */ 55 #define PERIPH_RPR_RXPTR_Pos 0 56 #define PERIPH_RPR_RXPTR_Msk (0xffffffffu << PERIPH_RPR_RXPTR_Pos) /**< \brief (PERIPH_RPR) Receive Pointer Register */ 57 #define PERIPH_RPR_RXPTR(value) ((PERIPH_RPR_RXPTR_Msk & ((value) << PERIPH_RPR_RXPTR_Pos))) 58 /* -------- PERIPH_RCR : (PDC Offset: 0x4) Receive Counter Register -------- */ 59 #define PERIPH_RCR_RXCTR_Pos 0 60 #define PERIPH_RCR_RXCTR_Msk (0xffffu << PERIPH_RCR_RXCTR_Pos) /**< \brief (PERIPH_RCR) Receive Counter Register */ 61 #define PERIPH_RCR_RXCTR(value) ((PERIPH_RCR_RXCTR_Msk & ((value) << PERIPH_RCR_RXCTR_Pos))) 62 /* -------- PERIPH_TPR : (PDC Offset: 0x8) Transmit Pointer Register -------- */ 63 #define PERIPH_TPR_TXPTR_Pos 0 64 #define PERIPH_TPR_TXPTR_Msk (0xffffffffu << PERIPH_TPR_TXPTR_Pos) /**< \brief (PERIPH_TPR) Transmit Counter Register */ 65 #define PERIPH_TPR_TXPTR(value) ((PERIPH_TPR_TXPTR_Msk & ((value) << PERIPH_TPR_TXPTR_Pos))) 66 /* -------- PERIPH_TCR : (PDC Offset: 0xC) Transmit Counter Register -------- */ 67 #define PERIPH_TCR_TXCTR_Pos 0 68 #define PERIPH_TCR_TXCTR_Msk (0xffffu << PERIPH_TCR_TXCTR_Pos) /**< \brief (PERIPH_TCR) Transmit Counter Register */ 69 #define PERIPH_TCR_TXCTR(value) ((PERIPH_TCR_TXCTR_Msk & ((value) << PERIPH_TCR_TXCTR_Pos))) 70 /* -------- PERIPH_RNPR : (PDC Offset: 0x10) Receive Next Pointer Register -------- */ 71 #define PERIPH_RNPR_RXNPTR_Pos 0 72 #define PERIPH_RNPR_RXNPTR_Msk (0xffffffffu << PERIPH_RNPR_RXNPTR_Pos) /**< \brief (PERIPH_RNPR) Receive Next Pointer */ 73 #define PERIPH_RNPR_RXNPTR(value) ((PERIPH_RNPR_RXNPTR_Msk & ((value) << PERIPH_RNPR_RXNPTR_Pos))) 74 /* -------- PERIPH_RNCR : (PDC Offset: 0x14) Receive Next Counter Register -------- */ 75 #define PERIPH_RNCR_RXNCTR_Pos 0 76 #define PERIPH_RNCR_RXNCTR_Msk (0xffffu << PERIPH_RNCR_RXNCTR_Pos) /**< \brief (PERIPH_RNCR) Receive Next Counter */ 77 #define PERIPH_RNCR_RXNCTR(value) ((PERIPH_RNCR_RXNCTR_Msk & ((value) << PERIPH_RNCR_RXNCTR_Pos))) 78 /* -------- PERIPH_TNPR : (PDC Offset: 0x18) Transmit Next Pointer Register -------- */ 79 #define PERIPH_TNPR_TXNPTR_Pos 0 80 #define PERIPH_TNPR_TXNPTR_Msk (0xffffffffu << PERIPH_TNPR_TXNPTR_Pos) /**< \brief (PERIPH_TNPR) Transmit Next Pointer */ 81 #define PERIPH_TNPR_TXNPTR(value) ((PERIPH_TNPR_TXNPTR_Msk & ((value) << PERIPH_TNPR_TXNPTR_Pos))) 82 /* -------- PERIPH_TNCR : (PDC Offset: 0x1C) Transmit Next Counter Register -------- */ 83 #define PERIPH_TNCR_TXNCTR_Pos 0 84 #define PERIPH_TNCR_TXNCTR_Msk (0xffffu << PERIPH_TNCR_TXNCTR_Pos) /**< \brief (PERIPH_TNCR) Transmit Counter Next */ 85 #define PERIPH_TNCR_TXNCTR(value) ((PERIPH_TNCR_TXNCTR_Msk & ((value) << PERIPH_TNCR_TXNCTR_Pos))) 86 /* -------- PERIPH_PTCR : (PDC Offset: 0x20) Transfer Control Register -------- */ 87 #define PERIPH_PTCR_RXTEN (0x1u << 0) /**< \brief (PERIPH_PTCR) Receiver Transfer Enable */ 88 #define PERIPH_PTCR_RXTDIS (0x1u << 1) /**< \brief (PERIPH_PTCR) Receiver Transfer Disable */ 89 #define PERIPH_PTCR_TXTEN (0x1u << 8) /**< \brief (PERIPH_PTCR) Transmitter Transfer Enable */ 90 #define PERIPH_PTCR_TXTDIS (0x1u << 9) /**< \brief (PERIPH_PTCR) Transmitter Transfer Disable */ 91 /* -------- PERIPH_PTSR : (PDC Offset: 0x24) Transfer Status Register -------- */ 92 #define PERIPH_PTSR_RXTEN (0x1u << 0) /**< \brief (PERIPH_PTSR) Receiver Transfer Enable */ 93 #define PERIPH_PTSR_TXTEN (0x1u << 8) /**< \brief (PERIPH_PTSR) Transmitter Transfer Enable */ 94 95 /*@}*/ 96 97 98 #endif /* _SAM4S_PDC_COMPONENT_ */ 99