1 /* Opcode table header for m680[01234]0/m6888[12]/m68851. 2 Copyright (C) 1989-2021 Free Software Foundation, Inc. 3 4 This file is part of GDB, GAS, and the GNU binutils. 5 6 GDB, GAS, and the GNU binutils are free software; you can redistribute 7 them and/or modify them under the terms of the GNU General Public 8 License as published by the Free Software Foundation; either version 3, 9 or (at your option) any later version. 10 11 GDB, GAS, and the GNU binutils are distributed in the hope that they 12 will be useful, but WITHOUT ANY WARRANTY; without even the implied 13 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See 14 the GNU General Public License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with this file; see the file COPYING3. If not, write to the Free 18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 19 02110-1301, USA. */ 20 21 /* These are used as bit flags for the arch field in the m68k_opcode 22 structure. */ 23 #define _m68k_undef 0 24 #define m68000 0x001 25 #define m68010 0x002 26 #define m68020 0x004 27 #define m68030 0x008 28 #define m68040 0x010 29 #define m68060 0x020 30 #define m68881 0x040 31 #define m68851 0x080 32 #define cpu32 0x100 /* e.g., 68332 */ 33 #define fido_a 0x200 34 #define m68k_mask 0x3ff 35 36 #define mcfmac 0x400 /* ColdFire MAC. */ 37 #define mcfemac 0x800 /* ColdFire EMAC. */ 38 #define cfloat 0x1000 /* ColdFire FPU. */ 39 #define mcfhwdiv 0x2000 /* ColdFire hardware divide. */ 40 41 #define mcfisa_a 0x4000 /* ColdFire ISA_A. */ 42 #define mcfisa_aa 0x8000 /* ColdFire ISA_A+. */ 43 #define mcfisa_b 0x10000 /* ColdFire ISA_B. */ 44 #define mcfisa_c 0x20000 /* ColdFire ISA_C. */ 45 #define mcfusp 0x40000 /* ColdFire USP instructions. */ 46 #define mcf_mask 0x7e400 47 48 /* Handy aliases. */ 49 #define m68040up (m68040 | m68060) 50 #define m68030up (m68030 | m68040up) 51 #define m68020up (m68020 | m68030up) 52 #define m68010up (m68010 | cpu32 | fido_a | m68020up) 53 #define m68000up (m68000 | m68010up) 54 55 #define mfloat (m68881 | m68040 | m68060) 56 #define mmmu (m68851 | m68030 | m68040 | m68060) 57 58 /* The structure used to hold information for an opcode. */ 59 60 struct m68k_opcode 61 { 62 /* The opcode name. */ 63 const char *name; 64 /* The pseudo-size of the instruction(in bytes). Used to determine 65 number of bytes necessary to disassemble the instruction. */ 66 unsigned int size; 67 /* The opcode itself. */ 68 unsigned long opcode; 69 /* The mask used by the disassembler. */ 70 unsigned long match; 71 /* The arguments. */ 72 const char *args; 73 /* The architectures which support this opcode. */ 74 unsigned int arch; 75 }; 76 77 /* The structure used to hold information for an opcode alias. */ 78 79 struct m68k_opcode_alias 80 { 81 /* The alias name. */ 82 const char *alias; 83 /* The instruction for which this is an alias. */ 84 const char *primary; 85 }; 86 87 /* We store four bytes of opcode for all opcodes because that is the 88 most any of them need. The actual length of an instruction is 89 always at least 2 bytes, and is as much longer as necessary to hold 90 the operands it has. 91 92 The match field is a mask saying which bits must match particular 93 opcode in order for an instruction to be an instance of that 94 opcode. 95 96 The args field is a string containing two characters for each 97 operand of the instruction. The first specifies the kind of 98 operand; the second, the place it is stored. 99 100 If the first char of args is '.', it indicates that the opcode is 101 two words. This is only necessary when the match field does not 102 have any bits set in the second opcode word. Such a '.' is skipped 103 for operand processing. */ 104 105 /* Kinds of operands: 106 Characters used: AaBbCcDdEeFfGgHIiJjKkLlMmnOopQqRrSsTtUuVvWwXxYyZz01234|*~%;@!&$?/<>#^+- 107 108 D data register only. Stored as 3 bits. 109 A address register only. Stored as 3 bits. 110 a address register indirect only. Stored as 3 bits. 111 R either kind of register. Stored as 4 bits. 112 r either kind of register indirect only. Stored as 4 bits. 113 At the moment, used only for cas2 instruction. 114 F floating point coprocessor register only. Stored as 3 bits. 115 O an offset (or width): immediate data 0-31 or data register. 116 Stored as 6 bits in special format for BF... insns. 117 + autoincrement only. Stored as 3 bits (number of the address register). 118 - autodecrement only. Stored as 3 bits (number of the address register). 119 Q quick immediate data. Stored as 3 bits. 120 This matches an immediate operand only when value is in range 1 .. 8. 121 M moveq immediate data. Stored as 8 bits. 122 This matches an immediate operand only when value is in range -128..127 123 T trap vector immediate data. Stored as 4 bits. 124 125 k K-factor for fmove.p instruction. Stored as a 7-bit constant or 126 a three bit register offset, depending on the field type. 127 128 # immediate data. Stored in special places (b, w or l) 129 which say how many bits to store. 130 ^ immediate data for floating point instructions. Special places 131 are offset by 2 bytes from '#'... 132 B pc-relative address, converted to an offset 133 that is treated as immediate data. 134 d displacement and register. Stores the register as 3 bits 135 and stores the displacement in the entire second word. 136 137 C the CCR. No need to store it; this is just for filtering validity. 138 S the SR. No need to store, just as with CCR. 139 U the USP. No need to store, just as with CCR. 140 E the MAC ACC. No need to store, just as with CCR. 141 e the EMAC ACC[0123]. 142 G the MAC/EMAC MACSR. No need to store, just as with CCR. 143 g the EMAC ACCEXT{01,23}. 144 H the MASK. No need to store, just as with CCR. 145 i the MAC/EMAC scale factor. 146 147 I Coprocessor ID. Not printed if 1. The Coprocessor ID is always 148 extracted from the 'd' field of word one, which means that an extended 149 coprocessor opcode can be skipped using the 'i' place, if needed. 150 151 s System Control register for the floating point coprocessor. 152 153 J Misc register for movec instruction, stored in 'j' format. 154 Possible values: 155 0x000 SFC Source Function Code reg [60, 40, 30, 20, 10] 156 0x001 DFC Data Function Code reg [60, 40, 30, 20, 10] 157 0x002 CACR Cache Control Register [60, 40, 30, 20, mcf] 158 0x003 TC MMU Translation Control [60, 40] 159 0x004 ITT0 Instruction Transparent 160 Translation reg 0 [60, 40] 161 0x005 ITT1 Instruction Transparent 162 Translation reg 1 [60, 40] 163 0x006 DTT0 Data Transparent 164 Translation reg 0 [60, 40] 165 0x007 DTT1 Data Transparent 166 Translation reg 1 [60, 40] 167 0x008 BUSCR Bus Control Register [60] 168 0x800 USP User Stack Pointer [60, 40, 30, 20, 10] 169 0x801 VBR Vector Base reg [60, 40, 30, 20, 10, mcf] 170 0x802 CAAR Cache Address Register [ 30, 20] 171 0x803 MSP Master Stack Pointer [ 40, 30, 20] 172 0x804 ISP Interrupt Stack Pointer [ 40, 30, 20] 173 0x805 MMUSR MMU Status reg [ 40] 174 0x806 URP User Root Pointer [60, 40] 175 0x807 SRP Supervisor Root Pointer [60, 40] 176 0x808 PCR Processor Configuration reg [60] 177 0xC00 ROMBAR ROM Base Address Register [520X] 178 0xC04 RAMBAR0 RAM Base Address Register 0 [520X] 179 0xC05 RAMBAR1 RAM Base Address Register 0 [520X] 180 0xC0F MBAR0 RAM Base Address Register 0 [520X] 181 0xC04 FLASHBAR FLASH Base Address Register [mcf528x] 182 0xC05 RAMBAR Static RAM Base Address Register [mcf528x] 183 184 L Register list of the type d0-d7/a0-a7 etc. 185 (New! Improved! Can also hold fp0-fp7, as well!) 186 The assembler tries to see if the registers match the insn by 187 looking at where the insn wants them stored. 188 189 l Register list like L, but with all the bits reversed. 190 Used for going the other way. . . 191 192 c cache identifier which may be "nc" for no cache, "ic" 193 for instruction cache, "dc" for data cache, or "bc" 194 for both caches. Used in cinv and cpush. Always 195 stored in position "d". 196 197 u Any register, with ``upper'' or ``lower'' specification. Used 198 in the mac instructions with size word. 199 200 The remainder are all stored as 6 bits using an address mode and a 201 register number; they differ in which addressing modes they match. 202 203 * all (modes 0-6,7.0-4) 204 ~ alterable memory (modes 2-6,7.0,7.1) 205 (not 0,1,7.2-4) 206 % alterable (modes 0-6,7.0,7.1) 207 (not 7.2-4) 208 ; data (modes 0,2-6,7.0-4) 209 (not 1) 210 @ data, but not immediate (modes 0,2-6,7.0-3) 211 (not 1,7.4) 212 ! control (modes 2,5,6,7.0-3) 213 (not 0,1,3,4,7.4) 214 & alterable control (modes 2,5,6,7.0,7.1) 215 (not 0,1,3,4,7.2-4) 216 $ alterable data (modes 0,2-6,7.0,7.1) 217 (not 1,7.2-4) 218 ? alterable control, or data register (modes 0,2,5,6,7.0,7.1) 219 (not 1,3,4,7.2-4) 220 / control, or data register (modes 0,2,5,6,7.0-3) 221 (not 1,3,4,7.4) 222 > *save operands (modes 2,4,5,6,7.0,7.1) 223 (not 0,1,3,7.2-4) 224 < *restore operands (modes 2,3,5,6,7.0-3) 225 (not 0,1,4,7.4) 226 227 coldfire move operands: 228 m (modes 0-4) 229 n (modes 5,7.2) 230 o (modes 6,7.0,7.1,7.3,7.4) 231 p (modes 0-5) 232 233 coldfire bset/bclr/btst/mulsl/mulul operands: 234 q (modes 0,2-5) 235 v (modes 0,2-5,7.0,7.1) 236 b (modes 0,2-5,7.2) 237 w (modes 2-5,7.2) 238 y (modes 2,5) 239 z (modes 2,5,7.2) 240 x mov3q immediate operand. 241 j coprocessor ET operand. 242 K coprocessor command number. 243 4 (modes 2,3,4,5) 244 */ 245 246 /* For the 68851: */ 247 /* I didn't use much imagination in choosing the 248 following codes, so many of them aren't very 249 mnemonic. -rab 250 251 0 32 bit pmmu register 252 Possible values: 253 000 TC Translation Control Register (68030, 68851) 254 255 1 16 bit pmmu register 256 111 AC Access Control (68851) 257 258 2 8 bit pmmu register 259 100 CAL Current Access Level (68851) 260 101 VAL Validate Access Level (68851) 261 110 SCC Stack Change Control (68851) 262 263 3 68030-only pmmu registers (32 bit) 264 010 TT0 Transparent Translation reg 0 265 (aka Access Control reg 0 -- AC0 -- on 68ec030) 266 011 TT1 Transparent Translation reg 1 267 (aka Access Control reg 1 -- AC1 -- on 68ec030) 268 269 W wide pmmu registers 270 Possible values: 271 001 DRP Dma Root Pointer (68851) 272 010 SRP Supervisor Root Pointer (68030, 68851) 273 011 CRP Cpu Root Pointer (68030, 68851) 274 275 f function code register (68030, 68851) 276 0 SFC 277 1 DFC 278 279 V VAL register only (68851) 280 281 X BADx, BACx (16 bit) 282 100 BAD Breakpoint Acknowledge Data (68851) 283 101 BAC Breakpoint Acknowledge Control (68851) 284 285 Y PSR (68851) (MMUSR on 68030) (ACUSR on 68ec030) 286 Z PCSR (68851) 287 288 | memory (modes 2-6, 7.*) 289 290 t address test level (68030 only) 291 Stored as 3 bits, range 0-7. 292 Also used for breakpoint instruction now. 293 294 */ 295 296 /* Places to put an operand, for non-general operands: 297 Characters used: BbCcDdFfGgHhIijkLlMmNnostWw123456789/ 298 299 s source, low bits of first word. 300 d dest, shifted 9 in first word 301 1 second word, shifted 12 302 2 second word, shifted 6 303 3 second word, shifted 0 304 4 third word, shifted 12 305 5 third word, shifted 6 306 6 third word, shifted 0 307 7 second word, shifted 7 308 8 second word, shifted 10 309 9 second word, shifted 5 310 E second word, shifted 9 311 D store in both place 1 and place 3; for divul and divsl. 312 B first word, low byte, for branch displacements 313 W second word (entire), for branch displacements 314 L second and third words (entire), for branch displacements 315 (also overloaded for move16) 316 b second word, low byte 317 w second word (entire) [variable word/long branch offset for dbra] 318 W second word (entire) (must be signed 16 bit value) 319 l second and third word (entire) 320 g variable branch offset for bra and similar instructions. 321 The place to store depends on the magnitude of offset. 322 t store in both place 7 and place 8; for floating point operations 323 c branch offset for cpBcc operations. 324 The place to store is word two if bit six of word one is zero, 325 and words two and three if bit six of word one is one. 326 i Increment by two, to skip over coprocessor extended operands. Only 327 works with the 'I' format. 328 k Dynamic K-factor field. Bits 6-4 of word 2, used as a register number. 329 Also used for dynamic fmovem instruction. 330 C floating point coprocessor constant - 7 bits. Also used for static 331 K-factors... 332 j Movec register #, stored in 12 low bits of second word. 333 m For M[S]ACx; 4 bits split with MSB shifted 6 bits in first word 334 and remaining 3 bits of register shifted 9 bits in first word. 335 Indicate upper/lower in 1 bit shifted 7 bits in second word. 336 Use with `R' or `u' format. 337 n `m' withouth upper/lower indication. (For M[S]ACx; 4 bits split 338 with MSB shifted 6 bits in first word and remaining 3 bits of 339 register shifted 9 bits in first word. No upper/lower 340 indication is done.) Use with `R' or `u' format. 341 o For M[S]ACw; 4 bits shifted 12 in second word (like `1'). 342 Indicate upper/lower in 1 bit shifted 7 bits in second word. 343 Use with `R' or `u' format. 344 M For M[S]ACw; 4 bits in low bits of first word. Indicate 345 upper/lower in 1 bit shifted 6 bits in second word. Use with 346 `R' or `u' format. 347 N For M[S]ACw; 4 bits in low bits of second word. Indicate 348 upper/lower in 1 bit shifted 6 bits in second word. Use with 349 `R' or `u' format. 350 h shift indicator (scale factor), 1 bit shifted 10 in second word 351 352 Places to put operand, for general operands: 353 d destination, shifted 6 bits in first word 354 b source, at low bit of first word, and immediate uses one byte 355 w source, at low bit of first word, and immediate uses two bytes 356 l source, at low bit of first word, and immediate uses four bytes 357 s source, at low bit of first word. 358 Used sometimes in contexts where immediate is not allowed anyway. 359 f single precision float, low bit of 1st word, immediate uses 4 bytes 360 F double precision float, low bit of 1st word, immediate uses 8 bytes 361 x extended precision float, low bit of 1st word, immediate uses 12 bytes 362 p packed float, low bit of 1st word, immediate uses 12 bytes 363 G EMAC accumulator, load (bit 4 2nd word, !bit8 first word) 364 H EMAC accumulator, non load (bit 4 2nd word, bit 8 first word) 365 F EMAC ACCx 366 f EMAC ACCy 367 I MAC/EMAC scale factor 368 / Like 's', but set 2nd word, bit 5 if trailing_ampersand set 369 ] first word, bit 10 370 */ 371 372 extern const struct m68k_opcode m68k_opcodes[]; 373 extern const struct m68k_opcode_alias m68k_opcode_aliases[]; 374 375 extern const int m68k_numopcodes, m68k_numaliases; 376 377 /* end of m68k-opcode.h */ 378