1 ifndef __mcf547xinc ; avoid multiple inclusion 2__mcf547xinc equ 1 3 4 save 5 listing off ; no listing over this file 6 7;**************************************************************************** 8;* * 9;* AS 1.42 - File MCF547X.INC * 10;* * 11;* Contains SFR and Bit Definitions for ColdFire MCF547x * 12;* * 13;**************************************************************************** 14 15 ifndef MBAR 16MBAR equ $fc000000 17 warning "MBAR not set - assume default value $fc000000" 18 endif 19 20;---------------------------------------------------------------------------- 21; System Integration Unit 22 23SBCR equ MBAR+$10 ; System Breakpoint Control Register (32b) 24PIN2CPU cfbit SBCR,31 ; Pin control of the ColdFire V4e breakpoint. 25PIN2DMA cfbit SBCR,30 ; Pin control of the multichannel DMA breakpoint. 26CPU2DMA cfbit SBCR,29 ; ColdFire V4e control of the multichannel DMA breakpoint. 27DMA2CPU cfbit SBCR,28 ; DMA control of the ColdFire V4e breakpoint. 28PIN2DSPI cfbit SBCR,27 ; Pin control of the DSPI breakpoint. 29SECSACR equ MBAR+$38 ; Sequential Access Control Register (32b) 30SEQEN cfbit SECSACR,0 ; SEC Sequential access enable. 31RSR equ MBAR+$44 ; Reset Status Register (32b) 32RSTJTG cfbit RSR,3 ; JTAG reset asserted. 33RSTWD cfbit RSR,1 ; General purpose watchdog timer reset asserted. 34RST cfbit RSR,0 ; External reset (PLL Lock qualification) asserted. 35JTAGID equ MBAR+$50 ; JTAG Device Identification Number 36 37;---------------------------------------------------------------------------- 38; PLL 39 40SPCR equ MBAR+$300 ; System PLL Control Register (32b) 41PLLK cfbit SPCR,31 ; System PLL Lock Status 42COREN cfbit SPCR,14 ; Core & Communications Sub-System Clock Enable 43CRYENB cfbit SPCR,13 ; Crypto Clock Enable B 44CRYENA cfbit SPCR,12 ; Crypto Clock Enable A 45CAN1EN cfbit SPCR,11 ; CAN1 Clock Enable 46PSCEN cfbit SPCR,9 ; PSC Clock Enable 47USBEN cfbit SPCR,7 ; USB Clock Enable 48FEC1EN cfbit SPCR,6 ; FEC1 Clock Enable 49FEC0EN cfbit SPCR,5 ; FEC0 Clock Enable 50DMAEN cfbit SPCR,4 ; Multi-channel DMA Clock Enable 51CAN0EN cfbit SPCR,3 ; CAN0 Clock Enable 52FBEN cfbit SPCR,2 ; FlexBus Clock Enable 53PCIEN cfbit SPCR,1 ; PCI Bus Clock Enable 54MEMEN cfbit SPCR,0 ; Memory Clock Enable 55 56;---------------------------------------------------------------------------- 57; XL Bus Arbiter 58 59MBAR_XLB equ MBAR+$200 60 61XARB_CFG equ MBAR_XLB+$40 ; Arbiter Configuration Register (32b) 62PLDIS cfbit XARB_CFG,31 ; Pipeline Disable. 63SP cffield XARB_CFG,8,3 ; Select Parked Master. 64PM cffield XARB_CFG,5,2 ; Parking Mode. 65BA cfbit XARB_CFG,3 ; Bus Activity Time-out Enable. 66DT cfbit XARB_CFG,2 ; Data Tenure Time-out Enable. 67AT cfbit XARB_CFG,1 ; Address Tenure Time-out Enable. 68XARB_VER equ MBAR_XLB+$44 ; Arbiter Version Register (32b) 69VER cffield XARB_VER,0,32 ; Hardware Version ID. 70XARB_SR equ MBAR_XLB+$48 ; Arbiter Status Register (32b) 71SEA cfbit XARB_SR,8 ; Slave Error Acknowledge. 72MM cfbit XARB_SR,7 ; Multiple Masters at priority 0. 73TTA cfbit XARB_SR,6 ; TT Address Only. 74TTR cfbit XARB_SR,5 ; TT Reserved. 75ECW cfbit XARB_SR,4 ; External Control Word Read/Write. 76TTM cfbit XARB_SR,3 ; TBST/TSIZ mismatch. 77BA cfbit XARB_SR,2 ; Bus Activity Tenure Time-out. 78DT cfbit XARB_SR,1 ; Data Tenure Time-out. 79AT cfbit XARB_SR,0 ; Address Tenure Time-out. 80XARB_IMR equ MBAR_XLB+$4c ; Arbiter Interrupt Mask Register (32b) 81SEAE cfbit XARB_IMR,8 ; Slave Error Acknowledge interrupt enable. 82MME cfbit XARB_IMR,7 ; Multiple Masters at priority 0 interrupt enable. 83TTAE cfbit XARB_IMR,6 ; TT Address Only interrupt enable. 84TTRE cfbit XARB_IMR,5 ; TT Reserved interrupt enable. 85ECWE cfbit XARB_IMR,4 ; External Control Word Read/Write interrupt enable. 86TTME cfbit XARB_IMR,3 ; TBST/TSIZ mismatch interrupt enable. 87BAE cfbit XARB_IMR,2 ; Bus Activity Tenure Time-out interrupt enable. 88DTE cfbit XARB_IMR,1 ; Data Tenure Time-out interrupt enable. 89ATEq cfbit XARB_IMR,0 ; Address Tenure Time-out interrupt enable. 90XARB_ADRCAP equ MBAR_XLB+$50 ; Arbiter Address Capture (32b) 91ADRCAP cffield XARB_ADRCAP,0,32; Address that is captured when a bus error occurs. 92XARB_SIGCAP equ MBAR_XLB+$54 ; Arbiter Signal Capture (32b) 93TSIZ cffield XARB_SIGCAP,7,3 ; Transfer Size. 94TBST cfbit XARB_SIGCAP,5 ; Burst/Non-Burst 95TT cffield XARB_SIGCAP,0,5 ; Transfer Type 96XARB_ADRTO equ MBAR_XLB+$58 ; Arbiter Address Timeout (32b) 97ADRTO cffield XARB_ADRTO,0,28 ; Upper 28-bits of the Address time-out counter value. 98XARB_DATTO equ MBAR_XLB+$5c ; Arbiter Data Timeout (32b) 99DATTO cffield XARB_DATTO,0,28 ; Upper 28-bits fo the Data time-out counter value. 100XARB_BUSTO equ MBAR_XLB+$60 ; Arbiter Bus Timeout (32b) 101BUSTO cffield XARB_BUSTO,0,32 ; Bus activity time-out counter value in XLB clocks. 102XARB_PRIEN equ MBAR_XLB+$64 ; Arbiter Master Priority Enable (32b) 103M3 cfbit XARB_PRIEN,3 ; Master 3 Priority Register Enable 104M2 cfbit XARB_PRIEN,2 ; Master 2 Priority Register Enable 105M0 cfbit XARB_PRIEN,0 ; Master 0 Priority Register Enable 106XARB_PRI equ MBAR_XLB+$68 ; Arbiter Master Priority (32b) 107M3P cffield XARB_PRI,12,3 ; Master 3 Priority 108M2P cffield XARB_PRI,8,3 ; Master 2 Priority 109M0P cffield XARB_PRI,0,3 ; Master 0 Priority 110 111;---------------------------------------------------------------------------- 112; General Purpose Timers 113 114__defgpt macro N,Base 115GMS{N} equ Base+0 ; GPT Enable and Mode Select Register n (32b) 116OCPW cffield GMS{N},24,8 ; Output capture pulse width. 117OCT cffield GMS{N},20,2 ; Output capture type. 118ICT cffield GMS{N},16,2 ; Input capture type. 119WDEN cfbit GMS{N},15 ; Watchdog enable. 120CE cfbit GMS{N},12 ; Counter enable. 121SC cfbit GMS{N},10 ; Stop/continuous mode. 122OD cfbit GMS{N},9 ; Open drain. 123IEN cfbit GMS{N},8 ; Interrupt enable. 124GPIO cffield GMS{N},4,2 ; GPIO mode type. 125TMS cffield GMS{N},0,3 ; Timer mode select (and module enable). 126GCIR{N} equ Base+4 ; GPT Counter Input Register n (32b) 127PRE cffield GCIR{N},16,16 ; Prescaler. 128CNT cffield GCIR{N},0,16 ; Count value. 129GPWM{N} equ Base+8 ; GPT PWM Configuration Register n (32b) 130WIDTH cffield GPWM{N},16,16 ; PWM width. 131PWMOP cfbit GPWM{N},8 ; PWM output polarity. 132LOAD cfbit GPWM{N},0 ; Bit forces immediate period update. 133GSR{N} equ Base+12 ; GPT Status Register n (32b) 134CAPTURE cffield GSR{N},16,16 ; Read of internal counter, latch at reference event. 135OVF cffield GSR{N},12,3 ; Overflow counter. 136PIN cfbit GSR{N},8 ; GPIO input value. 137TEXP cfbit GSR{N},3 ; Timer expired in internal timer mode. 138PWMP cfbit GSR{N},2 ; PWM end of period occurred. 139COMP cfbit GSR{N},1 ; OC reference event occurred. 140CAPT cfbit GSR{N},0 ; IC reference event occurred. 141 endm 142 __defgpt "0",MBAR+$800 143 __defgpt "1",MBAR+$810 144 __defgpt "2",MBAR+$820 145 __defgpt "3",MBAR+$830 146 147;---------------------------------------------------------------------------- 148; Slice Timers 149 150__defslt macro N,Base 151STCNT{N} equ Base+0 ; SLT Terminal Count Register n (32b) 152TC cffield STCNT{N},0,32 ; Terminal count. 153SCR{N} equ Base+4 ; SLT Control Register n (32b) 154RUN cfbit SCR{N},26 ; Run or wait mode 155IEN cfbit SCR{N},25 ; Interrupt enable. 156TEN cfbit SCR{N},24 ; Timer enable 157SCNT{N} equ Base+8 ; SLT Count Value Register n (32b) 158CNT cffield SCNT{N},0,32 ; Timer count. 159SSR{N} equ Base+12 ; SLT Status Register n (32b) 160BE cfbit SSR{N},25 ; Bus Error Status. 161ST cfbit SSR{N},24 ; SLT timeout. 162 endm 163 __defslt "0",MBAR+$900 164 __defslt "1",MBAR+$910 165 166;---------------------------------------------------------------------------- 167; Interrupt Controller 168 169MBAR_INTC equ MBAR+$700 170IPRH equ MBAR_INTC+$00 ; Interrupt Pending Register High (32b) 171IPRL equ MBAR_INTC+$04 ; Interrupt Pending Register Low (32b) 172IMRH equ MBAR_INTC+$08 ; Interrupt Mask Register High (32b) 173IMRL equ MBAR_INTC+$0c ; Interrupt Mask Register Low (32b) 174INTFRCH equ MBAR_INTC+$10 ; Interrupt Force Register High (32b) 175INTFRCL equ MBAR_INTC+$14 ; Interrupt Force Register Low (32b) 176IRLR equ MBAR_INTC+$18 ; Interrupt Request Level Register (8b) 177IRQ cffield IRLR,1,7 ; Interrupt requests. 178IACKLPR equ MBAR_INTC+$19 ; Interrupt Acknowledge Level and Priority Register (8b) 179LEVEL cffield IACKLPR,4,3 ; Interrupt level. 180PRI cffield IACKLPR,0,4 ; Interrupt Priority. 181__N set 1 182 rept 64 183 __dec02str __NS,__N 184ICR{"\{__NS}"} equ MBAR_INTC+$040+__N; Interrupt Control Register N (8b) 185IL cffield ICR{"\{__NS}"},3,3 ; Interrupt level. 186IP cffield ICR{"\{__NS}"},0,3 ; Interrupt priority. 187__N set __N+1 188 endm 189SWIACK equ MBAR_INTC+$e0 ; Software Interrupt Acknowledge (8b) 190__N set 1 191 rept 6 192 __decstr __NS,__N 193L{"\{__NS}"}IACK equ MBAR_INTC+$e0+(4*__N) ; Interrupt Acknowledge Register N (8b) 194__N set __N+1 195 endm 196 197;---------------------------------------------------------------------------- 198; Edge Port Module 199 200MBAR_EPORT equ MBAR+$f00 201 include "52xxeport.inc" ; TODO: edge port 0 not defined on 547x 202 203;---------------------------------------------------------------------------- 204; GPIO 205 206MBAR_GPIO equ MBAR+$a00 207 208; Port Output Data Registers 209 210PODR_FBCTL equ MBAR_GPIO+$00 ; FlexBus Control Output Data Register (8b) 211PODR_FBCS equ MBAR_GPIO+$01 ; FlexBus ChipSelect Output Data Register (8b) 212PODR_DMA equ MBAR_GPIO+$02 ; DMA Output Data Register (8b) 213PODR_FEC0H equ MBAR_GPIO+$04 ; FEC0 High Output Data Register (8b) 214PODR_FEC0L equ MBAR_GPIO+$05 ; FEC0 Low Output Data Register (8b) 215PODR_FEC1H equ MBAR_GPIO+$06 ; FEC1 High Output Data Register (8b) 216PODR_FEC1L equ MBAR_GPIO+$07 ; FEC1 Low Output Data Register (8b) 217PODR_FECI2C equ MBAR_GPIO+$08 ; FEC/I2C Output Data Register (8b) 218PODR_PCIBG equ MBAR_GPIO+$09 ; PCI Grant Output Data Register (8b) 219PODR_PCIBR equ MBAR_GPIO+$0a ; PCI Request Output Data Register (8b) 220PODR_PSC3PSC2 equ MBAR_GPIO+$0c ; Progr. Serial Controller 3/2 Output Data Register (8b) 221PODR_PSC1PSC0 equ MBAR_GPIO+$0d ; Progr. Serial Controller 1/0 Output Data Register (8b) 222PODR_DSPI equ MBAR_GPIO+$0e ; DMA Serial Peripheral Interface Output Data Register (8b) 223 224; Port Data Direction Registers 225 226PDDR_FBCTL equ MBAR_GPIO+$10 ; FlexBus Control Data Direction Register (8b) 227PDDR_FBCS equ MBAR_GPIO+$11 ; FlexBus ChipSelect Data Direction Register (8b) 228PDDR_DMA equ MBAR_GPIO+$12 ; DMA Output Data Direction Register (8b) 229PDDR_FEC0H equ MBAR_GPIO+$14 ; FEC0 High Data Direction Register (8b) 230PDDR_FEC0L equ MBAR_GPIO+$15 ; FEC0 Low Data Direction Register (8b) 231PDDR_FEC1H equ MBAR_GPIO+$16 ; FEC1 High Data Direction Register (8b) 232PDDR_FEC1L equ MBAR_GPIO+$17 ; FEC1 Low Data Direction Register (8b) 233PDDR_FECI2C equ MBAR_GPIO+$18 ; FEC/I2C Data Direction Register (8b) 234PDDR_PCIBG equ MBAR_GPIO+$19 ; PCI Grant Data Direction Register (8b) 235PDDR_PCIBR equ MBAR_GPIO+$1a ; PCI Request Data Direction Register (8b) 236PDDR_PSC3PSC2 equ MBAR_GPIO+$1c ; Progr. Serial Controller 3/2 Data Direction Register (8b) 237PDDR_PSC1PSC0 equ MBAR_GPIO+$1d ; Progr. Serial Controller 1/0 Data Direction Register (8b) 238PDDR_DSPI equ MBAR_GPIO+$1e ; DMA Serial Peripheral Interface Data Direction Register (8b) 239 240; Port Pin Data/Set Data Registers 241 242PPDSDR_FBCTL equ MBAR_GPIO+$20 ; FlexBus Control Data/Set Data Register (8b) 243PPDSDR_FBCS equ MBAR_GPIO+$21 ; FlexBus ChipSelect Data/Set Data Register (8b) 244PPDSDR_DMA equ MBAR_GPIO+$22 ; DMA Output Data/Set Data Register (8b) 245PPDSDR_FEC0H equ MBAR_GPIO+$24 ; FEC0 High Data/Set Data Register (8b) 246PPDSDR_FEC0L equ MBAR_GPIO+$25 ; FEC0 Low Data/Set Data Register (8b) 247PPDSDR_FEC1H equ MBAR_GPIO+$26 ; FEC1 High Data/Set Data Register (8b) 248PPDSDR_FEC1L equ MBAR_GPIO+$27 ; FEC1 Low Data/Set Data Register (8b) 249PPDSDR_FECI2C equ MBAR_GPIO+$28 ; FEC/I2C Data/Set Data Register (8b) 250PPDSDR_PCIBG equ MBAR_GPIO+$29 ; PCI Grant Data/Set Data Register (8b) 251PPDSDR_PCIBR equ MBAR_GPIO+$2a ; PCI Request Data/Set Data Register (8b) 252PPDSDR_PSC3PSC2 equ MBAR_GPIO+$2c ; Progr. Serial Controller 3/2 Data/Set Data Register (8b) 253PPDSDR_PSC1PSC0 equ MBAR_GPIO+$2d ; Progr. Serial Controller 1/0 Data/Set Data Register (8b) 254PPDSDR_DSPI equ MBAR_GPIO+$2e ; DMA Serial Peripheral Interface Data/Set Data Register (8b) 255 256; Port Clear Output Data Registers 257 258PCLRR_FBCTL equ MBAR_GPIO+$30 ; FlexBus Control Clear Output Data Register (8b) 259PCLRR_FBCS equ MBAR_GPIO+$31 ; FlexBus ChipSelect Clear Output Data Register (8b) 260PCLRR_DMA equ MBAR_GPIO+$32 ; DMA Output Clear Output Data Register (8b) 261PCLRR_FEC0H equ MBAR_GPIO+$34 ; FEC0 High Clear Output Data Register (8b) 262PCLRR_FEC0L equ MBAR_GPIO+$35 ; FEC0 Low Clear Output Data Register (8b) 263PCLRR_FEC1H equ MBAR_GPIO+$36 ; FEC1 High Clear Output Data Register (8b) 264PCLRR_FEC1L equ MBAR_GPIO+$37 ; FEC1 Low Clear Output Data Register (8b) 265PCLRR_FECI2C equ MBAR_GPIO+$38 ; FEC/I2C Clear Output Data Register (8b) 266PCLRR_PCIBG equ MBAR_GPIO+$39 ; PCI Grant Clear Output Data Register (8b) 267PCLRR_PCIBR equ MBAR_GPIO+$3a ; PCI Request Clear Output Data Register (8b) 268PCLRR_PSC3PSC2 equ MBAR_GPIO+$3c ; Progr. Serial Controller 3/2 Clear Output Data Register (8b) 269PCLRR_PSC1PSC0 equ MBAR_GPIO+$3d ; Progr. Serial Controller 1/0 Clear Output Data Register (8b) 270PCLRR_DSPI equ MBAR_GPIO+$3e ; DMA Serial Peripheral Clear Output Data Register (8b) 271 272; Pin Assignment Registers 273 274PAR_FBCTL equ MBAR_GPIO+$00 ; FlexBus Control Pin Assignment Register (16b) 275PAR_BWE3 cfbit PAR_FBCTL,14 ; -BE3/-BWE3 Usage 276PAR_BWE2 cfbit PAR_FBCTL,12 ; -BE2/-BWE2 Usage 277PAR_BWE1 cfbit PAR_FBCTL,10 ; -BE1/-BWE1 Usage 278PAR_BWE0 cfbit PAR_FBCTL,8 ; -BE0/-BWE0 Usage 279PAR_OE cfbit PAR_FBCTL,6 ; -OE Usage 280PAR_RWB cffield PAR_FBCTL,4,2 ; -R/-W Usage 281PAR_TA cfbit PAR_FBCTL,2 ; -TA Usage 282PAR_ALE cffield PAR_FBCTL,0,2 ; ALE Usage 283PAR_FBCS equ MBAR_GPIO+$02 ; FlexBus ChipSelect Pin Assignment Register (8b) 284PAR_CS5 cfbit PAR_FBCS,5 ; -FBCS5 Usage 285PAR_CS4 cfbit PAR_FBCS,4 ; -FBCS4 Usage 286PAR_CS3 cfbit PAR_FBCS,3 ; -FBCS3 Usage 287PAR_CS2 cfbit PAR_FBCS,2 ; -FBCS2 Usage 288PAR_CS1 cfbit PAR_FBCS,1 ; -FBCS1 Usage 289PAR_DMA equ MBAR_GPIO+$03 ; DMA Output Pin Assignment Register (8b) 290PAR_DACK1 cffield PAR_DMA,6,2 ; -DACK1 Usage 291PAR_DACK0 cffield PAR_DMA,4,2 ; -DACK0 Usage 292PAR_DREQ1 cffield PAR_DMA,2,2 ; -DREQ1 Usage 293PAR_DREQ0 cffield PAR_DMA,0,2 ; -DREQ0 Usage 294PAR_FECI2CIRQ equ MBAR_GPIO+$04 ; FEC/I2C Pin Assignment Register (16b) 295PAR_E07 cfbit PAR_FECI2CIRQ,15; FEC0 7-wire mode pin assignment. 296PAR_E0MII cfbit PAR_FECI2CIRQ,14; FEC1 MII mode-only pin assignment. 297PAR_E0MDIO cfbit PAR_FECI2CIRQ,13; FEC0 MDIO pin assignment. 298PAR_E0MDC cfbit PAR_FECI2CIRQ,12; FEC0 MDC pin assignment. 299PAR_E17 cfbit PAR_FECI2CIRQ,11; FEC1 7-wire mode pin assignment. 300PAR_E1MII cfbit PAR_FECI2CIRQ,10; FEC1 MII mode-only pin assignment. 301PAR_E1MDIO cffield PAR_FECI2CIRQ,8,2; FEC1 MDIO pin assignment. 302PAR_E1MDC cffield PAR_FECI2CIRQ,6,2; FEC1 MDC pin assignment. 303PAR_SDA cfbit PAR_FECI2CIRQ,3 ; SDA Pin Assignment. 304PAR_SCL cfbit PAR_FECI2CIRQ,2 ; SCL Pin Assignment. 305PAR_IRQ6 cfbit PAR_FECI2CIRQ,1 ; -IRQ6 Pin Assignment. 306PAR_IRQ5 cfbit PAR_FECI2CIRQ,0 ; -IRQ5 Pin Assignment. 307PAR_PCIBG equ MBAR_GPIO+$08 ; PCI Grant Pin Assignment Register (16b) 308PAR_PCIBG4 cffield PAR_PCIBG,8,2 ; -PCIBG4 pin assignment. 309PAR_PCIBG3 cffield PAR_PCIBG,6,2 ; -PCIBG3 pin assignment. 310PAR_PCIBG2 cffield PAR_PCIBG,4,2 ; -PCIBG2 pin assignment. 311PAR_PCIBG1 cffield PAR_PCIBG,2,2 ; -PCIBG1 pin assignment. 312PAR_PCIBG0 cffield PAR_PCIBG,0,2 ; -PCIBG0 pin assignment. 313PAR_PCIBR equ MBAR_GPIO+$0a ; PCI Request Pin Assignment Register (16b) 314PAR_PCIBR4 cffield PAR_PCIBR,8,2 ; -PCIBR4 Pin Assignment. 315PAR_PCIBR3 cffield PAR_PCIBR,6,2 ; -PCIBR3 Pin Assignment. 316PAR_PCIBR2 cffield PAR_PCIBR,4,2 ; -PCIBR2 Pin Assignment. 317PAR_PCIBR1 cffield PAR_PCIBR,2,2 ; -PCIBR1 Pin Assignment. 318PAR_PCIBR0 cffield PAR_PCIBR,0,2 ; -PCIBR0 Pin Assignment. 319PAR_PSC3 equ MBAR_GPIO+$0c ; Progr. Serial Controller 3 Pin Assignment Register (8b) 320PAR_CTS3 cffield PAR_PSC3,6,2 ; -PSC3CTS pin assignment. 321PAR_RTS3 cffield PAR_PSC3,4,2 ; -PSC3RTS pin assignment. 322PAR_RXD3 cfbit PAR_PSC3,3 ; PSC3RXD pin assignment. 323PAR_TXD3 cfbit PAR_PSC3,2 ; PSC3TXD pin assignment. 324PAR_PSC2 equ MBAR_GPIO+$0d ; Progr. Serial Controller 2 Pin Assignment Register (8b) 325PAR_CTS2 cffield PAR_PSC2,6,2 ; -PSC2CTS pin assignment. 326PAR_RTS2 cffield PAR_PSC2,4,2 ; -PSC2RTS pin assignment. 327PAR_RXD2 cfbit PAR_PSC2,3 ; PSC2RXD pin assignment. 328PAR_TXD2 cfbit PAR_PSC2,2 ; PSC2TXD pin assignment. 329PAR_PSC1 equ MBAR_GPIO+$0e ; Progr. Serial Controller 1 Pin Assignment Register (8b) 330PAR_CTS1 cffield PAR_PSC1,6,2 ; -PSC1CTS pin assignment. 331PAR_RTS1 cffield PAR_PSC1,4,2 ; -PSC1RTS pin assignment. 332PAR_RXD1 cfbit PAR_PSC1,3 ; PSC1RXD pin assignment. 333PAR_TXD1 cfbit PAR_PSC1,2 ; PSC1TXD pin assignment. 334PAR_PSC0 equ MBAR_GPIO+$0f ; Progr. Serial Controller 0 Pin Assignment Register (8b) 335PAR_CTS0 cffield PAR_PSC0,6,2 ; -PSC0CTS pin assignment. 336PAR_RTS0 cffield PAR_PSC0,4,2 ; -PSC0RTS pin assignment. 337PAR_RXD0 cfbit PAR_PSC0,3 ; PSC0RXD pin assignment. 338PAR_TXD0 cfbit PAR_PSC0,2 ; PSC0TXD pin assignment. 339PAR_DSPI equ MBAR_GPIO+$10 ; DMA Serial Peripheral Pin Assignment Register (16b) 340PAR_CS5 cfbit PAR_DSPI,12 ; DSPICS5/-PCSS pin assignment. 341PAR_CS3 cffield PAR_DSPI,10,2 ; DSPICS3 pin assignment. 342PAR_CS2 cffield PAR_DSPI,8,2 ; DSPICS2 pin assignment. 343PAR_CS0 cffield PAR_DSPI,6,2 ; DSPICS0/-SS pin assignment. 344PAR_SCK cffield PAR_DSPI,4,2 ; DSPISCK pin assignment. 345PAR_SIN cffield PAR_DSPI,2,2 ; DSPISIN pin assignment. 346PAR_SOUT cffield PAR_DSPI,0,2 ; DSPISOUT pin assignment. 347PAR_TIMER equ MBAR_GPIO+$12 ; Timer Pin Assignment Register (8b) 348PAR_TIN3 cffield PAR_TIMER,4,2 ; TIN3 pin assignment. 349PAR_TOUT3 cfbit PAR_TIMER,3 ; TOUT3 pin assignment. 350PAR_TIN2 cffield PAR_TIMER,1,2 ; TIN2 pin assignment. 351PAR_TOUT2 cfbit PAR_TIMER,0 ; TOUT2 pin assignment. 352 353;---------------------------------------------------------------------------- 354; FlexBus 355 356MBAR_FBUS equ MBAR+$500 357 include "52xxfbus.inc" 358 359;---------------------------------------------------------------------------- 360; SDRAM Controller 361 362SDRAMDS equ MBAR+$04 ; SDRAM Drive Strength Register (32b) 363SB_E cffield SDRAMDS,8,2 ; Controls the drive strength of SDCKE. 364SB_C cffield SDRAMDS,6,2 ; Controls the drive strength of SDRAM clocks. 365SB_A cffield SDRAMDS,4,2 ; Controls the drive strength of SDCS[3:0], RAS, CAS, SDWE, SDADDR[12:0], and SDBA[1:0]. 366SB_S cffield SDRAMDS,2,2 ; Controls the drive strength of SDRDQS. 367SB_D cffield SDRAMDS,0,2 ; Controls the drive strength of SDDATA[31:0], SDDM[3:0], and SDQS[3:0]. 368__N set 0 369 rept 4 370 __decstr __NS,__N 371CS{__NS}CFG equ MBAR+$20+(__N*4); SDRAM Chip Select Configuration Registers n (32b) 372CSBA cffield CS{__NS}CFG,20,12 ; Chip select base address. 373CSSZ cffield CS{__NS}CFG,0,5 ; Chip select size. 374__N set __N+1 375 endm 376 377MBAR_SDRAM equ MBAR+$100 ; like 52xx SDRAM with different names 378 379SDMR equ MBAR_SDRAM+0 ; Mode/Extended Mode Register (32b) 380BNKAD cffield SDMR,30,2 ; Bank Address 381AD cffield SDMR,18,12 ; Address 382CMD cfbit SDMR,16 ; Command 383SDCR equ MBAR_SDRAM+4 ; Control Register (32b) 384MODE_EN cfbit SDCR,31 ; SDRAM Mode Register Programming Enable 385CKE cfbit SDCR,30 ; Clock Enable 386DDR cfbit SDCR,29 ; DDR Mode Select 387REF cfbit SDCR,28 ; Refresh Enable 388MUX cffield SDCR,24,2 ; Use of Internal Address Bits A[27:24] 389AP cfbit SDCR,23 ; Auto precharge control bit. 390DRIVE cfbit SDCR,22 ; Drive Rule Selection 391RCNT cffield SDCR,16,6 ; Refresh Rate 392DQS_OE cffield SDCR,8,4 ; DQS Output Enable 393BUFF cfbit SDCR,4 ; Buffering mode. 394IREF cfbit SDCR,2 ; Initiate Refresh Command 395IPALL cfbit SDCR,1 ; Initiate Precharge All Command 396SDCFG1 equ MBAR_SDRAM+8 ; Configuration Register 1 (32b) 397SRD2RW cffield SDCFG1,28,4 ; Single Read to Read/Write/Precharge Delay 398SWT2RD cffield SDCFG1,24,3 ; Single Write to Read/Write/Precharge Delay 399RDLAT cffield SDCFG1,20,4 ; Read CAS Latency 400ACT2RW cffield SDCFG1,16,3 ; Active to Read/Write Delay 401PRE2ACT cffield SDCFG1,12,3 ; Precharge to Active Delay 402REF2ACT cffield SDCFG1,8,4 ; Refresh to Active Delay 403WTLAT cffield SDCFG1,4,3 ; Write Latency 404SDCFG2 equ MBAR_SDRAM+12 ; Configuration Register 2 (32b) 405BRD2PRE cffield SDCFG2,28,4 ; Burst Read to Read/Precharge Delay 406BWT2RW cffield SDCFG2,24,4 ; Burst Write to Read/Write/Precharge Delay 407BRD2WT cffield SDCFG2,20,4 ; Burst Read to Write Delay 408BL cffield SDCFG2,16,4 ; Burst Length 409;---------------------------------------------------------------------------- 410; PCI Controller 411 412MBAR_PCI equ MBAR+$b00 413MBAR_CBUSPCI equ MBAR+$8400 414 415; PCI Type 0 Configuration Registers 416 417PCIIDR equ MBAR_PCI+$00 ; PCI Device ID/Vendor ID (32b) 418DEVICE_ID cffield PCIIDR,16,16 ; PCI Device Id assigned to the MCF547x. 419VENDOR_ID cffield PCIIDR,0,16 ; PCI Vendor Id assigned to the MCF547x. 420PCISCR equ MBAR_PCI+$04 ; PCI Status/Command (32b) 421PE cfbit PCISCR,31 ; Parity error detected. 422SE cfbit PCISCR,30 ; System error signalled. 423MA cfbit PCISCR,29 ; Master abort received. 424TR cfbit PCISCR,28 ; Target abort received. 425TS cfbit PCISCR,27 ; Target abort signalled. 426DT cffield PCISCR,25,2 ; DEVSEL timing. 427DP cfbit PCISCR,24 ; Master data parity error. 428FC cfbit PCISCR,23 ; Fast back-to-back capable. 429R cfbit PCISCR,22 ; Reserved. 43066M cfbit PCISCR,21 ; 66 MHz capable. 431C cfbit PCISCR,20 ; Capabilities list. 432F cfbit PCISCR,9 ; Fast back-to-back transfer enable. 433S cfbit PCISCR,8 ; SERR enable. 434ST cfbit PCISCR,7 ; Address and data stepping. 435PER cfbit PCISCR,6 ; Parity error response. 436V cfbit PCISCR,5 ; VGA palette snoop enable. 437MW cfbit PCISCR,4 ; Memory write and invalidate enable. 438SP cfbit PCISCR,3 ; Special cycle monitor or ignore. 439B cfbit PCISCR,2 ; Bus master enable. 440M cfbit PCISCR,1 ; Memory access control. 441IO cfbit PCISCR,0 ; I/O access control. 442PCICCRIR equ MBAR_PCI+$08 ; PCI Class Code/Revision ID (32b) 443CLASS_CODE cffield PCICCRIR,8,24 ; PCI Class Code assigned to processor. 444REVISION_ID cffield PCICCRIR,0,8 ; PCI Revision ID for this version of the processor. 445PCICR1 equ MBAR_PCI+$0c ; PCI Configuration 1 Register (32b) 446BIST cffield PCICR1,24,8 ; BIST 447HEADER_TYPE cffield PCICR1,16,8 ; Header Type 448LAT_TIMER cffield PCICR1,8,8 ; Lat Timer 449CLSIZ cffield PCICR1,0,8 ; Cache Line Size 450PCIBAR0 equ MBAR_PCI+$10 ; PCI Base Address Register 0 (32b) 451BAR0 cffield PCIBAR0,18,12 ; Base address register 0 (b12..31) 452PREF cfbit PCIBAR0,3 ; Prefetchable access. 453RANGE cffield PCIBAR0,1,2 ; Fixed to 00. 454IOM cfbit PCIBAR0,0 ; IO or memory space. 455PCIBAR1 equ MBAR_PCI+$14 ; PCI Base Address Register 1 (32b) 456BAR1 cffield PCIBAR1,30,2 ; Base address register 1 (b30..31) 457PREF cfbit PCIBAR1,3 ; Prefetchable access. 458RANGE cffield PCIBAR1,1,2 ; Fixed to 00. 459IOM cfbit PCIBAR1,0 ; IO or memory space. 460PCICCPR equ MBAR_PCI+$28 ; PCI Cardbus CIS Pointer (32b) 461PCISID equ MBAR_PCI+$2c ; Subsystem ID/Subsystem Vendor ID (32b) 462PCIERBAR equ MBAR_PCI+$30 ; PCI Expansion ROM (32b) 463PCICPR equ MBAR_PCI+$34 ; PCI Capabilities Pointer (32b) 464PCICR2 equ MBAR_PCI+$3c ; PCI Configuration Register 2 (32b) 465MAX_LAT cffield PCICR2,24,8 ; Maximum latency. 466MIN_GNT cffield PCICR2,16,8 ; Minimum grant. 467INTERRUPT_PIN cffield PCICR2,8,8 ; Fixed to 0x00. 468INTERRUPT_LINE cffield PCICR2,0,8 ; Fixed to 0x00. 469 470; General Control/Status Registers 471 472PCIGSCR equ MBAR_PCI+$60 ; Global Status/Control Register (32b) 473PE cfbit PCIGSCR,29 ; PERR detected. 474SE cfbit PCIGSCR,28 ; SERR detected. 475XLB2CLKIN cffield PCIGSCR,24,3 ; stores the XL bus clock to external PCI clock (CLKIN)divide ratio. 476PEE cfbit PCIGSCR,13 ; Parity error interrupt enable. 477SEE cfbit PCIGSCR,12 ; System error interrupt enable. 478PR cfbit PCIGSCR,0 ; PCI reset. 479PCITBATR0 equ MBAR_PCI+$64 ; Target Base Address Translation Register 0 (32b) 480BAT0 cffield PCITBATR0,18,14 ; Base address (b18...31) 481EN cfbit PCITBATR0,0 ; Enables a transaction in BAR0 space. 482PCITBATR1 equ MBAR_PCI+$68 ; Target Base Address Translation Register 1 (32b) 483BAT1 cffield PCITBATR1,30,2 ; Base address (b30..31) 484EN cfbit PCITBATR1,0 ; Enables a transaction in BAR1 space. 485PCITCR equ MBAR_PCI+$6c ; Target Control Register (32b) 486LD cfbit PCITCR,24 ; Latency rule disable. 487P cfbit PCITCR,16 ; Prefetch reads. 488PCIIW0BTAR equ MBAR_PCI+$70 ; Initiator Window 0 Base/Translation Address Register (32b) 489W0BAR cffield PCIIW0BTAR,24,8 ; Window 0 Base Address 490W0AM cffield PCIIW0BTAR,16,8 ; Window 0 Address Mask 491W0TA cffield PCIIW0BTAR,8,8 ; Window 0 Translation Address 492PCIIW1BTAR equ MBAR_PCI+$74 ; Initiator Window 1 Base/Translation Address Register (32b) 493W1BAR cffield PCIIW1BTAR,24,8 ; Window 1 Base Address 494W1AM cffield PCIIW1BTAR,16,8 ; Window 1 Address Mask 495W1TA cffield PCIIW1BTAR,8,8 ; Window 1 Translation Address 496PCIIW2BTAR equ MBAR_PCI+$78 ; Initiator Window 2 Base/Translation Address Register (32b) 497W2BAR cffield PCIIW2BTAR,24,8 ; Window 2 Base Address 498W2AM cffield PCIIW2BTAR,16,8 ; Window 2 Address Mask 499W2TA cffield PCIIW2BTAR,8,8 ; Window 2 Translation Address 500PCIIWCR equ MBAR_PCI+$80 ; Initiator Window Configuration Register (32b) 501W0CTRL cffield PCIIWCR,24,4 ; Window 0 Control 502W1CTRL cffield PCIIWCR,16,4 ; Window 1 Control 503W2CTRL cffield PCIIWCR,8,4 ; Window 2 Control 504PCIICR equ MBAR_PCI+$84 ; Initiator Control Register (32b) 505REE cfbit PCIICR,26 ; Retry error enable. 506IAE cfbit PCIICR,25 ; Initiator abort enable. 507TAE cfbit PCIICR,24 ; Target abort enable. 508MAX_RETRIES cffield PCIICR,0,8 ; maximum number of automatic PCI retries or master latency time-outs (write) 509PCIISR equ MBAR_PCI+$88 ; Initiator Status Register (32b) 510RE cfbit PCIISR,26 ; Retry error. 511IA cfbit PCIISR,25 ; Initiator abort. 512TA cfbit PCIISR,24 ; Target abort. 513PCICAR equ MBAR_PCI+$f8 ; Configuration Address Register (32b) 514E cfbit PCICAR,31 ; Enable. 515BUS_NUMBER cffield PCICAR,16,8 ; Target bus of the configuration access. 516DEV_NUMBER cffield PCICAR,11,5 ; Select a specific device on the target bus. 517FNC_NUMBER cffield PCICAR,8,3 ; Select a specific function in the requested device. 518DWORD cffield PCICAR,2,6 ; Select the Dword address offset in the configuration space of the target device. 519 520; CommBus FIFO Transmit Interface Registers 521 522PCITPSR equ MBAR_CBUSPCI+$00; Tx Packet Size Register (32b) 523PACKET_SIZE cffield PCITPSR,16,16 ; Packet Size 524PCITSAR equ MBAR_CBUSPCI+$04; Tx Start Address Register (32b) 525START_ADD cffield PCITSAR,0,32 ; PCI Packet Start Address 526PCITTCR equ MBAR_CBUSPCI+$08; Tx Transaction Control Register (32b) 527PCI_CMD cffield PCITTCR,24,4 ; PCI command to present during the address phase of each PCI transaction. 528MAX_RETRIES cffield PCITTCR,16,8 ; Maximum number of retries to permit "per packet". 529MAX_BEATS cffield PCITTCR,8,3 ; Number of PCI data beats to attempt on each PCI transaction. 530W cfbit PCITTCR,4 ; Word transfer. 531DI cfbit PCITTCR,0 ; Disable address incrementing. 532PCITER equ MBAR_CBUSPCI+$0c; Tx Enables Register (32b) 533RC cfbit PCITER,31 ; Reset controller. User 534RF cfbit PCITER,30 ; Reset FIFO. 535CM cfbit PCITER,28 ; Continuous mode. 536BE cfbit PCITER,27 ; Bus error enable. 537ME cfbit PCITER,24 ; Master enable. 538FEE cfbit PCITER,21 ; FIFO error enable. 539SE cfbit PCITER,20 ; System error enable. 540RE cfbit PCITER,19 ; Retry abort enable. 541TAE cfbit PCITER,18 ; Target abort enable. 542IAE cfbit PCITER,17 ; Initiator abort enable. 543NE cfbit PCITER,16 ; Normal termination enable. 544PCITNAR equ MBAR_CBUSPCI+$10; Tx Next Address Register (32b) 545NEX_TADDRESS cffield PCITNAR,0,32 ; Contains the next (unwritten) PCI address. 546PCITLWR equ MBAR_CBUSPCI+$14; Tx Last Word Register (32b) 547LAST_wORD cffield PCITLWR,0,32 ; indicates the last 32-bit data fetched from the FIFO 548PCITDCR equ MBAR_CBUSPCI+$18; Tx Done Counts Register (32b) 549BYTES_DONE cffield PCITDCR,16,16 ; Indicates the number of bytes transmitted since the start of a packet. 550PACKETS_DONE cffield PCITDCR,0,16 ; Indicates the number of previous packets transmitted. 551PCITSR equ MBAR_CBUSPCI+$1c; Tx Status Register (32b) 552NT cfbit PCITSR,24 ; Normal termination. 553BE3 cfbit PCITSR,23 ; Bus error type 3. 554BE2 cfbit PCITSR,22 ; Bus error type 2. 555BE1 cfbit PCITSR,21 ; Bus error type 1. 556FE cfbit PCITSR,20 ; FIFO error. 557SE cfbit PCITSR,19 ; System error. 558RE cfbit PCITSR,18 ; Retry error. 559TA cfbit PCITSR,17 ; Target abort. 560IA cfbit PCITSR,16 ; Initiator abort. 561PCITFDR equ MBAR_CBUSPCI+$40; Tx FIFO Data Register (32b) 562FIFO_DATA_WORD cffield PCITFDR,0,32 ; This is the data port to the FIFO. 563PCITFSR equ MBAR_CBUSPCI+$44; Tx FIFO Status Register (32b) 564IP cfbit PCITFSR,31 ; Illegal Pointer. 565TXW cfbit PCITFSR,30 ; Transmit Wait Condition. 566FAE cfbit PCITFSR,23 ; Frame accept error. 567RXW cfbit PCITFSR,22 ; Receive wait condition. 568UF cfbit PCITFSR,21 ; Underflow. 569OF cfbit PCITFSR,20 ; Overflow. 570FR cfbit PCITFSR,19 ; Frame ready. 571FULL cfbit PCITFSR,18 ; The FIFO is Full. 572ALARM cfbit PCITFSR,17 ; The FIFO is at or above the Alarm "watermark". 573EMPTY cfbit PCITFSR,16 ; The FIFO is empty. 574PCITFCR equ MBAR_CBUSPCI+$48; Tx FIFO Control Register (32b) 575WFR cfbit PCITFCR,29 ; Write frame. 576GR cffield PCITFCR,24,3 ; Granularity. 577IP_MASK cfbit PCITFCR,23 ; Illegal pointer mask. 578FAE_MASK cfbit PCITFCR,22 ; Frame accept error mask. 579RXW_MASK cfbit PCITFCR,21 ; Receive wait condition mask. 580UF_MASK cfbit PCITFCR,20 ; Underflow mask. 581OF_MASK cfbit PCITFCR,19 ; Overflow mask. 582TXW_MASK cfbit PCITFCR,18 ; Transmit wait condition mask. 583PCITFAR equ MBAR_CBUSPCI+$4c; Tx FIFO Alarm Register (32b) 584ALARM cffield PCITFAR,0,12 ; Low level "watermark". 585PCITFRPR equ MBAR_CBUSPCI+$50; Tx FIFO Read Pointer Register (32b) 586READPTR cffield PCITFRPR,0,7 ; Read address presented to the FIFO RAM. 587PCITFWPR equ MBAR_CBUSPCI+$54; Tx FIFO Write Pointer Register (32b) 588WRITEPTR cffield PCITFWPR,0,7 ; Write address presented to the FIFO RAM. 589 590; CommBus FIFO Receive Interface Registers 591 592PCIRPSR equ MBAR_CBUSPCI+$80; Rx Packet Size Register (32b) 593PACKET_SIZE cffield PCIRPSR,16,16 ; Packet Size 594PCIRSAR equ MBAR_CBUSPCI+$84; Rx Start Address Register (32b) 595START_ADD cffield PCIRSAR,0,32 ; Packet Starting Address 596PCIRTCR equ MBAR_CBUSPCI+$88; Rx Transaction Control Register (32b) 597PCI_CMD cffield PCIRTCR,24,4 ; Desired PCI command. 598MAX_RETRIES cffield PCIRTCR,16,8 ; Maximum number of retries to permit "per packet". 599FB cfbit PCIRTCR,12 ; Full burst. 600MAX_BEATS cffield PCIRTCR,8,3 ; Desired number of PCI data beats to attempt on each PCI transaction. 601W cfbit PCIRTCR,4 ; Disable the two high byte enables of the PCI bus 602DI cfbit PCIRTCR,0 ; Disable PCI address incrementing between transactions. 603PCIRER equ MBAR_CBUSPCI+$8c; Rx Enables Register (32b) 604RC cfbit PCIRER,31 ; Reset controller. 605RF cfbit PCIRER,30 ; Reset FIFO. 606FE cfbit PCIRER,29 ; Flush enable. 607CM cfbit PCIRER,28 ; Continuous mode. 608BE cfbit PCIRER,27 ; Bus error enable. 609ME cfbit PCIRER,24 ; Master enable. 610FEE cfbit PCIRER,21 ; FIFO error enable. 611SE cfbit PCIRER,20 ; System error enable. 612RE cfbit PCIRER,19 ; Retry abort enable. 613TAE cfbit PCIRER,18 ; Target abort enable. 614IAE cfbit PCIRER,17 ; Initiator abort enable. 615NE cfbit PCIRER,16 ; Normal termination enable. 616PCIRNAR equ MBAR_CBUSPCI+$90; Rx Next Address Register (32b) 617NEXT_ADDRESS cffield PCIRNAR,0,32 ; Next Address 618PCIRDCR equ MBAR_CBUSPCI+$98; Rx Done Counts Register (32b) 619BYTES_DONE cffield PCIRDCR,16,16 ; Bytes Done 620PACKETS_DONE cffield PCIRDCR,0,16 ; Packets Done 621PCIRSR equ MBAR_CBUSPCI+$9c; Rx Status Register (32b) 622NT cfbit PCIRSR,24 ; Normal Termination. 623BE3 cfbit PCIRSR,23 ; Bus Error type 3. 624BE2 cfbit PCIRSR,22 ; Bus Error type 2. 625BE1 cfbit PCIRSR,21 ; Bus Error type 1. 626FE cfbit PCIRSR,20 ; FIFO Error. 627SE cfbit PCIRSR,19 ; System error. 628RE cfbit PCIRSR,18 ; Retry Error. 629TA cfbit PCIRSR,17 ; Target Abort. 630IA cfbit PCIRSR,16 ; Initiator abort. 631PCIRFDR equ MBAR_CBUSPCI+$c0; Rx FIFO Data Register (32b) 632FIFO_DATA_WORD cffield PCIRFDR,0,32 ; FIFO data port. 633PCIRFSR equ MBAR_CBUSPCI+$c4; Rx FIFO Status Register (32b) 634IP cfbit PCIRFSR,31 ; Illegal Pointer. 635TXW cfbit PCIRFSR,30 ; Transmit Wait Condition. 636FAE cfbit PCIRFSR,23 ; Frame accept error. 637RXW cfbit PCIRFSR,22 ; Receive Wait Condition. 638UF cfbit PCIRFSR,21 ; UnderFlow. 639OF cfbit PCIRFSR,20 ; OverFlow. 640FR cfbit PCIRFSR,19 ; Frame Ready. 641FULL cfbit PCIRFSR,18 ; The FIFO is Full. 642ALARM cfbit PCIRFSR,17 ; The FIFO is at or above the Alarm "watermark". 643EMPTY cfbit PCIRFSR,16 ; The FIFO is empty. 644PCIRFCR equ MBAR_CBUSPCI+$c8; Rx FIFO Control Register (32b) 645WFR cfbit PCIRFCR,29 ; Write frame. 646GR cffield PCIRFCR,24,3 ; Granularity. 647IP_MASK cfbit PCIRFCR,23 ; Illegal Pointer Mask. 648FAE_MASK cfbit PCIRFCR,22 ; Frame accept error mask. 649RXW_MASK cfbit PCIRFCR,21 ; Receive wait condition mask. 650UF_MASK cfbit PCIRFCR,20 ; Underflow mask. 651OF_MASK cfbit PCIRFCR,19 ; Overflow mask. 652TXW_MASK cfbit PCIRFCR,18 ; Transmit wait condition mask. 653PCIRFAR equ MBAR_CBUSPCI+$cc; Rx FIFO Alarm Register (32b) 654ALARM cffield PCIRFAR,0,7 ; Low level watermark, 655PCIRFRPR equ MBAR_CBUSPCI+$d0; Rx FIFO Read Pointer Register (32b) 656READPTR cffield PCIRFRPR,0,7 ; Read address being presented to the FIFO RAM. 657PCIRFWPR equ MBAR_CBUSPCI+$d4; Rx FIFO Write Pointer Register (32b) 658WRITEPTR cffield PCIRFWPR,0,7 ; Write address being presented to the FIFO RAM. 659 660;---------------------------------------------------------------------------- 661; PCI Arbiter 662 663MBAR_PARB equ MBAR+$c00 664 665PACR equ MBAR_PARB+$00 ; PCI Arbiter Control Register 666DS cfbit PACR,31 ; Disable bit for the internal PCI arbiter. 667EXTMINTEN cffield PACR,17,5 ; External master broken interrupt enables. 668INTMINTEN cfbit PACR,16 ; Internal master broken interrupt enable. 669EXTMPRI cffield PACR,1,5 ; External master priority levels. 670INTMPRI cfbit PACR,0 ; Internal master priority level. 671PASR equ MBAR_PARB+$04 ; PCI Arbiter Status Register 672EXTMBK cffield PASR,17,5 ; External master broken. 673ITLMBK cfbit PASR,16 ; Internal master broken. 674 675;---------------------------------------------------------------------------- 676; Security Engine 677 678 if __has_sec 679MBAR_SEC equ MBAR+$20000 680 include "54xxsec.inc" 681 endif 682 683;---------------------------------------------------------------------------- 684; Multi-Channel DMA 685 686MBAR_MDMA equ MBAR+$8000 687 688TASKBAR equ MBAR_MDMA+$000 ; Task Base Address Register (32b) 689CP equ MBAR_MDMA+$004 ; Current Pointer (32b) 690EP equ MBAR_MDMA+$008 ; End Pointer (32b) 691VP equ MBAR_MDMA+$00c ; Variable Pointer (32b) 692PTD equ MBAR_MDMA+$012 ; PTD Control Register (16b) 693PCTL15 cfbit PTD,15 ; Task priority control. 694PCTL14 cfbit PTD,14 ; Bus error control 695PCTL13 cfbit PTD,13 ; Task arbitration control 696PCTL1 cfbit PTD,1 ; Registered request control 697PCTL0 cfbit PTD,0 ; CommBus Prefetch 698DIPR equ MBAR_MDMA+$014 ; DMA Interrupt Pending Register (32b) 699DIMR equ MBAR_MDMA+$018 ; DMA Interrupt Mask Register (32b) 700__N set 0 701 rept 16 702 __decstr __NS,__N 703TCR{__NS} equ MBAR_MDMA+$1c+(__N*2) ; Task Control Register n (16b) 704EN cfbit TCR{__NS},15 ; Task enable. 705V cfbit TCR{__NS},14 ; Initiator number is valid. 706ALWINIT cfbit TCR{__NS},13 ; Decode of the always initiator. 707INITNUM cffield TCR{__NS},8,5 ; Initiator number from task descriptor. 708ASTRT cfbit TCR{__NS},7 ; Auto start. 709HIPRITSKEN cfbit TCR{__NS},6 ; High-priority task enable. 710HLDINITNUM cfbit TCR{__NS},5 ; Hold initiator number. 711ASTSKNUM cffield TCR{__NS},0,4 ; Auto-start task number. 712__N set __N+1 713 endm 714__N set 0 715 rept 32 716 __decstr __NS,__N 717PRIOR{__NS} equ MBAR_MDMA+$3c+__N ; Priority Register n (8b) 718HLD cfbit PRIOR{__NS},7 ; Keep current priority of initiator. 719PRI cffield PRIOR{__NS},0,3 ; Priority level. 720__N set __N+1 721 endm 722IMCR equ MBAR_MDMA+$05c ; InitiatorMuxControl (32b) 723TSKSZ0 equ MBAR_MDMA+$060 ; Task Size Register 0 (32b) 724__N set 0 725 rept 8 726 __decstr __NS,__N 727TASK{__NS}.SRCSZ cffield TSKSZ0,30-(__N*4) ; Source Size 728TASK{__NS}.DSTSZ cffield TSKSZ0,28-(__N*4) ; Dest Size 729__N set __N+1 730 endm 731TSKSZ1 equ MBAR_MDMA+$064 ; Task Size Register 1 (32b) 732 rept 8 733 __decstr __NS,__N 734TASK{__NS}.SRCSZ cffield TSKSZ1,62-(__N*4) ; Source Size 735TASK{__NS}.DSTSZ cffield TSKSZ1,60-(__N*4) ; Dest Size 736__N set __N+1 737 endm 738DBGCOMP1 equ MBAR_MDMA+$070 ; Debug Comparator 1 (32b) 739DBGCOMP2 equ MBAR_MDMA+$074 ; Debug Comparator 2 (32b) 740DBGCTL equ MBAR_MDMA+$078 ; Debug Control (32b) 741BLOCKTASKS cffield DBGCTL,16,16 ; Specify for each of tasks 15-0, whether to block that task with detection of a breakpoint 742AA cfbit DBGCTL,15 ; AutoArm 743B cfbit DBGCTL,14 ; Breakpoint 744COMP1TYPE cffield DBGCTL,11,3 ; Comparator 1 type 745COMP2TYPE cffield DBGCTL,8,3 ; Comparator 2 type 746ANDOR cfbit DBGCTL,7 ; AND/OR 747E cfbit DBGCTL,2 ; Enable external breakpoint. 748I cfbit DBGCTL,1 ; Enable internal breakpoint 749DBGSTAT equ MBAR_MDMA+$07c ; Debug Status (32b) 750I cfbit DBGSTAT,18 ; Interrupt. 751E cfbit DBGSTAT,17 ; External Breakpoint. 752T cfbit DBGSTAT,16 ; Triggered. 753BLOCKED cffield DBGSTAT,0,16 ; Task Blocked. 754PTDDBG equ MBAR_MDMA+$080 ; PTD Debug Registers (32b) 755 756MBAR_EREQ equ MBAR+$d00 757 758__N set 0 759 rept 2 760 __decstr __NS,__N 761EREQBAR{__NS} equ MBAR_EREQ+(__N*16)+0 ; Base Address Register n (32b) 762EREQMASK{__NS} equ MBAR_EREQ+(__N*16)+4 ; Base Address Mask Register n (32b) 763EREQCTRL{__NS} equ MBAR_EREQ+(__N*16)+8 ; Control Reg n (32b) 764MD cffield EREQCTRL{__NS},6,2 ; Mode. 765BSEL cffield EREQCTRL{__NS},4,2 ; Bus Select. 766DACKWID cffield EREQCTRL{__NS},2,2 ; External DMA Acknowledge Width. 767SYNC cfbit EREQCTRL{__NS},1 ; Sync. 768EN cfbit EREQCTRL{__NS},0 ; Enable. 769__N set __N+1 770 endm 771 772;---------------------------------------------------------------------------- 773; CommBUS FIFO Interface 774 775__deffifo macro PR,Base 776{PR}FIFODR equ Base+00 ; FIFO Data Register (32b) 777DATA cffield {PR}FIFODR ; FIFO Data 778{PR}FIFOSR equ Base+04 ; FIFO Status Register (16b) 779IP cfbit {PR}FIFOSR,15 ; Illegal Pointer 780TXW cfbit {PR}FIFOSR,14 ; Transmit Wait Condition 781TYPE cffield {PR}FIFOSR,12,3 ; Frame Boundary Type Indicator 782FRM cffield {PR}FIFOSR,8,4 ; Frame Indicator 783FAE cfbit {PR}FIFOSR,7 ; Frame Accept Error 784RXW cfbit {PR}FIFOSR,6 ; Receive Wait Condition 785UF cfbit {PR}FIFOSR,5 ; FIFO Underflow 786OF cfbit {PR}FIFOSR,4 ; FIFO Overflow 787FRMRDY cfbit {PR}FIFOSR,3 ; Frame Ready 788FU cfbit {PR}FIFOSR,2 ; Full 789ALARM cfbit {PR}FIFOSR,1 ; FIFO Alarm 790EMT cfbit {PR}FIFOSR,0 ; Empty 791{PR}FIFOCR equ Base+08 ; FIFO Control Register (32b) 792SHADOW cfbit {PR}FIFOCR,31 ; Shadow Frame Mode Enable. 793WCTL cfbit {PR}FIFOCR,30 ; Write Control. 794WFR cfbit {PR}FIFOCR,29 ; Write Frame. 795TIMER cfbit {PR}FIFOCR,28 ; Timer Mode Enable. 796FRMEN cfbit {PR}FIFOCR,27 ; Frame Mode Enable. 797GR cffield {PR}FIFOCR,24,3 ; Last Transfer Granularity. 798IP_MASK cfbit {PR}FIFOCR,23 ; Illegal Pointer Mask. 799FAE_MASK cfbit {PR}FIFOCR,22 ; Frame Accept Error Mask. 800RXW_MASK cfbit {PR}FIFOCR,21 ; Receive Wait Condition Mask. 801UF_MASK cfbit {PR}FIFOCR,20 ; Underflow Mask. 802OF_MASK cfbit {PR}FIFOCR,19 ; Overflow Mask. 803TXW_MASK cfbit {PR}FIFOCR,18 ; Masks the Status Register's TXW bit from generating an error. 804COUNTER cffield {PR}FIFOCR,0,16 ; Timer Mode Counter 805{PR}ALARMP equ Base+0e ; Alarm Pointer (16b) 806ALARM cffield {PR}ALARMP,0,12 807{PR}READP equ Base+12 ; FIFO Read Pointer (16b) 808READ cffield {PR}READP,0,12 809{PR}WRITEP equ Base+16 ; FIFO Write Pointer (16b) 810WRITE cffield {PR}WRITEP,0,12 811{PR}LRFP equ Base+1a ; Last Read Frame Pointer (16b) 812{PR}LWFP equ Base+1e ; Last Write Frame Pointer (16b) 813 endm 814 815;---------------------------------------------------------------------------- 816; CommTimer Module 817 818MBAR_CTM equ MBAR+$7f00 819 820__N set 0 821 rept 4 822 __decstr __NS,__N 823CTCR{__NS} equ MBAR_CTM+__N*4 ; Comm Timer Control Register n - Fixed Timer Channel 824I cfbit CTCR{__NS},31 ; Interrupt. 825IM cfbit CTCR{__NS},24 ; Interrupt mask. 826M cfbit CTCR{__NS},23 ; Mode. 827PCT cffield CTCR{__NS},20,3 ; Percent active time select. 828S cffield CTCR{__NS},16,4 ; Clock enable source select. 829CRV cffield CTCR{__NS},0,16 ; Counter reference value. 830__N set __N+1 831 endm 832 rept 4 833 __decstr __NS,__N 834CTCR{__NS} equ MBAR_CTM+__N*4 ; Comm Timer Control Register n - Variable Timer Channel 835S cfbit CTCR{__NS},28 ; Clock enable source select. 836M cfbit CTCR{__NS},27 ; Mode. 837PCT cffield CTCR{__NS},24,3 ; Percent active time select. 838CRV cffield CTCR{__NS},0,24 ; Counter reference value. 839__N set __N+1 840 endm 841 842;---------------------------------------------------------------------------- 843; Programmable Serial Controller(s) 844 845__defpsc macro N,Base 846PSCMR1{N} equ Base+$00 ; PSC Mode register 1 (8b) 847RXRTS cfbit PSCMR1{N},7 ; Receiver request-to-send (UART and SIR modes only). 848RXIRQ cfbit PSCMR1{N},6 ; Receiver interrupt select. 849ERR cfbit PSCMR1{N},5 ; Error mode (UART mode only). 850PM cffield PSCMR1{N},3,2 ; Parity mode (UART mode only). 851PT cfbit PSCMR1{N},2 ; Parity type (UART mode only). 852BC cffield PSCMR1{N},0,2 ; Bits per character (UART mode only). 853PSCMR2{N} equ Base+$00 ; PSC Mode register 2 (8b) 854CM cffield PSCMR2{N},6,2 ; Channel mode. 855TXRTS cfbit PSCMR2{N},5 ; Transmitter ready-to-send (UART and SIR modes). 856TXCTS cfbit PSCMR2{N},4 ; Transmitter clear-to-send (UART and SIR modes). 857SB cffield PSCMR2{N},0,4 ; Stop-bit length control (UART mode only). 858PSCSR{N} equ Base+$04 ; PSC Status Register (16b) 859RB_NEOF cfbit PSCSR{N},15 ; For UART and SIR modes, this field signifies a received break. 860FE_PHYERR cfbit PSCSR{N},14 ; For UART and SIR modes, this field signifies a framing error. 861PE_CRCERR cfbit PSCSR{N},13 ; For UART and SIR modes, this field signifies a parity error. 862OE cfbit PSCSR{N},12 ; This field signifies an overrun error occurred. 863TXEMP_URERR cfbit PSCSR{N},11 ; For UART and SIR modes, this field signifies a transmitter empty. 864TXRDY cfbit PSCSR{N},10 ; This field signifies a Transmitter ready. 865FU cfbit PSCSR{N},9 ; This field signifies that the RxFIFO is full. 866RXRDY cfbit PSCSR{N},8 ; This field signifies a Receiver ready. 867CDE_DEOF cfbit PSCSR{N},7 ; In MIR and FIR mode, this bit signifies Detect End of Frame or the RxFIFO contains EOF. 868ERR cfbit PSCSR{N},6 ; Error bit. 869PSCCSR{N} equ Base+$04 ; PSC Clock Select Register (8b) 870RCSEL cffield PSCCSR{N},4,4 ; In UART or SIR mode, this is the receiver clock select. 871TCSEL cffield PSCCSR{N},0,4 ; In UART or SIR mode, this is the transmitter clock select. 872PSCCR{N} equ Base+$08 ; PSC Command Register (8b) 873MISC cffield PSCCR{N},4,3 ; Misc Commands 874TXC cffield PSCCR{N},2,2 ; Receiver Command 875RXC cffield PSCCR{N},0,2 ; Transmitter Command 876PSCRB{N} equ Base+$0c ; PSC Receive Buffer (32b) 877RB cffield PSCRB{N},0,32 ; Received data. 878PSCTB{N} equ Base+$0c ; PSC Transmit Buffer (32b) 879TB cffield PSCTB{N},0,32 ; Transmitted data. 880PSCIPCR{N} equ Base+$10 ; PSC Input Port Change Register (8b) 881SYNC cfbit PSCIPCR{N},7 ; For modem modes, this bit signifies Sync is detected or not. 882D_CTS cfbit PSCIPCR{N},4 ; Delta CTS 883CTS cfbit PSCIPCR{N},0 ; Current state of PSCnCTS port. 884PSCACR{N} equ Base+$10 ; PSC Auxiliary Control Register (8b) 885IEC0 cfbit PSCACR{N},0 ; Interrupt enable control for D_CTS. 886PSCISR{N} equ Base+$14 ; PSC Interrupt Status Register (16b) 887IPC cffield PSCISR{N},15 ; Input port change. 888DB cffield PSCISR{N},10 ; In UART / SIR, this is a Delta break. 889RXRDY_FU cffield PSCISR{N},9 ; RxFIFO over threshold/Receive data is ready. 890TXRDY cffield PSCISR{N},8 ; Transmitter ready 891DEOF cffield PSCISR{N},7 ; For SIR and MIR modes, this bit signifies detect end of frame or the RxFIFO contains EOF. 892ERR cffield PSCISR{N},6 ; OR of all errors status including FIFO errors. 893PSCIMR{N} equ Base+$14 ; PSC Interrupt Mask Register (16b) 894IPC cffield PSCIMR{N},15 ; Input port change. 895DB cffield PSCIMR{N},10 ; In UART / SIR, this is a Delta break. 896RXRDY_FU cffield PSCIMR{N},9 ; RxFIFO over threshold/Receive data is ready. 897TXRDY cffield PSCIMR{N},8 ; Transmitter ready 898DEOF cffield PSCIMR{N},7 ; For SIR and MIR modes, this bit signifies detect end of frame or the RxFIFO contains EOF. 899ERR cffield PSCIMR{N},6 ; OR of all errors status including FIFO errors. 900PSCCTUR{N} equ Base+$18 ; PSC Counter Timer Upper Register (8b) 901PSCCTLR{N} equ Base+$18 ; PSC Counter Timer Lower Register (8b) 902PSCIP{N} equ Base+$34 ; PSC Input Port (8b) 903LPWR_B cfbit PSCIP{N},7 ; In AC97 mode, this bit signifies the low power mode. 904TGL cfbit PSCIP{N},6 ; In AC97 and modem modes, this bit signifies test usage. 905CTS cfbit PSCIP{N},0 ; Current state of the PSCnCTS input 906PSCOPSET{N} equ Base+$38 ; PSC Output Port Set (8b) 907RTS cfbit PSCOPSET{N},0 ; Assert /PSCnRTS output 908PSCOPRESET{N} equ Base+$3c ; PSC Output Port Reset (8b) 909RTS cfbit PSCOPRESET{N},0 ; Negate /PSCnRTS output 910PSCSICR{N} equ Base+$40 ; PSC PSC / IrDA Control Register (8b) 911ACRB cfbit PSCSICR{N},7 ; In AC97 mode, this bit signifies Cold Reset to the transceiver in PSC. 912AWR cfbit PSCSICR{N},6 ; In AC97 mode, this bit signifies Warm Reset (to the transceiver in PSC and AC97 CODEC). 913DTS1 cfbit PSCSICR{N},5 ; In modem modes, this bit signifies delay of time slot 1. 914SHDIR cfbit PSCSICR{N},4 ; In modem modes, this bit signifies Shift Direction. 915SIM cffield PSCSICR{N},0,3 ; PSC/IrDA operation mode. 916PSCIRCR1{N} equ Base+$44 ; PSC IrDA Control Register 1 (8b) 917FD cfbit PSCIRCR1{N},2 ; In MIR, FIR, SIR, and modem modes, this bit signifies full duplex enable. 918SIPEN cfbit PSCIRCR1{N},1 ; In MIR, FIR, and modem mode, this bit signifies sends SIP enable after every frame. 919SPUL cfbit PSCIRCR1{N},0 ; In SIR mode, this bit signifies SIR pulse width. 920PSCIRCR2{N} equ Base+$48 ; PSC IrDA Control Register 2 (8b) 921SIPREQ cfbit PSCIRCR2{N},2 ; In MIR and FIR mode, this bit signifies request to send SIP. 922ABORT cfbit PSCIRCR2{N},1 ; In MIR and FIR mode, this bit signifies abort output. 923NXTEOF cfbit PSCIRCR2{N},0 ; In MIR and FIR mode, this bit signifies next is the last byte. 924PSCIRSDR{N} equ Base+$4c ; PSC IrDA SIR Divide Register (8b) 925IRSTIM cffield PSCIRSDR{N},0,8 ; In SIR mode, this field signifies the timer counter value for 1.6 us pulse. 926PSCIRMDR{N} equ Base+$50 ; PSC IrDA MIR Divide Register (8b) 927FREQ cfbit PSCIRMDR{N},7 ; In MIR mode, this bit signifies 0.576 Mbps mode. 928M_FDIV cffield PSCIRMDR{N},0,7 ; In MIR mode, this bit signifies clock divide ratio. 929PSCIRFDR{N} equ Base+$54 ; PSC IrDA FIR Divide Register (8b) 930F_FDIV cffield PSCIRFDR{N},0,4 ; In FIR mode, this field signifies clock divide ratio. 931PSCRFCNT{N} equ Base+$58 ; PSC RxFIFO Counter Register (16b) 932CNT cffield PSCRFCNT{N},0,9 ; Number of bytes in the FIFO 933PSCTFCNT{N} equ Base+$5c ; PSC TxFIFO Counter Register (16b) 934CNT cffield PSCTFCNT{N},0,9 ; Number of bytes in the FIFO 935PSCRFDR{N} equ Base+$60 ; PSC RxFIFO Data Register (32b) 936PSCRFSR{N} equ Base+$64 ; PSC RxFIFO Status Register (16b) 937PSCRFCR{N} equ Base+$68 ; PSC RxFIFO Control Register (16b) 938PSCRFAR{N} equ Base+$6e ; PSC RxFIFO Alarm Register (16b) 939PSCRFRP{N} equ Base+$72 ; PSC RxFIFO Read Pointer (16b) 940PSCRFWP{N} equ Base+$76 ; PSC RxFIFO Write Pointer (16b) 941PSCRLRFP{N} equ Base+$7a ; PSC RxFIFO Last Read Frame Pointer (16b) 942PSCRLWFP{N} equ Base+$7e ; PSC RxFIFO Last Write Frame Pointer (16b) 943PSCTFDR{N} equ Base+$80 ; PSC TxFIFO Data Register (32b) 944PSCTFSR{N} equ Base+$84 ; PSC TxFIFO Status Register (16b) 945PSCTFCR{N} equ Base+$88 ; PSC TxFIFO Control Register (32b) 946PSCTFAR{N} equ Base+$8e ; PSC TxFIFO Alarm Register (16b) 947PSCTFRP{N} equ Base+$92 ; PSC TxFIFO Read Pointer (16b) 948PSCTFWP{N} equ Base+$96 ; PSC TxFIFO Write Pointer (16b) 949PSCTLRFP{N} equ Base+$9a ; PSC TxFIFO Last Read Frame Pointer (16b) 950PSCTLWFP{N} equ Base+$9e ; PSC TxFIFO Last Write Frame Pointer (16b) 951 irp Reg,PSCRFSR{N},PSCTFSR{N} 952IP cfbit Reg,15 ; Illegal pointer. 953TXW cfbit Reg,14 ; Transmit wait condition. 954TAG cffield Reg,12,2 ; Holds the last read tag information. 955FRM cffield Reg,8,4 ; Frame indicator. 956FAE cfbit Reg,7 ; Frame accept error. 957RXW cfbit Reg,6 ; Receive wait condition. 958UF cfbit Reg,5 ; FIFO underflow. 959OF cfbit Reg,4 ; FIFO Overflow. 960FRMRDY cfbit Reg,3 ; Frame ready. 961FU cfbit Reg,2 ; FIFO full alarm. 962ALARM cfbit Reg,1 ; Alarm. 963EMT cfbit Reg,0 ; FIFO empty. 964 endm 965 irp Reg,PSCRFCR{N},PSCTFCR{N} 966WFR cfbit Reg,29 ; Write frame. 967TIMER cfbit Reg,28 ; Timer mode enable. 968FRMEN cfbit Reg,27 ; Frame mode enable 969GR cffield Reg,24,3 ; Granularity 970IP_MSK cfbit Reg,23 ; Illegal pointer mask. 971FAE_MSK cfbit Reg,22 ; Frame accept error mask. 972RXW_MSK cfbit Reg,21 ; Receive wait condition mask. 973UF_MSK cfbit Reg,20 ; FIFO underflow mask. 974OF_MSK cfbit Reg,19 ; FIFO overflow mask. 975TXW_MSK cfbit Reg,18 ; Transmit wait condition mask. 976CNTR cffield Reg,0,16 ; Timer mode counter. 977 endm 978 irp Reg,PSCRFAR{N},PSCTFAR{N} 979ALARM cffield Reg,0,9 ; Alarm pointer. 980 endm 981 irp Reg,PSCRFRP{N},PSCTFRP{N} 982READ cffield Reg,0,9 ; Read pointer. 983 endm 984 irp Reg,PSCRFWP{N},PSCTFWP{N} 985WRITE cffield Reg,0,9 ; Write pointer. 986 endm 987 irp Reg,PSCRLRFP{N},PSCTLRFP{N} 988LRFP cffield Reg,0,9 ; Last read frame pointer. 989 endm 990 irp Reg,PSCRLWFP{N},PSCTLWFP{N} 991LWFP cffield Reg,0,9 ; Last write frame pointer. 992 endm 993 endm 994 995 __defpsc "0",MBAR+$8600 996 __defpsc "1",MBAR+$8700 997 __defpsc "2",MBAR+$8800 998 __defpsc "3",MBAR+$8900 999 1000;---------------------------------------------------------------------------- 1001; DMA Serial Peripheral Interface (similar to 52277, different names) 1002 1003MBAR_DSPI equ MBAR+$8a00 1004 1005DMCR equ MBAR_DSPI+$000 ; DSPI module configuration register (32b) 1006MSTR cfbit DMCR,31 ; Master/slave mode select. 1007CSCK cfbit DMCR,30 ; Continuous DSPISCK enable. 1008DCONF cffield DMCR,28,2 ; DSPI configuration. 1009FRZ cfbit DMCR,27 ; Freeze. 1010MTFE cfbit DMCR,26 ; Modified timing format enable. 1011PCSSE cfbit DMCR,25 ; Peripheral chip select strobe enable. 1012ROOE cfbit DMCR,24 ; Receive FIFO overflow overwrite enable. 1013CSIS5 cfbit DMCR,21 ; Chip select n inactive state. 1014CSIS3 cfbit DMCR,19 1015CSIS2 cfbit DMCR,18 1016CSIS0 cfbit DMCR,16 1017DTXF cfbit DMCR,13 ; Disable transmit FIFO. 1018DRXF cfbit DMCR,12 ; Disable receive FIFO. 1019CTXF cfbit DMCR,11 ; Clear TX FIFO. 1020CRXF cfbit DMCR,10 ; Clear RX FIFO. 1021SMPL_PT cffield DMCR,8,2 ; Sample point. 1022HALT cfbit DMCR,0 ; Halt. 1023DTCR equ MBAR_DSPI+$008 ; DSPI transfer count register (32b) 1024SPI_TCNT cffield DTCR,16,16 ; SPI transfer counter. 1025__N set 0 1026 rept 8 1027 __decstr __NS,__N 1028DCTAR{"\{__NS}"} equ MBAR_DSPI+$00C+(__N*4) ; DSPI clock and transfer attributes registers (8*32b) 1029TRSZ cffield DCTAR{"\{__NS}"},27,4 ; Transfer size. 1030CPOL cfbit DCTAR{"\{__NS}"},26 ; Clock polarity. 1031CPHA cfbit DCTAR{"\{__NS}"},25 ; Clock phase. 1032LSBFE cfbit DCTAR{"\{__NS}"},24 ; LSB first enable. 1033PCSSCK cffield DCTAR{"\{__NS}"},22,2 ; CS to SCK delay prescaler. 1034PASC cffield DCTAR{"\{__NS}"},20,2 ; After SCK delay prescaler. 1035PDT cffield DCTAR{"\{__NS}"},18,2 ; Delay after transfer prescaler. 1036PBR cffield DCTAR{"\{__NS}"},16,2 ; Baud rate prescaler. 1037CSSCK cffield DCTAR{"\{__NS}"},12,4 ; PCS to SCK delay scaler. 1038ASC cffield DCTAR{"\{__NS}"},8,4 ; After SCK delay scaler. 1039DT cffield DCTAR{"\{__NS}"},4,4 ; Delay after transfer scaler. 1040BR cffield DCTAR{"\{__NS}"},0,4 ; Baud rate scaler. 1041__N set __N+1 1042 endm 1043DSR equ MBAR_DSPI+$02C ; DSPI status register (32b) 1044TCF cfbit DSR,31 ; Transfer complete flag. 1045TXRXS cfbit DSR,30 ; TX and RX status. 1046EOQF cfbit DSR,28 ; End of queue flag. 1047TFUF cfbit DSR,27 ; Transmit FIFO underflow flag. 1048TFFF cfbit DSR,25 ; Transmit FIFO fill flag. 1049RFOF cfbit DSR,19 ; Receive FIFO overflow flag. 1050RFDF cfbit DSR,17 ; Receive FIFO drain flag. 1051TXCTR cffield DSR,12,4 ; TX FIFO counter. 1052TXNXTPTR cffield DSR,8,4 ; Transmit next pointer. 1053RXCTR cffield DSR,4,4 ; RX FIFO counter. 1054POPNXTPTR cffield DSR,0,4 ; Pop next pointer. 1055DIRSR equ MBAR_DSPI+$030 ; DSPI DMA/interrupt request select and enable register (32b) 1056TCFE cfbit DIRSR,31 ; Transmission complete interrupt enable. 1057EOQFE cfbit DIRSR,28 ; End of queue flag interrupt enable. 1058TFUFE cfbit DIRSR,27 ; Transmit FIFO underflow interrupt enable. 1059TFFFE cfbit DIRSR,25 ; Transmit FIFO fill interrupt enable. 1060TFFFS cfbit DIRSR,24 ; Transmit FIFO fill DMA or interrupt request select. 1061RFOFRE cfbit DIRSR,19 ; Receive FIFO overflow interrupt enable. 1062RFDFE cfbit DIRSR,17 ; Receive FIFO drain interrupt enable. 1063RFDFS cfbit DIRSR,16 ; Receive FIFO drain DMA or interrupt request select. 1064DTFR equ MBAR_DSPI+$034 ; DSPI TX FIFO register (32b) 1065CONT cfbit DTFR,31 ; Continuous peripheral chip select enable. 1066CTAS cffield DTFR,28,3 ; Clock and transfer attributes select. 1067EOQ cfbit DTFR,27 ; End of queue. 1068CTCNT cfbit DTFR,26 ; Clear SPI_TCNT. 1069CS5 cfbit DTFR,21 ; Cip select n. 1070CS3 cfbit DTFR,19 1071CS2 cfbit DTFR,18 1072CS0 cfbit DTFR,16 1073TXDATA cffield DTFR,0,16 ; Transmit data. 1074DRFR equ MBAR_DSPI+$038 ; DSPI RX FIFO register (32b) 1075RXDATA cffield DRFR,0,16 ; Received data. 1076__DSPI_TXRX macro 1077DTFDR{"\{__NS}"} equ MBAR_DSPI+$03C+(__N*4) ; DSPI Tx FIFO Debug Registers (32b) 1078TXCMD cffield DTFDR{"\{__NS}"},16,16 ; Transmit command. 1079TXDATA cffield DTFDR{"\{__NS}"},0,16 ; Transmit data. 1080DRFDR{"\{__NS}"} equ MBAR_DSPI+$07C+(__N*4) ; DSPI Rx FIFO Debug Registers (32b) 1081RXDATA cffield DRFDR{"\{__NS}"},0,16 ; Receive data. 1082 endm 1083 __enumregs __DSPI_TXRX,0,15 1084 1085;---------------------------------------------------------------------------- 1086; I2C 1087 1088MBAR_I2C equ MBAR+$8f00 1089 include "52xxi2c.inc" 1090 1091I2ICR equ MBAR_I2C+$20 ; I2C Interrupt Control Register (8b) 1092BNBE cfbit I2ICR,3 ; Permits I2C module to generate an interrupt when the bus is NOT busy. 1093TE cfbit I2ICR,2 ; Routes the interrupt for the I2C module to the TX requestor at the multichannel DMA. 1094RE cfbit I2ICR,1 ; Routes the interrupt for the I2C module to the RX requestor at the multichannel DMA. 1095IE cfbit I2ICR,0 ; Routes the interrupt for the I2C module to the CPU. 1096 1097;---------------------------------------------------------------------------- 1098; USB 2.0 1099 1100 if __has_usb 1101MBAR_USB2 equ MBAR+$b000 1102 include "54xxusb2.inc" 1103 endif 1104 1105;---------------------------------------------------------------------------- 1106; FEC 1107 1108 include "54xxfec.inc" 1109 __def54fec "FEC0.",MBAR+$9000 1110 if __has_fec1 1111 __def54fec "FEC1.",MBAR+$9800 1112 endif 1113 1114;---------------------------------------------------------------------------- 1115 1116 restore ; re-enable listing 1117 1118 endif ; __mcf547xinc 1119