1 ifndef reg29kinc ; avoid multiple inclusion 2reg29kinc equ 1 3 4 save 5 listing off ; no listing over this file 6 7;**************************************************************************** 8;* * 9;* AS 1.42 - File REG29K.INC * 10;* * 11;* Contains Address Definitions for 2924x Processors * 12;* * 13;**************************************************************************** 14 15 if (MOMCPU<>168512)&&(MOMCPU<>168515)&&(MOMCPU<>168517) 16 fatal "wrong target selected: only AM29240, AM29243 oder AM29245 supported" 17 endif 18 19 20 if MOMPASS=1 21 message "AM2924x SFR Definitions (C) 1995 Alfred Arnold" 22 message "including AM\{MOMCPU} SFRs" 23 endif 24 25;---------------------------------------------------------------------------- 26; Register Base 27 28RegBase equ 0x80000000 29 30;---------------------------------------------------------------------------- 31; ROM Controller 32 33RMCT equ RegBase+0x00 ; ROM Control Register 34RMCF equ RegBase+0x04 ; ROM Configuration Register 35 36;---------------------------------------------------------------------------- 37; DRAM Controller 38 39DRCT equ RegBase+0x08 ; DRAM Control Register 40DRCF equ RegBase+0x0c ; DRAM Configuration Register 41 42;---------------------------------------------------------------------------- 43; PIA 44 45PICT0 equ RegBase+0x20 ; PIA Control Register 0 46PICT1 equ RegBase+0x24 ; PIA Control Register 1 47 48;---------------------------------------------------------------------------- 49; DMA Controller 50 51DMCT0 equ RegBase+0x30 ; Channel 0 Control Register 52DMAD0 equ RegBase+0x34 ; Channel 0 Address Register 53TAD0 equ RegBase+0x70 ; Channel 0 Queued Address Register 54DMCN0 equ RegBase+0x38 ; Channel 0 Count Register 55TCN0 equ RegBase+0x3c ; Channel 0 Queued Count Register 56DMCT1 equ RegBase+0x40 ; Channel 1 Control Register 57DMAD1 equ RegBase+0x44 ; Channel 1 Address Register 58TAD1 equ RegBase+0x74 ; Channel 1 Queued-Address Register 59DMCN1 equ RegBase+0x48 ; Channel 1 Count Register 60TCN1 equ RegBase+0x4c ; Channel 1 Queued-Count Register 61 if MOMCPU<>0x29245 62DMCT2 equ RegBase+0x50 ; Channel 2 Control Register 63DMAD2 equ RegBase+0x54 ; Channel 2 Address Register 64TAD2 equ RegBase+0x78 ; Channel 2 Queued-Address Register 65DMCN2 equ RegBase+0x58 ; Channel 2 Count Register 66TCN2 equ RegBase+0x5c ; Channel 2 Queued-Count Register 67DMCT3 equ RegBase+0x60 ; Channel 3 Control Register 68DMAD3 equ RegBase+0x64 ; Channel 3 Address Register 69TAD3 equ RegBase+0x7c ; Channel 3 Queued-Address Register 70DMCN3 equ RegBase+0x68 ; Channel 3 Count Register 71TCN3 equ RegBase+0x6c ; Channel 3 Queued-Count Register 72 endif 73 74;---------------------------------------------------------------------------- 75; PIO 76 77POCT equ RegBase+0xd0 ; PIO Control Register 78PIN equ RegBase+0xd4 ; PIO Input Register 79POUT equ RegBase+0xd8 ; PIO Output Register 80POEN equ RegBase+0xdc ; PIO Direction Control 81 82;---------------------------------------------------------------------------- 83; Parallelport 84 85PPCT equ RegBase+0xc0 ; Control Register 86PPST equ RegBase+0xc8 ; Status Register 87PPDT equ RegBase+0xc4 ; Data Register 88 89;---------------------------------------------------------------------------- 90; Serial Ports 91 92SPCTA equ RegBase+0x80 ; Channel A Control Register 93SPSTA equ RegBase+0x84 ; Channel A Status Register 94SPTHA equ RegBase+0x88 ; Channel A Transmit Register 95SPRBA equ RegBase+0x8c ; Channel A Receive Register 96BAUDA equ RegBase+0x90 ; Channel A Baud Rate Register 97 if MOMCPU<>0x29245 98SPCTB equ RegBase+0xa0 ; Channel B Control Register 99SPSTB equ RegBase+0xa4 ; Channel B Status Register 100SPTHB equ RegBase+0xa8 ; Channel B Transmit Register 101SPRBB equ RegBase+0xac ; Channel B Receive Register 102BAUDB equ RegBase+0xb0 ; Channel B Baud Rate Register 103 endif 104 105;---------------------------------------------------------------------------- 106; Video Interface 107 108 if MOMCPU<>0x29243 109VCT equ RegBase+0xe0 ; Control Register 110TOP equ RegBase+0xe4 ; Line Number Upper Border 111SIDE equ RegBase+0xe8 ; Column Number Left/Right Border 112VDT equ RegBase+0xec ; Data Register 113 endif 114 115;---------------------------------------------------------------------------- 116; Interrupt Control 117 118ICT equ RegBase+0x28 ; Control Register 119IMASK equ RegBase+0x2c ; Mask Register 120 121;---------------------------------------------------------------------------- 122 123 endif 124 125 restore 126