1 ifndef __regavrinc ; avoid multiple inclusion 2__regavrinc equ 1 3 4 save 5 listing off ; no listing over this file 6 7;**************************************************************************** 8;* * 9;* AS 1.42 - Datei REGAVROLD.INC * 10;* * 11;* Contains SFR and Bit Definitions for AVR Processors * 12;* OUTDATED VERSION - PLEASE SWITCH TO NEW FILE IF POSSIBLE * 13;* * 14;**************************************************************************** 15 16; Set internal CPU code and memory addresses in one step 17 18 switch MOMCPUNAME 19 case "AT90S1200" 20__cpucode equ 0x011200 21eeend equ 63 ; End Address EEPROM 22iramend equ 95,data ; End Address SRAM 23iromend label 1023 ; End Address EPROM 24 case "AT90S2313" 25__cpucode equ 0x012313 26eeend equ 127 27iramend equ 0xdf,data 28iromend label 2047 29 case "AT90S4414" 30__cpucode equ 0x014414 31eeend equ 255 32iramend equ 0x15f,data 33iromend label 4095 34 case "AT90S8515" 35__cpucode equ 0x018515 36eeend equ 511 37iramend equ 0x25f,data 38iromend label 8191 39 case "ATMEGA8" 40__cpucode equ 0x020008 41eeend equ 511 42iramend equ 0x45f,data 43iromend label 8191 44 case "ATMEGA16" 45__cpucode equ 0x020010 46eeend equ 511 47iramend equ 0x45f,data 48iromend label 16383 49 elsecase 50 fatal "wrong target selected: only AT90S1200, AT90S2313, AT90S4414, AT90S8515, ATMEGA8, or ATMEGA16 supported" 51 endcase 52 53ismega function code,(code>>16)=2 54 55 if MOMPASS=1 56 message "Atmel AVR SFR Definitions (C) 1996,2002 Alfred Arnold" 57 endif 58 59;---------------------------------------------------------------------------- 60; Constant Memory Addresses 61 62eestart equ 0 ; Start Address Internal EEPROM 63iram equ 96,data ; Start Address Internal SRAM 64 ; (behind mapped I/O) 65irom label 0 ; Start Address Internal EPROM 66 67;---------------------------------------------------------------------------- 68; Prozessorkern 69 70sreg port 0x3f ; Status Register: 71c equ 0 ; Carry 72z equ 1 ; Zero Result 73n equ 2 ; Negative Result 74v equ 3 ; Twos Complement Overflow 75s equ 4 ; Sign 76h equ 5 ; Half Carry 77t equ 6 ; Bit Storage 78i equ 7 ; Globale Interrupt Enable 79 80; Size of stack pointer depends on size of Internal data space 81; (if present at all) 82 83 if __cpucode>=0x012313 84spl equ 0x3d ; Stack Pointer (LSB) 85 if iramend>=256 86sph equ 0x3e ; (MSB) 87 endif 88 endif 89 90;---------------------------------------------------------------------------- 91; Chip Configuration 92 93mcucr port 0x35 ; CPU Control: 94isc00 equ 0 ; INT0 Edge Selection 95isc01 equ 1 ; INT0 Edge/Level Trigger 96 if __cpucode>=0x012313 97isc10 equ 2 ; INT1 Edge Selection 98isc11 equ 3 ; INT1 Edge/Level Trigger 99 endif 100 if ismega(__cpucode) 101; Note: for the Mega16, bits 6 & 7 are interchanged, I guess that's an 102; error in the data sheet... 103se equ 7 ; Sleep Enable 104sm2 equ 6 ; Sleep Mode Select 105sm1 equ 5 106sm0 equ 4 107 else ; !ismega 108sm equ 4 ; Select Idle/PowerDdown Mode 109se equ 5 ; Enable Sleep Mode 110 if __cpucode>=0x014414 111srw equ 6 ; Wait State Selection External SRAM 112sre equ 7 ; External External SRAM 113 endif 114 endif 115 116 if ismega(__cpucode) 117osccal port 0x31 ; Oscillator Calibration 118 119mcucsr port 0x34 120 if __cpucode>=0x020010 121jtd equ 7 ; JTAG Reset Flag 122isc2 equ 6 ; Interrupt Sense Control 2 123 endif 124wdrf equ 3 ; Watchdog Reset Occured 125borf equ 2 ; Brown Out Occured 126extrf equ 1 ; External Reset Occured 127porf equ 0 ; Power On Reset Occured 128 129spmcr port 0x37 ; Store Program Memory Control Register 130spmie equ 7 ; Interrupt Enable 131rwwsb equ 6 ; Read-while-Write Section Busy 132rwwsre equ 4 ; Read-while-Write Section Read Enable 133blbset equ 3 ; Boot Lock Bit Set 134pgwrt equ 2 ; Page Write 135pgers equ 1 ; Page Erase 136spmen equ 0 ; Store Program Memory Enable 137 endif 138 139;---------------------------------------------------------------------------- 140; Interrupt-Steuerung 141 142 if ismega(__cpucode) 143gicr port 0x3b 144ivce equ 0 ; Interrupt Vector Change Enable 145ivsel equ 1 ; Interrupt Vector Select 146int0 equ 6 ; Enable External Interrupt 0 147int1 equ 7 ; Enable External Interrupt 1 148 if __cpucode>=0x020010 149int2 equ 5 ; Enable External Interrupt 2 150 endif 151 elseif 152gimsk port 0x3b ; Global Interrupt Mask: 153int0 equ 6 ; External Interrupt 0 154 if __cpucode>=0x012313 155int1 equ 7 ; External Interrupt 1 156 endif 157 endif 158 159 if __cpucode>=0x012313 160gifr port 0x3a ; Global Interrupt Flags 161intf0 equ 6 ; External Interrupt 0 162intf1 equ 7 ; External Interrupt 1 163 ifdef int2 164intf2 equ int2 ; External Interrupt 2 165 endif 166 endif 167 168; who the heck decided to rearrange all bits for the Megas? 169 170timsk port 0x39 ; Timer Interrupt Mask: 171 if ismega(__cpucode) 172toie0 equ 0 173 elseif 174toie0 equ 1 ; Timer 0 Overflow 175 endif 176 if __cpucode>=0x012313 177 if __cpucode>=0x014414 178 if ismega(__cpucode) 179ocie1b equ 3 ; Timer 1 Vergleich B 180 elseif 181ocie1b equ 5 ; Timer 1 Vergleich B 182 endif 183 endif 184 if ismega(__cpucode) 185toie1 equ 2 186ticie1 equ 5 187toie2 equ 6 188ocie2 equ 7 189ocie1a equ 4 190 elseif 191toie1 equ 7 ; Timer 1 Overflow 192ticie1 equ 3 ; Timer 1 Capture 193ocie1a equ 6 ; Timer 1 Compare 194 endif 195 endif 196 197tifr port 0x38 ; Timer Interrupt Flags 198tov0 equ toie0 ; Timer 0 Overflow 199 if __cpucode>=0x012313 200ocf1a equ ocie1a ; Timer 1 Compare A 201tov1 equ toie1 ; Timer 1 Overflow 202icf1 equ ticie1 ; Timer 1 Capture 203 endif 204 if __cpucode>=0x014414 205ocf1b equ ocie1b ; Timer 1 Compare 206 endif 207 if ismega(__cpucode) 208tov2 equ toie2 209ocf2 equ ocie2 210 endif 211 212 213;---------------------------------------------------------------------------- 214; Parallel Ports 215 216 if ismega(__cpucode) 217sfior equ 0x30 218psr10 equ 0 ; T0/T1 Prescaler Reset 219psr2 equ 1 ; ditto T2 220pud equ 2 ; Pullup Disable 221acme equ 3 ; Analog Comparator Multiplexer Enable 222adhsm equ 4 ; ADC High Speed Mode 223 if __cpucode>=0x020010 224adts0 equ 5 225adts1 equ 6 226adts2 equ 7 227 endif 228 endif 229 230 if (__cpucode=0x014414)||(__cpucode=0x018515)||(__cpucode=0x020010) 231porta port 0x1b ; Port A Data Register 232ddra port 0x1a ; Port A Data Direction Register 233pina port 0x19 ; Port A Read Register 234 endif 235 236portb port 0x18 ; Port B Data Register 237ddrb port 0x17 ; Port B Data Direction Register 238pinb port 0x16 ; Port B Read Register 239 240 if __cpucode>=0x014414 241portc port 0x15 ; Port C Data Register 242ddrc port 0x14 ; Port C Data Direction Register 243pinc port 0x13 ; Port C Read Register 244 endif 245 246portd port 0x12 ; Port D Data Register 247ddrd port 0x11 ; Port D Data Direction Register 248pind port 0x10 ; Port D Read Register 249 250;---------------------------------------------------------------------------- 251; Timer 252 253tccr0 port 0x33 ; Timer 0 Control Register: 254cs00 equ 0 ; Prescaler Setting 255cs01 equ 1 256cs02 equ 2 257 if __cpucode=0x020010 258wgm01 equ 3 ; Waveform Generation Mode 259wgm00 equ 6 260com00 equ 4 ; Compare/Match Output Mode 261com01 equ 5 262foc0 equ 7 ; Force Output Compare 263 endif 264 265tcnt0 port 0x32 ; Timer 0 Count Register 266 267ocr0 port 0x3c 268 269 if __cpucode>=0x012313 270tccr1a port 0x2f ; Timer 1 Steuerregister A: 271pwm10 equ 0 ; PWM Mode 272wgm10 equ pwm10 273pwm11 equ 1 274wgm11 equ pwm11 275com1a0 equ 6 ; Compare Mode A 276com1a1 equ 7 277 if __cpucode>=0x014414 278com1b0 equ 4 ; Compare Mode B 279com1b1 equ 5 280 endif 281 if ismega(__cpucode) 282foc1b equ 2 283foc1a equ 3 284 endif 285 286tccr1b port 0x2e ; Timer 1 Control Register B: 287cs10 equ 0 ; Prescale setting 288cs11 equ 1 289cs12 equ 2 290ctc1 equ 3 ; Reset after Equality ? 291wgm12 equ ctc1 292 if ismega(__cpucode) 293wgm13 equ 4 294 endif 295ices1 equ 6 ; Capture Edge Selection 296icnc1 equ 7 ; Capture Noise Filter 297 298tcnt1l port 0x2c ; Timer 1 Count Register (LSB) 299tcnt1h port 0x2d ; (MSB) 300 301 if __cpucode>=0x014414 302ocr1al port 0x2a ; Timer 1 Compare Register A (LSB) 303ocr1ah port 0x2b ; (MSB) 304ocr1bl port 0x28 ; Timer 1 Compare Register B (LSB) 305ocr1bh port 0x29 ; (MSB) 306 elseif 307ocr1l port 0x2a ; Timer 1 Compare Register (LSB) 308ocr1h port 0x2b ; (MSB) 309 endif 310 311 if ismega(__cpucode) 312icr1l port 0x26 313icr1h port 0x27 314 elseif 315icr1l port 0x24 ; Timer 1 Capture Value (LSB) 316icr1h port 0x25 ; (MSB) 317 endif 318 endif 319 320 if ismega(__cpucode) 321tccr2 port 0x26 ; Timer 2 Control Register 322cs20 equ 0 ; Prescaler 323cs21 equ 1 324cs22 equ 2 325wgm21 equ 3 326com20 equ 4 327com21 equ 5 328wgm20 equ 6 329foc2 equ 7 330 331tcnt2 port 0x24 ; Timer Value 332ocr2 port 0x23 ; Output Compare Value 333 334assr port 0x22 ; Asynchronous Status Register 335as2 equ 3 ; Asynchronous Timer 2 336tcn2ub equ 2 ; Timer/Counter 2 Update Busy 337ocr2ub equ 1 ; Output Compare Register 2 Update Busy 338tcr2ub equ 0 ; Timer/Counter Control Register 2 Update Busy 339 endif 340 341;---------------------------------------------------------------------------- 342; Watchdog 343 344wdtcr port 0x21 ; Watchdog-Control Register: 345wdp0 equ 0 ; Prescaler 346wdp1 equ 1 347wdp2 equ 2 348wde equ 3 ; Enable 349 if __cpucode=0x010008 350wdce equ 4 ; Watchdog Change Enable 351 elseif __cpucode>=0x012313 352wdttoe equ 4 ; Needed for Disable 353 endif 354 355;---------------------------------------------------------------------------- 356; serielle Ports 357 358 if __cpucode>=0x012312 359udr port 0x0c ; Data Register UART 360 361usr port 0x0b ; Status Register UART: 362ucsra port usr 363 if ismega(__cpucode) 364mpcm equ 0 ; Multiprocessor Communication Mode 365u2x equ 1 ; Double Speed 366pe equ 2 ; Parity Error 367 endif 368or equ 3 ; Receiver Overflow 369dor equ or 370fe equ 4 ; Framing Error 371udre equ 5 ; Data Register Empty 372txc equ 6 ; Transmission Complete 373rxc equ 7 ; Reception Complete 374 375ucr port 0x0a ; UART Control Register: 376ucsrb port ucr 377txb8 equ 0 ; Transmit Bit 8 378rxb8 equ 1 ; Receive Bit 8 379chr9 equ 2 ; Enable 9 Bit Data Values 380ucsz2 equ chr9 381txen equ 3 ; Transmitter Enable 382rxen equ 4 ; Receiver Enable 383udrie equ 5 ; Enable Free Data Register Interrupt 384txcie equ 6 ; Enable Transmit Complete Interrupt 385rxcie equ 7 ; Enable Receive Complete Interrupt 386 387 if ismega(__cpucode) 388ucsrc port 0x20 ; Control Register C 389ursel equ 7 ; Register Select 390umsel equ 6 ; Sync/Async Mode 391upm1 equ 5 ; Parity Mode 392upm0 equ 4 393usbs equ 3 ; Stop Bit Select 394ucsz1 equ 2 ; Character Size 395ucsz0 equ 1 396ucpol equ 0 ; Clock Polarity 397 endif 398 399ubrr port 0x09 ; Baud Rate Generator 400 if ismega(__cpucode) 401ubrrl port ubrr 402ubrrh port ucsrc 403 endif 404 endif 405 406 if __cpucode>=0x014414 407spcr port 0x0d ; SPI Control Register: 408spr0 equ 0 ; Clock Selection 409spr1 equ 1 410cpha equ 2 ; Clock Phase 411cpol equ 3 ; Clock Polarity 412mstr equ 4 ; Master/Slave Select 413dord equ 5 ; Bit Order 414spe equ 6 ; SPI Enable 415spie equ 7 ; SPI Interrupt Enable 416 417spsr port 0x0e ; SPI Status Register: 418 if ismega(__cpucode) 419spi2x equ 0 ; Double Speed Mode 420 endif 421wcol equ 6 ; Write Collision ? 422spif equ 7 ; SPI Interrupt Flag 423 424spdr port 0x0f ; SPI Data Register 425 endif 426 427 if ismega(__cpucode) 428twbr port 0x00 ; Bit Rate Register 429 430twcr port 0x36 ; Control Register 431twint equ 7 ; Interrupt Flag 432twea equ 6 ; Enable Acknowledge Bit 433twsta equ 5 ; Start Condition 434twsto equ 4 ; Stop Condition 435twwc equ 3 ; Write Collision Flag 436twen equ 2 ; Enable Bit 437twie equ 0 ; Interupt Enable 438 439twsr port 0x01 ; Status Register 440tws7 equ 7 ; Status 441tws6 equ 6 442tws5 equ 5 443tws4 equ 4 444tws3 equ 3 445twps1 equ 1 ; Prescaler 446twps0 equ 0 447 448twdr port 0x03 ; Data Register 449 450twar port 0x02 ; (Slave) Address Register 451twgce equ 0 ; General Call recognition Bit 452 endif 453 454;---------------------------------------------------------------------------- 455; Analog Comparator 456 457acsr port 0x08 ; Comparator Control/Status Register: 458acis0 equ 0 ; Interrupt Mode 459acis1 equ 1 460 if __cpucode>=0x012313 461acic equ 2 ; Use Comparator as Capture Signal for Timer 1 462 endif 463acie equ 3 ; Interrupt Enable 464aci equ 4 ; Interrupt Flag 465aco equ 5 ; Comparator Output 466 if ismega(__cpucode) 467acbg equ 6 ; Bandgap Select 468 endif 469acd equ 7 ; Power Off 470 471;---------------------------------------------------------------------------- 472; A/D Converter 473 474 if ismega(__cpucode) 475admux port 0x07 ; Multiplexer Selection 476refs1 equ 7 ; reference Selection Bits 477refs0 equ 6 478adlar equ 5 ; Left Adjust Right 479mux3 equ 3 ; Multiplexer 480mux2 equ 2 481mux1 equ 1 482mux0 equ 0 483 484 if __cpucode >=0x020010 485adcsra port 0x06 ; Control/Status Register 486adate equ 5 ; Auto Trigger Enable 487 elseif 488adcsr port 0x06 ; Control/Status Register 489adfr equ 5 ; free Running Select 490 endif 491aden equ 7 ; Enable ADC 492adsc equ 6 ; Start Conversion 493adif equ 4 ; Interrupt Flag 494adie equ 3 ; Interrupt Enable 495adps2 equ 2 ; Prescaler Select 496adps1 equ 1 497adps0 equ 0 498 499adch port 0x05 ; Data Register 500adcl port 0x04 501 endif 502 503;---------------------------------------------------------------------------- 504; JTAG 505 506 if __cpucode >=0x020010 507ocdr port osccal ; Debug Register 508 endif 509 510;---------------------------------------------------------------------------- 511; EEPROM 512 513 if eeend>=256 514eearl port 0x1e ; Address Register 515eearh port 0x1f 516 elseif 517eear port 0x1e 518 endif 519 520eedr port 0x1d ; Data Register 521 522eecr port 0x1c ; Control Register: 523eere equ 0 ; Read Enable 524eewe equ 1 ; Write Enable 525 if __cpucode>=0x012313 526eemwe equ 2 527 endif 528 if __cpucode=0x020008 529eerie equ 3 ; Enable Ready Interrupt 530 endif 531 532;---------------------------------------------------------------------------- 533; Vectors 534; Unfortunately, interrupt numbers change for biggger processors 535; Why only, Atmel, why ? 536 537vec_reset label 0 ; Reset Entry 538 switch __cpucode 539 case 0x011200 540vec_int0 label 1 ; Entry External Interrupt 0 541vec_tm0ovf label 2 ; Entry Overflow Timer 0 542vec_anacomp label 3 ; Entry Analog Comparator 543 case 0x012313 544vec_int0 label 1 ; Entry External Interrupt 0 545vec_int1 label 2 ; Entry External Interrupt 2 546vec_tm1capt label 3 ; Entry Capture Timer 1 547vec_tm1comp label 4 ; Entry Compare Timer 1 548vec_tm1ovf label 5 ; Entry Overflow Timer 1 549vec_tm0ovf label 6 ; Entry Overflow Timer 0 550vec_uartrx label 7 ; Entry UART Empfang komplett 551vec_uartudre label 8 ; Entry UART Data Register leer 552vec_uarttx label 9 ; Entry UART Sendung komplett 553vec_anacomp label 10 ; Entry Analog-Komparator 554 case 0x014414,0x018515 555vec_int0 label 1 ; Entry External Interrupt 0 556vec_int1 label 2 ; Entry External Interrupt 2 557vec_tm1capt label 3 ; Entry Capture Timer 1 558vec_tm1compa label 4 ; Entry Compare A Timer 1 559vec_tm1compb label 5 ; Entry Compare A Timer 1 560vec_tm1ovf label 6 ; Entry Overflow Timer 1 561vec_tm0ovf label 7 ; Entry Overflow Timer 0 562vec_spi label 8 ; Entry SPI Interrupt 563vec_uartrx label 9 ; Entry UART Reception Complete 564vec_uartudre label 10 ; Entry UART Data Register Empty 565vec_uarttx label 11 ; Entry UART Sendung Complete 566vec_anacomp label 12 ; Entry Analog Comparator 567 case 0x020008 568vec_int0 label 1 ; Entry External Interrupt 0 569vec_int1 label 2 ; External Interrupt 1 570vec_tm2comp label 3 ; Timer 2 Compare Match 571vec_tm2ovf label 4 ; Timer 2 Overflow 572vec_tm1capt label 5 ; Timer 1 Capture 573vec_tm1compa label 6 ; Timer 1 Compare Match A 574vec_tm1compb label 7 ; Timer 1 Compare Match B 575vec_tm1ovf label 8 ; Timer 1 Overflow 576vec_tm0ovf label 9 ; Timer 0 Overflow 577vec_spi label 10 ; SPI Transfer Complete 578vec_uartrx label 11 ; UART Rx Complete 579vec_uartudre label 12 ; UART Data Register Empty 580vec_uarttx label 13 ; UART Tx Complete 581vec_adc label 14 ; ADC Conversion Complete 582vec_eerdy label 15 ; EEPROM Ready 583vec_anacomp label 16 ; analog Comparator 584vec_twi label 17 ; Two-Wire Interface 585vec_spm_rdy label 18 ; Store Program Memory Ready 586 case 0x020010 587vec_int0 label 2 ; External Interrupt 0 588vec_int1 label 4 ; External Interrupt 1 589vec_tm2comp label 6 ; Timer 2 Compare Match 590vec_tm2ovf label 8 ; Timer 2 Overflow 591vec_tm1capt label 10 ; Timer 1 Capture 592vec_tm1compa label 12 ; Timer 1 Compare Match A 593vec_tm1compb label 14 ; Timer 1 Compare Match B 594vec_tm1ovf label 16 ; Timer 1 Overflow 595vec_tm0ovf label 18 ; Timer 0 Overflow 596vec_spi label 20 ; SPI Transfer Complete 597vec_uartrx label 22 ; UART Rx Complete 598vec_uartudre label 24 ; UART Data Register Empty 599vec_uarttx label 26 ; UART Tx Complete 600vec_adc label 28 ; ADC Conversion Complete 601vec_eerdy label 30 ; EEPROM Ready 602vec_anacomp label 32 ; analog Comparator 603vec_twi label 34 ; Two-Wire Interface 604vec_int2 label 36 ; External Interrupt 2 605vec_tm0comp label 38 ; Timer 0 Compare Match 606vec_spm_rdy label 40 ; Store Program Memory Ready 607 endcase 608 609;---------------------------------------------------------------------------- 610 611 restore ; re-allow listing 612 613 endif ; __regavrinc 614