1                ifndef  stddef4xinc     ; avoid multiple inclusion
2stddef4xinc     equ     1
3
4                save
5                listing off		; no listing over this file
6
7;****************************************************************************
8;*                                                                          *
9;*   AS - File STDDEF4X.INC                                                 *
10;*   								            *
11;*   Contains Register and Address Definitions for TMS320C4x CPUs           *
12;* 									    *
13;****************************************************************************
14
15                if      (MOMCPUNAME<>"320C40")&&(MOMCPUNAME<>"320C44")
16                 fatal  "wrong processor type set: use only 320C40/320C44"
17		endif
18
19                if      MOMPASS=1
20                 message "TMS320C4x Definitions (C) 2016 Alfred Arnold"
21		endif
22
23;------------------------------------------------------------------------------
24; Memory Control
25
26GMICR		equ	00100000h	; Global Memory Interface Control Register
27LMICR		equ	00100004h	; Local Memory Interface Control Register
28
29;------------------------------------------------------------------------------
30; Timer
31
32__deftimer	macro	num,base
33__CHAN  set     num
34__CHANS set     "\{__CHAN}"
35T{__CHANS}CTRL          equ     base+0h	; Control Register
36T{__CHANS}CNT           equ     base+4h	; Counter Register
37T{__CHANS}PERIOD        equ     base+8h	; Period Register
38                endm
39
40		__deftimer 0,00100020h
41		__deftimer 1,00100030h
42
43;------------------------------------------------------------------------------
44; Communication Ports
45
46__defcomm	macro	num,base
47__CHAN  set     num
48__CHANS set     "\{__CHAN}"
49CPCR{__CHANS}            equ    base+0       ; Control Register
50IFIFO{__CHANS}POS0       equ    base+1       ; Input FIFO Position 0
51OFIFO{__CHANS}POS7       equ    base+2       ; Output FIFO Position 7
52P{__CHANS}RESET          equ    base+3       ; Software Reset
53		endm
54
55		if	MOMCPUNAME="320C40"
56		 __defcomm 0,00100040h
57		 __defcomm 3,00100070h
58		endif
59
60		__defcomm 1,00100050h
61		__defcomm 2,00100060h
62		__defcomm 4,00100080h
63		__defcomm 5,00100090h
64
65;------------------------------------------------------------------------------
66; Channel Registers
67
68__defdma	macro	num,base
69__CHAN	set	num
70__CHANS	set	"\{__CHAN}"
71DMA{__CHANS}CTRL	equ	base+0	; Control Register
72DMA{__CHANS}SRCADDR	equ	base+1	; Source Address
73DMA{__CHANS}SRCIDX	equ	base+2	; Source Address Index
74DMA{__CHANS}TCNT	equ	base+3	; Transfer Counter
75DMA{__CHANS}DSTADDR	equ	base+4	; Destination Address
76DMA{__CHANS}DSTIDX	equ	base+5	; Destination Address Index
77DMA{__CHANS}LINKPTR	equ	base+6	; Link Pointer
78DMA{__CHANS}AUXTCNT	equ	base+7	; Auxiliary Transfer Counter
79DMA{__CHANS}AUXLINKPTR	equ	base+8	; Auxiliary Link Pointer
80		endm
81
82		__defdma	0,001000a0h
83		__defdma	1,001000b0h
84		__defdma	2,001000c0h
85		__defdma	3,001000d0h
86		__defdma	4,001000e0h
87		__defdma	5,001000f0h
88
89;------------------------------------------------------------------------------
90; Interrupt Vector Addresses
91
92INTVEC_RESET	equ	0
93INTVEC_NMI	equ     1
94INTVEC_TINT0	equ	2
95__TMPINTVEC	set	0
96		rept	4
97INTVEC_IIOF{"\{__TMPINTVEC}"} equ __TMPINTVEC+3
98__TMPINTVEC	set	__TMPINTVEC+1
99                endm
100__TMPINTVEC	set	0
101		rept	6
102INTVEC_ICFULL{"\{__TMPINTVEC}"}		equ	__TMPINTVEC*4+0dh
103INTVEC_ICRDY{"\{__TMPINTVEC}"}		equ	__TMPINTVEC*4+0eh
104INTVEC_OCRDY{"\{__TMPINTVEC}"}		equ	__TMPINTVEC*4+0fh
105INTVEC_OCEMPTY{"\{__TMPINTVEC}"}	equ	__TMPINTVEC*4+10h
106__TMPINTVEC	set	__TMPINTVEC+1
107                endm
108__TMPINTVEC	set	0
109		rept	6
110INTVEC_DMATINT{"\{__TMPINTVEC}"}	equ	__TMPINTVEC+25h
111__TMPINTVEC	set	__TMPINTVEC+1
112                endm
113INTVEC_TINT1	equ	02bh
114
115;------------------------------------------------------------------------------
116
117		restore			; allow listing again
118
119		endif			; stddef4xinc
120