1                ifndef  stddef60inc     ; avoid multiple inclusion
2stddef60inc     equ     1
3
4                save
5                listing off		; no listing over this file
6
7;****************************************************************************
8;*                                                                          *
9;*   AS 1.42 - STDDEF60.INC                                                 *
10;*   								            *
11;*   Contains Macro Definitions for PowerPC                                 *
12;* 									    *
13;****************************************************************************
14
15                if      MOMPASS=1
16                 message "PowerPC Macro Definitions (C) 1994,2012 Alfred Arnold"
17                 switch  MOMCPUNAME
18                 case    "RS6000"
19                  message "Target System RS6000"
20                 case    "MPC601"
21                  message "Target System MPC601"
22                 case    "MPC505"
23                  message "Target System MPC505"
24                 case    "PPC403"
25                  message "Target System PPC403"
26                 case    "PPC403GC"
27                  message "Target System PPC403GC"
28                 case    "MPC821"
29                  message "Target System MPC821"
30                 elsecase
31                  fatal  "Wrong target selected: only MPC601, MPC505, PPC403[GC], MPC821 or RS6000 allowed"
32                 endcase
33		endif
34
35
36;============================================================================
37; Device Control Register
38
39__defdcr        macro   NAME,val,{NoExpand}
40NAME            equ     val
41mt{"NAME"}      macro      reg
42                mtdcr   NAME,reg
43                endm
44mf{"NAME"}      macro      reg
45                mfdcr   reg,NAME
46                endm
47		endm
48
49                if      (MOMCPU=0x403)||(MOMCPU=0x403c)
50                 __defdcr BEAR,0x90     ; Bus Error Address
51                 __defdcr BESR,0x91     ; Bus Error Syndrome
52                 __defdcr BR0,0x80      ; Bank Registers 0..7
53                 __defdcr BR1,0x81
54                 __defdcr BR2,0x82
55                 __defdcr BR3,0x83
56                 __defdcr BR4,0x84
57                 __defdcr BR5,0x85
58                 __defdcr BR6,0x86
59                 __defdcr BR7,0x87
60                 __defdcr DMACC0,0xc4   ; DMA Chain Counter
61                 __defdcr DMACR0,0xc0   ; DMA Control Register Channel 0..3
62                 __defdcr DMACR1,0xc8
63                 __defdcr DMACR2,0xd0
64                 __defdcr DMACR3,0xd8
65                 __defdcr DMACT0,0xc1   ; DMA Count Register Channel 0..3
66                 __defdcr DMACT1,0xc9
67                 __defdcr DMACT2,0xd1
68                 __defdcr DMACT3,0xd9
69                 __defdcr DMADA0,0xc2   ; DMA Target Address Channel 0..3
70                 __defdcr DMADA1,0xca
71                 __defdcr DMADA2,0xd2
72                 __defdcr DMADA3,0xda
73                 __defdcr DMASA0,0xc3   ; DMA Source Address Channel 0..3
74                 __defdcr DMASA1,0xcb
75                 __defdcr DMASA2,0xd3
76                 __defdcr DMASA3,0xdb
77                 __defdcr DMASR,0xe0    ; DMA Status Register
78                 __defdcr EXISR,0x40    ; External Interrupt Status Register
79                 __defdcr EXIER,0x42    ; External Interrupt Enable Register
80                 __defdcr IOCR,0xa0     ; I/O Configuration
81                endif
82
83;============================================================================
84; Special Purpose Registers
85
86__defspr        macro   NAME,val,{NoExpand}
87NAME            equ     val
88mt{"NAME"}      macro      reg
89                mtspr   NAME,reg
90                endm
91mf{"NAME"}      macro      reg
92                mfspr   reg,NAME
93                endm
94		endm
95
96                __defspr XER,0x001      ; Integer Exception Register
97                __defspr LR,0x008       ; Link Register
98                __defspr CTR,0x009      ; Count Register
99                __defspr SRR0,0x01a     ; Save/Restore Register
100                __defspr SRR1,0x01b
101                __defspr SPRG0,0x110    ; Special Purpose Register
102                __defspr SPRG1,0x111
103                __defspr SPRG2,0x112
104                __defspr SPRG3,0x113
105                switch MOMCPU
106                case 0x403,0x403c
107                 __defspr DAC1,0x3f6    ; Data Address Compare Register
108                 __defspr DAC2,0x3f7
109                 __defspr DBCR,0x3f2    ; Debug Control Register
110                 __defspr DBSR,0x3f0    ; Debug Status Register
111                 __defspr DCCR,0x3fa    ; Data Cache Control Register
112                 __defspr DEAR,0x3d5    ; Data Exception Addresse Register
113                 __defspr ESR,0x3d4     ; Exception Syndrome Datea Access
114                 __defspr EVPR,0x3d6    ; Exception Vector Prefix
115                 __defspr IAC1,0x3f4    ; Code Address Compare Register
116                 __defspr IAC2,0x3f5
117                 __defspr ICCR,0x3fb    ; Instruction Cache Control Register
118                 __defspr PBL1,0x3fc    ; Lower Bounds
119                 __defspr PBL2,0x3fe
120                 __defspr PBU1,0x3fd    ; Upper Bounds
121                 __defspr PBU2,0x3ff
122                 __defspr PIT,0x3db     ; Timer
123                 __defspr PVR,0x11f     ; Processor Version
124                 __defspr SRR2,0x3de    ; Save Restore Registers
125                 __defspr SRR3,0x3df
126                 __defspr TBHI,0x3dc    ; Time Base
127                 __defspr TBLO,0x3dd
128                 __defspr TCR,0x3da     ; Timer Control Register
129                 __defspr TSR,0x3d8     ; Timer Status Register
130                 __defspr SGR,0x3b9     ; ????
131                case 0x505
132                 __defspr TBL,268       ; Time Base
133                 __defspr TBU,269
134                 __defspr DSISR,18      ; Reason for Alignment Exceptions
135                 __defspr DAR,19        ; Erroneous Data Address after Exception
136                 __defspr DEC,22        ; counts @ 1 MHz
137                 __defspr EIE,80        ; External Interrupt Enable
138                 __defspr EID,81        ; External Interrupt Disable
139                 __defspr NRE,82        ; Non Recoverable Exception
140                 __defspr TBL_S,284     ; another Time Base ?!
141                 __defspr TBU_S,285
142                 __defspr PVR,287       ; Processor Version
143                 __defspr ICCST,560     ; Instruction Cache Control & Status
144                 __defspr ICADR,561     ; Instruktion Cache Address Register
145                 __defspr ICDAT,562     ; Instruktion Cache Data Register
146                 __defspr FPECR,1022    ; Floating Point Exception
147                 __defspr CMPA,144      ; Comparison Value A..D
148                 __defspr CMPB,145
149                 __defspr CMPC,146
150                 __defspr CMPD,147
151                 __defspr ECR,148       ; Debug Exception Cause
152                 __defspr DER,149       ; Debug Enable Register
153                 __defspr COUNTA,150    ; Breakpoint Counter
154                 __defspr COUNTB,151
155                 __defspr CMPE,152      ; Comparison Value  E..H
156                 __defspr CMPF,153
157                 __defspr CMPG,154
158                 __defspr CMPH,155
159                 __defspr LCTRL1,156    ; Debug Control Comparator L Bus
160                 __defspr LCTRL2,157
161                 __defspr ICTRL,158     ; Debug Control I-Bus
162                 __defspr BAR,159       ; Breakpoint Address
163                 __defspr DPDR,630      ; Development Port Data
164                 __defspr DPIR,631      ;     "        "   Instructions
165                case 0x601
166                 __defspr RTCU,0x004    ; Counter
167                 __defspr RTCL,0x005
168                 __defspr DEC,0x006
169                 __defspr DSISR,0x012
170                 __defspr DAR,0x013
171                 __defspr DEC2,0x016
172                 __defspr SDR1,0x019
173                 __defspr EAR,0x11a
174                 __defspr BAT0U,0x210
175                 __defspr BAT0L,0x211
176                 __defspr BAT1U,0x212
177                 __defspr BAT1L,0x213
178                 __defspr BAT2U,0x214
179                 __defspr BAT2L,0x215
180                 __defspr BAT3U,0x216
181                 __defspr BAT3L,0x217
182                 __defspr HID0,0x3f0
183                 __defspr HID1,0x3f1
184                 __defspr HID2,0x3f2
185                 __defspr HID5,0x3f5
186                 __defspr HID15,0x3ff
187                case 0x6000
188                 __defspr MQ,0x000      ; Upper Half Divident/Product
189                case 0x821
190                 __defspr EIE,80        ; External Interrupts Enable
191                 __defspr EID,81        ; External Interrupts Disable
192                 __defspr NRI,82        ; Non Recoverable Exception
193                 __defspr NRE,82        ; (alias)
194                 __defspr CMPA,144      ; Comparison Value A..D
195                 __defspr CMPB,145
196                 __defspr CMPC,146
197                 __defspr CMPD,147
198                 __defspr ICR,148       ; Debug Exception Cause
199                 __defspr ECR,148       ; (alias)
200                 __defspr DER,149       ; Debug Feature Enable
201                 __defspr COUNTA,150    ; Breakpoint Counter
202                 __defspr COUNTB,151
203                 __defspr CMPE,152      ; Comparison Value E..H
204                 __defspr CMPF,153
205                 __defspr CMPG,154
206                 __defspr CMPH,155
207                 __defspr LCTRL1,156    ; Debug Control Comparator L-Bus
208                 __defspr LCTRL2,157
209                 __defspr ICTRL,158     ; Debug Control I-Bus
210                 __defspr BAR,159       ; Breakpoint Address
211                 __defspr DPDR,630      ; Development Port Data
212                 __defspr DPIR,631      ;     "        "   Instructions
213                 __defspr IMMR,638
214                 __defspr IC_CST,560    ; Instruktion Cache Control & Status Control & Status
215                 __defspr ICCST,560     ; (alias)
216                 __defspr ICCSR,560     ; (alias)
217                 __defspr IC_ADR,561    ; Instruktion Cache Control & Status Address Register
218                 __defspr ICADR,561     ; (alias)
219                 __defspr IC_DAT,562    ; Instruktion Cache Control & Status Data Register
220                 __defspr ICDAT,562     ; (alias)
221                 __defspr DC_CST,568    ; Steuerung & Status Data Cache
222                 __defspr DCCST,568     ; (alias)
223                 __defspr DCCSR,568     ; (alias)
224                 __defspr DC_ADR,569    ; Data Cache Address Register
225                 __defspr DCADR,569     ; (alias)
226                 __defspr DC_DAT,570    ; Data Cache Data Register
227                 __defspr DCDAT,570     ; (alias)
228                 __defspr MI_CTR,784
229                 __defspr MICTR,784
230                 __defspr MI_AP,786
231                 __defspr MIAP,786
232                 __defspr MI_EPN,787
233                 __defspr MIEPN,787
234                 __defspr MI_TWC,789
235                 __defspr MITWC,789
236                 __defspr MIL1DL2P,789  ; (alias)
237                 __defspr MI_RPN,790
238                 __defspr MIRPN,790
239                 __defspr MI_DBCAM,816
240                 __defspr MICAM,816
241                 __defspr MI_DBRAM0,817
242                 __defspr MIRAM0,817
243                 __defspr MI_DBRAM1,818
244                 __defspr MIRAM1,818
245                 __defspr MD_CTR,792
246                 __defspr MDCTR1,792
247                 __defspr M_CASID,793
248                 __defspr MCASID,793
249                 __defspr MD_AP,794
250                 __defspr MDAP,794
251                 __defspr MD_EPN,795
252                 __defspr MDEPN,795
253                 __defspr M_TWP,796
254                 __defspr MDTWB,796
255                 __defspr MDL1P,796     ; (alias)
256                 __defspr MD_TWC,797
257                 __defspr MDTWC,797
258                 __defspr MDL1DL2P,797  ; (alias)
259                 __defspr MD_RPN,798
260                 __defspr MDRPN,798
261                 __defspr M_TW,799
262                 __defspr MDTW,799
263                 __defspr MDSAVE,799   ; (alias)
264                 __defspr MD_DBCAM,824
265                 __defspr MDCAM,824
266                 __defspr MD_DBRAM0,825
267                 __defspr MDRAM0,825
268                 __defspr MD_DBRAM1,826
269                 __defspr MDRAM1,826
270                endcase
271                if MOMCPU=0x403c
272                 __defspr pid, 0x3b1
273                endif
274
275;============================================================================
276; Serial Port PPC403:
277
278                if      (MOMCPU=0x403)||(MOMCPU=0x403c)
279spls             equ     0x40000000     ; Line State
280sphs             equ     0x40000002     ; State of Handshake Lines
281brdh             equ     0x40000004     ; Baud Raten Divider
282brdl             equ     0x40000005
283spctl            equ     0x40000006     ; Control Register
284sprc             equ     0x40000007     ; Command Register Receiver
285sptc             equ     0x40000008     ; Command Register Transmitter
286sprb             equ     0x40000009     ; Transmit/Receive Buffer
287sptb             equ     sprb
288                endif
289
290;============================================================================
291; SIU MPC505:
292; erinnert irgendwie an die vom 6833x...
293
294                if      MOMCPU=0x505
295siumcr           equ     0x8007fc00     ; Base Control Register
296siutest1         equ     0x8007fc04
297memmap           equ     0x8007fc20     ; Memory Layout
298specaddr         equ     0x8007fc24     ; Allow/Block Speculative Loads
299specmask         equ     0x8007fc28
300termstat         equ     0x8007fc2c
301picsr            equ     0x8007fc40     ; Periodic Interrupts Control
302pit              equ     0x8007fc44     ; Periodic Interrupt Timer Count Value
303bmcr             equ     0x8007fc48     ; Bus Monitor Control
304rsr              equ     0x8007fc4c     ; Reset Status
305sccr             equ     0x8007fc50     ; System Clock Control
306sccsr            equ     0x8007fc54     ; System Clock Status
307portbase         equ     0x8007fc60
308ddrm             equ     portbase+0x00  ; Data Direction Register Port M
309pmpar            equ     portbase+0x04  ; Pin Assignment Port M
310portm            equ     portbase+0x08  ; Data Register Port M
311papar            equ     portbase+0x24  ; Pin Assignment Port A+B
312pbpar            equ     papar
313porta            equ     portbase+0x28  ; Data Register Port A+B
314portb            equ     porta
315ddri             equ     portbase+0x38  ; Data Direction Register Port I..L
316ddrj             equ     ddri
317ddrk             equ     ddri
318ddrl             equ     ddri
319pipar            equ     portbase+0x38  ; Pin Assignment Port I..L
320pjpar            equ     pipar
321pkpar            equ     pipar
322plpar            equ     pipar
323porti            equ     portbase+0x40  ; Data Register Port I..L
324portj            equ     porti
325portk            equ     porti
326portl            equ     porti
327csbase           equ     0x8007fd00
328csbtbar          equ     csbase+0xf8    ; Base Address Boot EPROM
329csbtsbbar        equ     csbase+0xf0
330csbar1           equ     csbase+0xe0    ; Base Addresses /CS1../CS5
331csbar2           equ     csbase+0xd8
332csbar3           equ     csbase+0xd0
333csbar4           equ     csbase+0xc8
334csbar5           equ     csbase+0xc0
335csbtor           equ     csbase+0xfc    ; Boot EPROM Options
336csbtsbor         equ     csbase+0xf4
337csor0            equ     csbase+0xec    ; Options /CS1../CS11
338csor1            equ     csbase+0xe4
339csor2            equ     csbase+0xdc
340csor3            equ     csbase+0xd4
341csor4            equ     csbase+0xcc
342csor5            equ     csbase+0xc4
343csor6            equ     csbase+0xbc
344csor7            equ     csbase+0xb4
345csor8            equ     csbase+0xac
346csor9            equ     csbase+0xa4
347csor10           equ     csbase+0x9c
348csor11           equ     csbase+0x94
349                endif
350
351;----------------------------------------------------------------------------
352; Peripheral Control Unit MPC505
353
354                if      MOMCPU=0x505
355pcubase          equ     0x8007ef80
356pcumcr           equ     pcubase+0x00   ; Base Configuration
357tstmsra          equ     pcubase+0x10
358tstmsrb          equ     tstmsra
359tstcntrab        equ     pcubase+0x14
360tstreps          equ     tstcntrab
361tstcreg1         equ     pcubase+0x18
362tstcreg2         equ     tstcreg1
363tstdreg          equ     pcubase+0x1c
364irqpend          equ     pcubase+0x20   ; Pending Interrupts
365irqand           equ     pcubase+0x24   ; Enabled & Pending Interrupts
366irqenable        equ     pcubase+0x28   ; Enabled Interrupts
367pitqil           equ     pcubase+0x2c   ; Interrupt Level PortQ/PIT
368swsr             equ     pcubase+0x40   ; Trigger Reload Watchdog
369swcr             equ     pcubase+0x44   ; Watchdog Control
370swtc             equ     swcr
371swr              equ     pcubase+0x48
372pqedgdat         equ     pcubase+0x50   ; Edge Selection PortQ
373pqpar            equ     pcubase+0x54   ; Pin Assignment PortQ
374                endif
375
376;----------------------------------------------------------------------------
377; SRAM Module MPC505
378
379                if      MOMCPU=0x505
380srammcr          equ     0x8007f00      ; Basiskonfiguration SRAM
381                endif
382
383;============================================================================
384; SUBI may have two or three arguments
385
386subi            macro   dest,src,VAL
387                if      "VAL"=""
388                 addi   dest,dest,-src
389                elseif
390                 addi   dest,src,-VAL
391                endif
392                endm
393
394;----------------------------------------------------------------------------
395; Comparisons
396
397cmpw            macro   cr,REG1,REG2
398                if      "REG2"=""
399                cmp     0,0,cr,REG1
400                elseif
401                cmp     cr,0,REG1,REG2
402                endif
403                endm
404
405cmpwi           macro   cr,REG1,IMM
406                if      "IMM"=""
407                cmpi    0,0,cr,IMM
408                elseif
409                cmpi    cr,0,REG1,imm
410                endif
411                endm
412
413cmplw           macro   cr,REG1,REG2
414                if      "REG2"=""
415                cmpl    0,0,cr,REG1
416                elseif
417                cmpl    cr,0,REG1,REG2
418                endif
419                endm
420
421cmplwi          macro   cr,REG1,IMM
422                if      "IMM"=""
423                cmpli   0,0,cr,IMM
424                elseif
425                cmpli   cr,0,REG1,IMM
426                endif
427                endm
428
429;----------------------------------------------------------------------------
430; Extended Instructions Condition Code Register
431
432crset           macro   bx
433                creqv   bx,bx,bx
434                endm
435
436crnot           macro   bx,by
437                crnor   bx,by,by
438                endm
439
440crmove          macro   bx,by
441                cror    bx,by,by
442                endm
443
444;----------------------------------------------------------------------------
445; Extended Logic Instructions
446
447not             macro   dest,SRC
448                if      "SRC"=""
449                 nor    dest,dest
450                elseif
451                 nor    dest,SRC,SRC
452                endif
453                endm
454
455not.            macro   dest,SRC
456                if      "SRC"=""
457                 nor.   dest,dest
458                elseif
459                 nor.   dest,SRC,SRC
460                endif
461                endm
462
463mr              macro   dest,src
464                or      dest,src,src
465                endm
466
467mr.             macro   dest,src
468                or.     dest,src,src
469                endm
470
471nop             macro
472                ori     0,0,0
473                endm
474
475;----------------------------------------------------------------------------
476; Simplified Shift-In Instructions
477
478inslwi          macro   ra,rs,n,b
479                rlwimi  ra,rs,32-b,b,b+n-1
480                endm
481inslwi.         macro   ra,rs,n,b
482                rlwimi. ra,rs,32-b,b,b+n-1
483                endm
484
485insrwi          macro   ra,rs,n,b
486                rlwimi  ra,rs,32-b-n,b,b+n-1
487                endm
488insrwi.         macro   ra,rs,n,b
489                rlwimi. ra,rs,32-b-n,b,b+n-1
490                endm
491
492__defins1       macro   NAME,par1,par2,par3,{NoExpand}
493{"NAME"}        macro   ra,rs,n
494                rlwinm  ra,rs,par1,par2,par3
495                endm
496{"NAME"}.       macro   ra,rs,n
497                rlwinm. ra,rs,par1,par2,par3
498                endm
499                endm
500
501__defins2       macro   NAME,par1,par2,par3,{NoExpand}
502{"NAME"}        macro   ra,rs,b,n
503                rlwinm  ra,rs,par1,par2,par3
504                endm
505{"NAME"}.       macro   ra,rs,b,n
506                rlwinm. ra,rs,par1,par2,par3
507                endm
508                endm
509
510                __defins1 clrlwi,0,n,31
511                __defins2 clrlslwi,n,b-n,31-n
512                __defins1 clrrwi,0,0,31-n
513                __defins2 extlwi,b,0,n-1
514                __defins2 extrwi,b+n,32-n,31
515                __defins1 rotlwi,n,0,31
516                __defins1 rotrwi,32-n,0,31
517                __defins1 slwi,n,0,31-n
518                __defins1 srwi,32-n,n,31
519
520rotlw           macro   ra,rs,rb
521                rlwnm   ra,rs,rb,0,31
522                endm
523rotlw.          macro   ra,rs,rb
524                rlwnm.  ra,rs,rb,0,31
525                endm
526
527;----------------------------------------------------------------------------
528; Simplified Jumps
529
530__defjmp1       macro   NAME,m1,m2,{NoExpand}
531{"NAME"}        macro   adr
532                bc      m1,m2,adr
533                endm
534{"NAME"}a       macro   adr
535                bca     m1,m2,adr
536                endm
537{"NAME"}l       macro   adr
538                bcl     m1,m2,adr
539                endm
540{"NAME"}la      macro   adr
541                bcla    m1,m2,adr
542                endm
543                endm
544
545                __defjmp1 bdnz,16,0
546                __defjmp1 bdz,18,0
547
548__defjmp2       macro   NAME,m1,{NoExpand}
549{"NAME"}        macro   cr,adr
550                bc      m1,cr,adr
551                endm
552{"NAME"}a       macro   cr,adr
553                bca     m1,cr,adr
554                endm
555{"NAME"}l       macro   cr,adr
556                bcl     m1,cr,adr
557                endm
558{"NAME"}la      macro   cr,adr
559                bcla    m1,cr,adr
560                endm
561                endm
562
563                __defjmp2 bdnzf,0
564                __defjmp2 bdnzt,8
565                __defjmp2 bdzf,2
566                __defjmp2 bdzt,10
567                __defjmp2 bf,4
568                __defjmp2 bt,12
569
570__defjmp3       macro   NAME,mask,ofs,{NoExpand}
571{"NAME"}        macro   cr,ADR
572                if      "ADR"=""
573                 bc      mask,ofs,cr
574                elseif
575                 bc      mask,cr*4+ofs,adr
576                endif
577                endm
578{"NAME"}a       macro   cr,ADR
579                if      "ADR"=""
580                 bca     mask,ofs,cr
581                elseif
582                 bca     mask,cr*4+ofs,adr
583                endif
584                endm
585{"NAME"}l       macro   cr,ADR
586                if      "ADR"=""
587                 bcl     mask,ofs,cr
588                elseif
589                 bcl     mask,cr*4+ofs,adr
590                endif
591                endm
592{"NAME"}la      macro   cr,ADR
593                if      "ADR"=""
594                 bcla    mask,ofs,cr
595                elseif
596                 bcla    mask,cr*4+ofs,adr
597                endif
598                endm
599{"NAME"}ctr     macro   CR
600                if      "CR"=""
601                 bcctr   mask,ofs
602                elseif
603                 bc      mask,CR*4+ofs
604                endif
605                endm
606{"NAME"}ctrl    macro   CR
607                if      "CR"=""
608                 bcl     mask,ofs
609                elseif
610                 bcl     mask,CR*4+ofs
611                endif
612                endm
613{"NAME"}lr      macro   CR
614                if      "CR"=""
615                bclr    mask,ofs
616                elseif
617                bclr    mask,4*CR+ofs
618                endif
619                endm
620{"NAME"}lrl     macro   CR
621                if      "CR"=""
622                bclrl   mask,ofs
623                elseif
624                bclrl   mask,4*CR+ofs
625                endif
626                endm
627                endm
628
629                __defjmp3 beq,12,2
630                __defjmp3 bge,4,0
631                __defjmp3 bgt,12,1
632                __defjmp3 ble,4,1
633                __defjmp3 blt,12,0
634                __defjmp3 bne,4,2
635                __defjmp3 bng,4,1
636                __defjmp3 bnl,4,0
637                __defjmp3 bns,4,3
638                __defjmp3 bnu,4,3
639                __defjmp3 bso,12,3
640                __defjmp3 bun,12,3
641
642bctr            macro
643                bcctr   20,0
644                endm
645bctrl           macro
646                bcctrl  20,0
647                endm
648
649__defjmp4       macro   NAME,mask,{NoExpand}
650{"NAME"}        macro   cr
651                bcctr   mask,cr
652                endm
653{"NAME"}l       macro   cr
654                bcctrl  mask,cr
655                endm
656                endm
657
658                __defjmp4 bfctr,4
659                __defjmp4 btctr,12
660
661__defjmp6       macro   NAME,mask,bit,{NoExpand}
662{"NAME"}        macro
663                bclr    mask,bit
664                endm
665{"NAME"}l       macro
666                bclrl   mask,bit
667                endm
668                endm
669
670                __defjmp6 blr,20,0
671                __defjmp6 bdnzlr,16,0
672                __defjmp6 bdzlr,18,0
673
674__defjmp7       macro   NAME,mask,{NoExpand}
675{"NAME"}        macro   cr
676                bclr    mask,cr
677                endm
678{"NAME"}l       macro   cr
679                bclrl   mask,cr
680                endm
681                endm
682
683                __defjmp7 bdnzflr,0
684                __defjmp7 bdnztlr,8
685                __defjmp7 bdzflr,2
686                __defjmp7 bdztlr,10
687                __defjmp7 bflr,4
688                __defjmp7 btlr,12
689
690;-------------------------------------------------------------------------
691; Traps
692
693trap            macro   ra,rb
694                tw      31,ra,rb
695                endm
696
697__deftrap       macro   NAME,mask,{NoExpand}
698{"NAME"}        macro   ra,rb
699                tw      mask,ra,rb
700                endm
701{"NAME"}i       macro   ra,im
702                twi     mask,ra,im
703                endm
704                endm
705
706                __deftrap tweq,4
707                __deftrap twge,12
708                __deftrap twgt,8
709                __deftrap twle,20
710                __deftrap twlge,5
711                __deftrap twlgt,1
712                __deftrap twlle,6
713                __deftrap twllt,2
714                __deftrap twlng,6
715                __deftrap twlnl,5
716                __deftrap twlt,16
717                __deftrap twne,24
718                __deftrap twng,20
719                __deftrap twnl,12
720
721;-------------------------------------------------------------------------
722; MMU Macros PPC403G[BC]
723
724		if (MOMCPU=0x403c)||(MOMCPU=0x403c)
725
726tlbrehi		macro	rt,ra
727		tlbre	rt,ra,0
728		endm
729
730tlbrelo		macro	rt,ra
731		tlbre	rt,ra,1
732		endm
733
734tlbwehi		macro	rt,ra
735		tlbwe	rt,ra,0
736		endm
737
738tlbwelo		macro	rt,ra
739		tlbwe	rt,ra,1
740		endm
741
742		endif
743
744;=========================================================================
745
746                restore                 ; allow listing again
747
748                endif			; stddef60inc
749