1;; Predicate definitions of Andes NDS32 cpu for GNU compiler 2;; Copyright (C) 2012-2020 Free Software Foundation, Inc. 3;; Contributed by Andes Technology Corporation. 4;; 5;; This file is part of GCC. 6;; 7;; GCC is free software; you can redistribute it and/or modify it 8;; under the terms of the GNU General Public License as published 9;; by the Free Software Foundation; either version 3, or (at your 10;; option) any later version. 11;; 12;; GCC is distributed in the hope that it will be useful, but WITHOUT 13;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 14;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 15;; License for more details. 16;; 17;; You should have received a copy of the GNU General Public License 18;; along with GCC; see the file COPYING3. If not see 19;; <http://www.gnu.org/licenses/>. 20 21(define_predicate "nds32_equality_comparison_operator" 22 (match_code "eq,ne")) 23 24(define_predicate "nds32_greater_less_comparison_operator" 25 (match_code "gt,ge,lt,le")) 26 27(define_predicate "nds32_float_comparison_operator" 28 (match_code "eq,ne,le,lt,ge,gt,ordered,unordered,ungt,unge,unlt,unle")) 29 30(define_predicate "nds32_movecc_comparison_operator" 31 (match_code "eq,ne,le,leu,ge,geu")) 32 33(define_special_predicate "nds32_logical_binary_operator" 34 (match_code "and,ior,xor")) 35 36(define_special_predicate "nds32_conditional_call_comparison_operator" 37 (match_code "lt,ge")) 38 39(define_special_predicate "nds32_have_33_inst_operator" 40 (match_code "mult,and,ior,xor")) 41 42(define_predicate "nds32_symbolic_operand" 43 (and (match_code "const,symbol_ref,label_ref") 44 (match_test "!(TARGET_ICT_MODEL_LARGE 45 && nds32_indirect_call_referenced_p (op))"))) 46 47(define_predicate "nds32_nonunspec_symbolic_operand" 48 (and (match_code "const,symbol_ref,label_ref") 49 (match_test "!flag_pic && nds32_const_unspec_p (op) 50 && !(TARGET_ICT_MODEL_LARGE 51 && nds32_indirect_call_referenced_p (op))"))) 52 53(define_predicate "nds32_reg_constant_operand" 54 (ior (match_operand 0 "register_operand") 55 (match_operand 0 "const_int_operand"))) 56 57(define_predicate "nds32_rimm15s_operand" 58 (ior (match_operand 0 "register_operand") 59 (and (match_operand 0 "const_int_operand") 60 (match_test "satisfies_constraint_Is15 (op)")))) 61 62(define_predicate "nds32_rimm11s_operand" 63 (ior (match_operand 0 "register_operand") 64 (and (match_operand 0 "const_int_operand") 65 (match_test "satisfies_constraint_Is11 (op)")))) 66 67(define_predicate "nds32_imm_0_1_operand" 68 (and (match_operand 0 "const_int_operand") 69 (ior (match_test "satisfies_constraint_Iv00 (op)") 70 (match_test "satisfies_constraint_Iv01 (op)")))) 71 72(define_predicate "nds32_imm_1_2_operand" 73 (and (match_operand 0 "const_int_operand") 74 (ior (match_test "satisfies_constraint_Iv01 (op)") 75 (match_test "satisfies_constraint_Iv02 (op)")))) 76 77(define_predicate "nds32_imm_1_2_4_8_operand" 78 (and (match_operand 0 "const_int_operand") 79 (ior (ior (match_test "satisfies_constraint_Iv01 (op)") 80 (match_test "satisfies_constraint_Iv02 (op)")) 81 (ior (match_test "satisfies_constraint_Iv04 (op)") 82 (match_test "satisfies_constraint_Iv08 (op)"))))) 83 84(define_predicate "nds32_imm2u_operand" 85 (and (match_operand 0 "const_int_operand") 86 (match_test "satisfies_constraint_Iu02 (op)"))) 87 88(define_predicate "nds32_imm4u_operand" 89 (and (match_operand 0 "const_int_operand") 90 (match_test "satisfies_constraint_Iu04 (op)"))) 91 92(define_predicate "nds32_imm5u_operand" 93 (and (match_operand 0 "const_int_operand") 94 (match_test "satisfies_constraint_Iu05 (op)"))) 95 96(define_predicate "nds32_imm6u_operand" 97 (and (match_operand 0 "const_int_operand") 98 (match_test "satisfies_constraint_Iu06 (op)"))) 99 100(define_predicate "nds32_rimm4u_operand" 101 (ior (match_operand 0 "register_operand") 102 (match_operand 0 "nds32_imm4u_operand"))) 103 104(define_predicate "nds32_rimm5u_operand" 105 (ior (match_operand 0 "register_operand") 106 (match_operand 0 "nds32_imm5u_operand"))) 107 108(define_predicate "nds32_rimm6u_operand" 109 (ior (match_operand 0 "register_operand") 110 (match_operand 0 "nds32_imm6u_operand"))) 111 112(define_predicate "nds32_move_operand" 113 (and (match_operand 0 "general_operand") 114 (not (match_code "high,const,symbol_ref,label_ref"))) 115{ 116 /* If the constant op does NOT satisfy Is20 nor Ihig, 117 we cannot perform move behavior by a single instruction. */ 118 if (CONST_INT_P (op) 119 && !satisfies_constraint_Is20 (op) 120 && !satisfies_constraint_Ihig (op)) 121 return false; 122 123 return true; 124}) 125 126(define_predicate "nds32_vmove_operand" 127 (and (match_operand 0 "general_operand") 128 (not (match_code "high,const,symbol_ref,label_ref"))) 129{ 130 /* If the constant op does NOT satisfy Is20 nor Ihig, 131 we cannot perform move behavior by a single instruction. */ 132 if (GET_CODE (op) == CONST_VECTOR 133 && !satisfies_constraint_CVs2 (op) 134 && !satisfies_constraint_CVhi (op)) 135 return false; 136 137 return true; 138}) 139 140(define_predicate "nds32_and_operand" 141 (match_operand 0 "nds32_reg_constant_operand") 142{ 143 return REG_P (op) 144 || GET_CODE (op) == SUBREG 145 || satisfies_constraint_Izeb (op) 146 || satisfies_constraint_Izeh (op) 147 || satisfies_constraint_Ixls (op) 148 || satisfies_constraint_Ix11 (op) 149 || satisfies_constraint_Ibms (op) 150 || satisfies_constraint_Ifex (op) 151 || satisfies_constraint_Iu15 (op) 152 || satisfies_constraint_Ii15 (op) 153 || satisfies_constraint_Ic15 (op); 154}) 155 156(define_predicate "nds32_ior_operand" 157 (match_operand 0 "nds32_reg_constant_operand") 158{ 159 return REG_P (op) 160 || GET_CODE (op) == SUBREG 161 || satisfies_constraint_Iu15 (op) 162 || satisfies_constraint_Ie15 (op); 163}) 164 165(define_predicate "nds32_xor_operand" 166 (match_operand 0 "nds32_reg_constant_operand") 167{ 168 return REG_P (op) 169 || GET_CODE (op) == SUBREG 170 || satisfies_constraint_Iu15 (op) 171 || satisfies_constraint_It15 (op); 172}) 173 174(define_predicate "nds32_general_register_operand" 175 (match_code "reg,subreg") 176{ 177 if (GET_CODE (op) == SUBREG) 178 op = SUBREG_REG (op); 179 180 return (REG_P (op) 181 && (REGNO (op) >= FIRST_PSEUDO_REGISTER 182 || REGNO (op) <= NDS32_LAST_GPR_REGNUM)); 183}) 184 185(define_predicate "nds32_call_address_operand" 186 (ior (match_operand 0 "nds32_symbolic_operand") 187 (match_operand 0 "nds32_general_register_operand"))) 188 189(define_predicate "nds32_insv_operand" 190 (match_code "const_int") 191{ 192 return INTVAL (op) == 0 193 || INTVAL (op) == 8 194 || INTVAL (op) == 16 195 || INTVAL (op) == 24; 196}) 197 198(define_predicate "nds32_lmw_smw_base_operand" 199 (and (match_code "mem") 200 (match_test "nds32_valid_smw_lwm_base_p (op)"))) 201 202(define_predicate "float_even_register_operand" 203 (and (match_code "reg") 204 (and (match_test "REGNO (op) >= NDS32_FIRST_FPR_REGNUM") 205 (match_test "REGNO (op) <= NDS32_LAST_FPR_REGNUM") 206 (match_test "(REGNO (op) & 1) == 0")))) 207 208(define_predicate "float_odd_register_operand" 209 (and (match_code "reg") 210 (and (match_test "REGNO (op) >= NDS32_FIRST_FPR_REGNUM") 211 (match_test "REGNO (op) <= NDS32_LAST_FPR_REGNUM") 212 (match_test "(REGNO (op) & 1) != 0")))) 213 214(define_special_predicate "nds32_load_multiple_operation" 215 (match_code "parallel") 216{ 217 /* To verify 'load' operation, pass 'true' for the second argument. 218 See the implementation in nds32.c for details. */ 219 return nds32_valid_multiple_load_store_p (op, true, false); 220}) 221 222(define_special_predicate "nds32_load_multiple_and_update_address_operation" 223 (match_code "parallel") 224{ 225 /* To verify 'load' operation, pass 'true' for the second argument. 226 to verify 'update address' operation, pass 'true' for the third argument 227 See the implementation in nds32.c for details. */ 228 return nds32_valid_multiple_load_store_p (op, true, true); 229}) 230 231(define_special_predicate "nds32_store_multiple_operation" 232 (match_code "parallel") 233{ 234 /* To verify 'store' operation, pass 'false' for the second argument. 235 See the implementation in nds32.c for details. */ 236 return nds32_valid_multiple_load_store_p (op, false, false); 237}) 238 239(define_special_predicate "nds32_store_multiple_and_update_address_operation" 240 (match_code "parallel") 241{ 242 /* To verify 'store' operation, pass 'false' for the second argument, 243 to verify 'update address' operation, pass 'true' for the third argument 244 See the implementation in nds32.c for details. */ 245 return nds32_valid_multiple_load_store_p (op, false, true); 246}) 247 248(define_special_predicate "nds32_stack_push_operation" 249 (match_code "parallel") 250{ 251 /* To verify 'push' operation, pass 'true' for the second argument. 252 See the implementation in nds32-predicates.c for details. */ 253 return nds32_valid_stack_push_pop_p (op, true); 254}) 255 256(define_special_predicate "nds32_stack_pop_operation" 257 (match_code "parallel") 258{ 259 /* To verify 'pop' operation, pass 'false' for the second argument. 260 See the implementation in nds32-predicates.c for details. */ 261 return nds32_valid_stack_push_pop_p (op, false); 262}) 263 264;; ------------------------------------------------------------------------ 265