1 /* Definitions of target machine for GNU compiler, for IBM S/390 2 Copyright (C) 1999-2020 Free Software Foundation, Inc. 3 Contributed by Hartmut Penner (hpenner@de.ibm.com) and 4 Ulrich Weigand (uweigand@de.ibm.com). 5 Andreas Krebbel (Andreas.Krebbel@de.ibm.com) 6 7 This file is part of GCC. 8 9 GCC is free software; you can redistribute it and/or modify it under 10 the terms of the GNU General Public License as published by the Free 11 Software Foundation; either version 3, or (at your option) any later 12 version. 13 14 GCC is distributed in the hope that it will be useful, but WITHOUT ANY 15 WARRANTY; without even the implied warranty of MERCHANTABILITY or 16 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 17 for more details. 18 19 You should have received a copy of the GNU General Public License 20 along with GCC; see the file COPYING3. If not see 21 <http://www.gnu.org/licenses/>. */ 22 23 #ifndef _S390_H 24 #define _S390_H 25 26 /* Optional architectural facilities supported by the processor. */ 27 28 enum processor_flags 29 { 30 PF_IEEE_FLOAT = 1, 31 PF_ZARCH = 2, 32 PF_LONG_DISPLACEMENT = 4, 33 PF_EXTIMM = 8, 34 PF_DFP = 16, 35 PF_Z10 = 32, 36 PF_Z196 = 64, 37 PF_ZEC12 = 128, 38 PF_TX = 256, 39 PF_Z13 = 512, 40 PF_VX = 1024, 41 PF_Z14 = 2048, 42 PF_VXE = 4096, 43 PF_VXE2 = 8192, 44 PF_Z15 = 16384 45 }; 46 47 /* This is necessary to avoid a warning about comparing different enum 48 types. */ 49 #define s390_tune_attr ((enum attr_cpu)(s390_tune > PROCESSOR_8561_Z15 ? PROCESSOR_8561_Z15 : s390_tune )) 50 51 /* These flags indicate that the generated code should run on a cpu 52 providing the respective hardware facility regardless of the 53 current cpu mode (ESA or z/Architecture). */ 54 55 #define TARGET_CPU_IEEE_FLOAT \ 56 (s390_arch_flags & PF_IEEE_FLOAT) 57 #define TARGET_CPU_IEEE_FLOAT_P(opts) \ 58 (opts->x_s390_arch_flags & PF_IEEE_FLOAT) 59 #define TARGET_CPU_LONG_DISPLACEMENT \ 60 (s390_arch_flags & PF_LONG_DISPLACEMENT) 61 #define TARGET_CPU_LONG_DISPLACEMENT_P(opts) \ 62 (opts->x_s390_arch_flags & PF_LONG_DISPLACEMENT) 63 #define TARGET_CPU_EXTIMM \ 64 (s390_arch_flags & PF_EXTIMM) 65 #define TARGET_CPU_EXTIMM_P(opts) \ 66 (opts->x_s390_arch_flags & PF_EXTIMM) 67 #define TARGET_CPU_DFP \ 68 (s390_arch_flags & PF_DFP) 69 #define TARGET_CPU_DFP_P(opts) \ 70 (opts->x_s390_arch_flags & PF_DFP) 71 #define TARGET_CPU_Z10 \ 72 (s390_arch_flags & PF_Z10) 73 #define TARGET_CPU_Z10_P(opts) \ 74 (opts->x_s390_arch_flags & PF_Z10) 75 #define TARGET_CPU_Z196 \ 76 (s390_arch_flags & PF_Z196) 77 #define TARGET_CPU_Z196_P(opts) \ 78 (opts->x_s390_arch_flags & PF_Z196) 79 #define TARGET_CPU_ZEC12 \ 80 (s390_arch_flags & PF_ZEC12) 81 #define TARGET_CPU_ZEC12_P(opts) \ 82 (opts->x_s390_arch_flags & PF_ZEC12) 83 #define TARGET_CPU_HTM \ 84 (s390_arch_flags & PF_TX) 85 #define TARGET_CPU_HTM_P(opts) \ 86 (opts->x_s390_arch_flags & PF_TX) 87 #define TARGET_CPU_Z13 \ 88 (s390_arch_flags & PF_Z13) 89 #define TARGET_CPU_Z13_P(opts) \ 90 (opts->x_s390_arch_flags & PF_Z13) 91 #define TARGET_CPU_VX \ 92 (s390_arch_flags & PF_VX) 93 #define TARGET_CPU_VX_P(opts) \ 94 (opts->x_s390_arch_flags & PF_VX) 95 #define TARGET_CPU_Z14 \ 96 (s390_arch_flags & PF_Z14) 97 #define TARGET_CPU_Z14_P(opts) \ 98 (opts->x_s390_arch_flags & PF_Z14) 99 #define TARGET_CPU_VXE \ 100 (s390_arch_flags & PF_VXE) 101 #define TARGET_CPU_VXE_P(opts) \ 102 (opts->x_s390_arch_flags & PF_VXE) 103 #define TARGET_CPU_Z15 \ 104 (s390_arch_flags & PF_Z15) 105 #define TARGET_CPU_Z15_P(opts) \ 106 (opts->x_s390_arch_flags & PF_Z15) 107 #define TARGET_CPU_VXE2 \ 108 (s390_arch_flags & PF_VXE2) 109 #define TARGET_CPU_VXE2_P(opts) \ 110 (opts->x_s390_arch_flags & PF_VXE2) 111 112 #define TARGET_HARD_FLOAT_P(opts) (!TARGET_SOFT_FLOAT_P(opts)) 113 114 /* These flags indicate that the generated code should run on a cpu 115 providing the respective hardware facility when run in 116 z/Architecture mode. */ 117 118 #define TARGET_LONG_DISPLACEMENT \ 119 (TARGET_ZARCH && TARGET_CPU_LONG_DISPLACEMENT) 120 #define TARGET_LONG_DISPLACEMENT_P(opts) \ 121 (TARGET_ZARCH_P (opts->x_target_flags) \ 122 && TARGET_CPU_LONG_DISPLACEMENT_P (opts)) 123 #define TARGET_EXTIMM \ 124 (TARGET_ZARCH && TARGET_CPU_EXTIMM) 125 #define TARGET_EXTIMM_P(opts) \ 126 (TARGET_ZARCH_P (opts->x_target_flags) && TARGET_CPU_EXTIMM_P (opts)) 127 #define TARGET_DFP \ 128 (TARGET_ZARCH && TARGET_CPU_DFP && TARGET_HARD_FLOAT) 129 #define TARGET_DFP_P(opts) \ 130 (TARGET_ZARCH_P (opts->x_target_flags) && TARGET_CPU_DFP_P (opts) \ 131 && TARGET_HARD_FLOAT_P (opts->x_target_flags)) 132 #define TARGET_Z10 \ 133 (TARGET_ZARCH && TARGET_CPU_Z10) 134 #define TARGET_Z10_P(opts) \ 135 (TARGET_ZARCH_P (opts->x_target_flags) && TARGET_CPU_Z10_P (opts)) 136 #define TARGET_Z196 \ 137 (TARGET_ZARCH && TARGET_CPU_Z196) 138 #define TARGET_Z196_P(opts) \ 139 (TARGET_ZARCH_P (opts->x_target_flags) && TARGET_CPU_Z196_P (opts)) 140 #define TARGET_ZEC12 \ 141 (TARGET_ZARCH && TARGET_CPU_ZEC12) 142 #define TARGET_ZEC12_P(opts) \ 143 (TARGET_ZARCH_P (opts->x_target_flags) && TARGET_CPU_ZEC12_P (opts)) 144 #define TARGET_HTM (TARGET_OPT_HTM) 145 #define TARGET_HTM_P(opts) (TARGET_OPT_HTM_P (opts->x_target_flags)) 146 #define TARGET_Z13 \ 147 (TARGET_ZARCH && TARGET_CPU_Z13) 148 #define TARGET_Z13_P(opts) \ 149 (TARGET_ZARCH_P (opts->x_target_flags) && TARGET_CPU_Z13_P (opts)) 150 #define TARGET_VX \ 151 (TARGET_ZARCH && TARGET_CPU_VX && TARGET_OPT_VX && TARGET_HARD_FLOAT) 152 #define TARGET_VX_P(opts) \ 153 (TARGET_ZARCH_P (opts->x_target_flags) && TARGET_CPU_VX_P (opts) \ 154 && TARGET_OPT_VX_P (opts->x_target_flags) \ 155 && TARGET_HARD_FLOAT_P (opts->x_target_flags)) 156 #define TARGET_Z14 (TARGET_ZARCH && TARGET_CPU_Z14) 157 #define TARGET_Z14_P(opts) \ 158 (TARGET_ZARCH_P (opts->x_target_flags) && TARGET_CPU_Z14_P (opts)) 159 #define TARGET_VXE \ 160 (TARGET_VX && TARGET_CPU_VXE) 161 #define TARGET_VXE_P(opts) \ 162 (TARGET_VX_P (opts) && TARGET_CPU_VXE_P (opts)) 163 #define TARGET_Z15 (TARGET_ZARCH && TARGET_CPU_Z15) 164 #define TARGET_Z15_P(opts) \ 165 (TARGET_ZARCH_P (opts->x_target_flags) && TARGET_CPU_Z15_P (opts)) 166 #define TARGET_VXE2 \ 167 (TARGET_VX && TARGET_CPU_VXE2) 168 #define TARGET_VXE2_P(opts) \ 169 (TARGET_VX_P (opts) && TARGET_CPU_VXE2_P (opts)) 170 #if defined(HAVE_AS_VECTOR_LOADSTORE_ALIGNMENT_HINTS_ON_Z13) 171 #define TARGET_VECTOR_LOADSTORE_ALIGNMENT_HINTS TARGET_Z13 172 #elif defined(HAVE_AS_VECTOR_LOADSTORE_ALIGNMENT_HINTS) 173 #define TARGET_VECTOR_LOADSTORE_ALIGNMENT_HINTS TARGET_Z14 174 #else 175 #define TARGET_VECTOR_LOADSTORE_ALIGNMENT_HINTS 0 176 #endif 177 178 #ifdef HAVE_AS_MACHINE_MACHINEMODE 179 #define S390_USE_TARGET_ATTRIBUTE 1 180 #else 181 #define S390_USE_TARGET_ATTRIBUTE 0 182 #endif 183 184 #ifdef HAVE_AS_ARCHITECTURE_MODIFIERS 185 #define S390_USE_ARCHITECTURE_MODIFIERS 1 186 #else 187 #define S390_USE_ARCHITECTURE_MODIFIERS 0 188 #endif 189 190 #if S390_USE_TARGET_ATTRIBUTE 191 /* For switching between functions with different target attributes. */ 192 #define SWITCHABLE_TARGET 1 193 #endif 194 195 #define TARGET_SUPPORTS_WIDE_INT 1 196 197 /* Use the ABI introduced with IBM z13: 198 - pass vector arguments <= 16 bytes in VRs 199 - align *all* vector types to 8 bytes */ 200 #define TARGET_VX_ABI TARGET_VX 201 202 #define TARGET_AVOID_CMP_AND_BRANCH (s390_tune == PROCESSOR_2817_Z196) 203 204 /* Issue a write prefetch for the +4 cache line. */ 205 #define TARGET_SETMEM_PREFETCH_DISTANCE 1024 206 207 /* Expand to a C expressions evaluating to true if a setmem to VAL of 208 length LEN should be emitted using prefetch instructions. */ 209 #define TARGET_SETMEM_PFD(VAL,LEN) \ 210 (TARGET_Z10 \ 211 && (s390_tune < PROCESSOR_2964_Z13 || (VAL) != const0_rtx) \ 212 && (!CONST_INT_P (LEN) || INTVAL ((LEN)) > TARGET_SETMEM_PREFETCH_DISTANCE)) 213 214 /* Run-time target specification. */ 215 216 /* Defaults for option flags defined only on some subtargets. */ 217 #ifndef TARGET_TPF_PROFILING 218 #define TARGET_TPF_PROFILING 0 219 #endif 220 221 /* This will be overridden by OS headers. */ 222 #define TARGET_TPF 0 223 224 /* Target CPU builtins. */ 225 #define TARGET_CPU_CPP_BUILTINS() s390_cpu_cpp_builtins (pfile) 226 227 /* Target CPU versions for D. */ 228 #define TARGET_D_CPU_VERSIONS s390_d_target_versions 229 230 #ifdef DEFAULT_TARGET_64BIT 231 #define TARGET_DEFAULT (MASK_64BIT | MASK_ZARCH | MASK_HARD_DFP \ 232 | MASK_OPT_HTM | MASK_OPT_VX) 233 #else 234 #define TARGET_DEFAULT 0 235 #endif 236 237 /* Support for configure-time defaults. 238 The order here is important so that -march doesn't squash the 239 tune values. */ 240 #define OPTION_DEFAULT_SPECS \ 241 { "mode", "%{!mesa:%{!mzarch:-m%(VALUE)}}" }, \ 242 { "tune", "%{!mtune=*:%{!march=*:-mtune=%(VALUE)}}" }, \ 243 { "arch", "%{!march=*:-march=%(VALUE)}" } 244 245 #ifdef __s390__ 246 extern const char *s390_host_detect_local_cpu (int argc, const char **argv); 247 # define EXTRA_SPEC_FUNCTIONS \ 248 { "local_cpu_detect", s390_host_detect_local_cpu }, 249 250 #define MARCH_MTUNE_NATIVE_SPECS \ 251 "%{mtune=native:%<mtune=native %:local_cpu_detect(tune)} " \ 252 "%{march=native:%<march=native" \ 253 " %:local_cpu_detect(arch %{mesa|mzarch:mesa_mzarch})}" 254 #else 255 # define MARCH_MTUNE_NATIVE_SPECS "" 256 #endif 257 258 #ifdef DEFAULT_TARGET_64BIT 259 #define S390_TARGET_BITS_STRING "64" 260 #else 261 #define S390_TARGET_BITS_STRING "31" 262 #endif 263 264 /* Defaulting rules. */ 265 #define DRIVER_SELF_SPECS \ 266 MARCH_MTUNE_NATIVE_SPECS, \ 267 "%{!m31:%{!m64:-m" S390_TARGET_BITS_STRING "}}", \ 268 "%{!mesa:%{!mzarch:%{m31:-mesa}%{m64:-mzarch}}}", \ 269 "%{!march=*:-march=z900}" 270 271 /* Constants needed to control the TEST DATA CLASS (TDC) instruction. */ 272 #define S390_TDC_POSITIVE_ZERO (1 << 11) 273 #define S390_TDC_NEGATIVE_ZERO (1 << 10) 274 #define S390_TDC_POSITIVE_NORMALIZED_BFP_NUMBER (1 << 9) 275 #define S390_TDC_NEGATIVE_NORMALIZED_BFP_NUMBER (1 << 8) 276 #define S390_TDC_POSITIVE_DENORMALIZED_BFP_NUMBER (1 << 7) 277 #define S390_TDC_NEGATIVE_DENORMALIZED_BFP_NUMBER (1 << 6) 278 #define S390_TDC_POSITIVE_INFINITY (1 << 5) 279 #define S390_TDC_NEGATIVE_INFINITY (1 << 4) 280 #define S390_TDC_POSITIVE_QUIET_NAN (1 << 3) 281 #define S390_TDC_NEGATIVE_QUIET_NAN (1 << 2) 282 #define S390_TDC_POSITIVE_SIGNALING_NAN (1 << 1) 283 #define S390_TDC_NEGATIVE_SIGNALING_NAN (1 << 0) 284 285 /* The following values are different for DFP. */ 286 #define S390_TDC_POSITIVE_DENORMALIZED_DFP_NUMBER (1 << 9) 287 #define S390_TDC_NEGATIVE_DENORMALIZED_DFP_NUMBER (1 << 8) 288 #define S390_TDC_POSITIVE_NORMALIZED_DFP_NUMBER (1 << 7) 289 #define S390_TDC_NEGATIVE_NORMALIZED_DFP_NUMBER (1 << 6) 290 291 /* For signbit, the BFP-DFP-difference makes no difference. */ 292 #define S390_TDC_SIGNBIT_SET (S390_TDC_NEGATIVE_ZERO \ 293 | S390_TDC_NEGATIVE_NORMALIZED_BFP_NUMBER \ 294 | S390_TDC_NEGATIVE_DENORMALIZED_BFP_NUMBER\ 295 | S390_TDC_NEGATIVE_INFINITY \ 296 | S390_TDC_NEGATIVE_QUIET_NAN \ 297 | S390_TDC_NEGATIVE_SIGNALING_NAN ) 298 299 #define S390_TDC_INFINITY (S390_TDC_POSITIVE_INFINITY \ 300 | S390_TDC_NEGATIVE_INFINITY ) 301 302 /* Target machine storage layout. */ 303 304 /* Everything is big-endian. */ 305 #define BITS_BIG_ENDIAN 1 306 #define BYTES_BIG_ENDIAN 1 307 #define WORDS_BIG_ENDIAN 1 308 309 #define STACK_SIZE_MODE (Pmode) 310 311 #ifndef IN_LIBGCC2 312 313 /* Width of a word, in units (bytes). */ 314 #define UNITS_PER_WORD (TARGET_ZARCH ? 8 : 4) 315 316 /* Width of a pointer. To be used instead of UNITS_PER_WORD in 317 ABI-relevant contexts. This always matches 318 GET_MODE_SIZE (Pmode). */ 319 #define UNITS_PER_LONG (TARGET_64BIT ? 8 : 4) 320 #define MIN_UNITS_PER_WORD 4 321 #define MAX_BITS_PER_WORD 64 322 #else 323 324 /* In libgcc, UNITS_PER_WORD has ABI-relevant effects, e.g. whether 325 the library should export TImode functions or not. Thus, we have 326 to redefine UNITS_PER_WORD depending on __s390x__ for libgcc. */ 327 #ifdef __s390x__ 328 #define UNITS_PER_WORD 8 329 #else 330 #define UNITS_PER_WORD 4 331 #endif 332 #endif 333 334 /* Width of a pointer, in bits. */ 335 #define POINTER_SIZE (TARGET_64BIT ? 64 : 32) 336 337 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ 338 #define PARM_BOUNDARY (TARGET_64BIT ? 64 : 32) 339 340 /* Boundary (in *bits*) on which stack pointer should be aligned. */ 341 #define STACK_BOUNDARY 64 342 343 /* Allocation boundary (in *bits*) for the code of a function. */ 344 #define FUNCTION_BOUNDARY 64 345 346 /* There is no point aligning anything to a rounder boundary than this. */ 347 #define BIGGEST_ALIGNMENT 64 348 349 /* Alignment of field after `int : 0' in a structure. */ 350 #define EMPTY_FIELD_BOUNDARY 32 351 352 /* Alignment on even addresses for LARL instruction. */ 353 #define DATA_ABI_ALIGNMENT(TYPE, ALIGN) (ALIGN) < 16 ? 16 : (ALIGN) 354 355 /* Alignment is not required by the hardware. */ 356 #define STRICT_ALIGNMENT 0 357 358 /* Mode of stack savearea. 359 FUNCTION is VOIDmode because calling convention maintains SP. 360 BLOCK needs Pmode for SP. 361 NONLOCAL needs twice Pmode to maintain both backchain and SP. */ 362 #define STACK_SAVEAREA_MODE(LEVEL) \ 363 ((LEVEL) == SAVE_FUNCTION ? VOIDmode \ 364 : (LEVEL) == SAVE_NONLOCAL ? (TARGET_64BIT ? OImode : TImode) : Pmode) 365 366 367 /* Type layout. */ 368 369 /* Sizes in bits of the source language data types. */ 370 #define SHORT_TYPE_SIZE 16 371 #define INT_TYPE_SIZE 32 372 #define LONG_TYPE_SIZE (TARGET_64BIT ? 64 : 32) 373 #define LONG_LONG_TYPE_SIZE 64 374 #define FLOAT_TYPE_SIZE 32 375 #define DOUBLE_TYPE_SIZE 64 376 #define LONG_DOUBLE_TYPE_SIZE (TARGET_LONG_DOUBLE_128 ? 128 : 64) 377 378 /* Work around target_flags dependency in ada/targtyps.c. */ 379 #define WIDEST_HARDWARE_FP_SIZE 64 380 381 /* We use "unsigned char" as default. */ 382 #define DEFAULT_SIGNED_CHAR 0 383 384 385 /* Register usage. */ 386 387 /* We have 16 general purpose registers (registers 0-15), 388 and 16 floating point registers (registers 16-31). 389 (On non-IEEE machines, we have only 4 fp registers.) 390 391 Amongst the general purpose registers, some are used 392 for specific purposes: 393 GPR 11: Hard frame pointer (if needed) 394 GPR 12: Global offset table pointer (if needed) 395 GPR 13: Literal pool base register 396 GPR 14: Return address register 397 GPR 15: Stack pointer 398 399 Registers 32-35 are 'fake' hard registers that do not 400 correspond to actual hardware: 401 Reg 32: Argument pointer 402 Reg 33: Condition code 403 Reg 34: Frame pointer 404 Reg 35: Return address pointer 405 406 Registers 36 and 37 are mapped to access registers 407 0 and 1, used to implement thread-local storage. 408 409 Reg 38-53: Vector registers v16-v31 */ 410 411 #define FIRST_PSEUDO_REGISTER 54 412 413 /* Standard register usage. */ 414 #define GENERAL_REGNO_P(N) ((int)(N) >= 0 && (N) < 16) 415 #define ADDR_REGNO_P(N) ((N) >= 1 && (N) < 16) 416 #define FP_REGNO_P(N) ((N) >= 16 && (N) < 32) 417 #define CC_REGNO_P(N) ((N) == 33) 418 #define FRAME_REGNO_P(N) ((N) == 32 || (N) == 34 || (N) == 35) 419 #define ACCESS_REGNO_P(N) ((N) == 36 || (N) == 37) 420 #define VECTOR_NOFP_REGNO_P(N) ((N) >= 38 && (N) <= 53) 421 #define VECTOR_REGNO_P(N) (FP_REGNO_P (N) || VECTOR_NOFP_REGNO_P (N)) 422 423 #define GENERAL_REG_P(X) (REG_P (X) && GENERAL_REGNO_P (REGNO (X))) 424 #define ADDR_REG_P(X) (REG_P (X) && ADDR_REGNO_P (REGNO (X))) 425 #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X))) 426 #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X))) 427 #define FRAME_REG_P(X) (REG_P (X) && FRAME_REGNO_P (REGNO (X))) 428 #define ACCESS_REG_P(X) (REG_P (X) && ACCESS_REGNO_P (REGNO (X))) 429 #define VECTOR_NOFP_REG_P(X) (REG_P (X) && VECTOR_NOFP_REGNO_P (REGNO (X))) 430 #define VECTOR_REG_P(X) (REG_P (X) && VECTOR_REGNO_P (REGNO (X))) 431 432 /* Set up fixed registers and calling convention: 433 434 GPRs 0-5 are always call-clobbered, 435 GPRs 6-15 are always call-saved. 436 GPR 12 is fixed if used as GOT pointer. 437 GPR 13 is always fixed (as literal pool pointer). 438 GPR 14 is always fixed on S/390 machines (as return address). 439 GPR 15 is always fixed (as stack pointer). 440 The 'fake' hard registers are call-clobbered and fixed. 441 The access registers are call-saved and fixed. 442 443 On 31-bit, FPRs 18-19 are call-clobbered; 444 on 64-bit, FPRs 24-31 are call-clobbered. 445 The remaining FPRs are call-saved. 446 447 All non-FP vector registers are call-clobbered v16-v31. */ 448 449 #define FIXED_REGISTERS \ 450 { 0, 0, 0, 0, \ 451 0, 0, 0, 0, \ 452 0, 0, 0, 0, \ 453 0, 1, 1, 1, \ 454 0, 0, 0, 0, \ 455 0, 0, 0, 0, \ 456 0, 0, 0, 0, \ 457 0, 0, 0, 0, \ 458 1, 1, 1, 1, \ 459 1, 1, \ 460 0, 0, 0, 0, \ 461 0, 0, 0, 0, \ 462 0, 0, 0, 0, \ 463 0, 0, 0, 0 } 464 465 #define CALL_REALLY_USED_REGISTERS \ 466 { 1, 1, 1, 1, /* r0 - r15 */ \ 467 1, 1, 0, 0, \ 468 0, 0, 0, 0, \ 469 0, 0, 0, 0, \ 470 1, 1, 1, 1, /* f0 (16) - f15 (31) */ \ 471 1, 1, 1, 1, \ 472 1, 1, 1, 1, \ 473 1, 1, 1, 1, \ 474 1, 1, 1, 1, /* arg, cc, fp, ret addr */ \ 475 0, 0, /* a0 (36), a1 (37) */ \ 476 1, 1, 1, 1, /* v16 (38) - v23 (45) */ \ 477 1, 1, 1, 1, \ 478 1, 1, 1, 1, /* v24 (46) - v31 (53) */ \ 479 1, 1, 1, 1 } 480 481 /* Preferred register allocation order. */ 482 #define REG_ALLOC_ORDER \ 483 { 1, 2, 3, 4, 5, 0, 12, 11, 10, 9, 8, 7, 6, 14, 13, \ 484 16, 17, 18, 19, 20, 21, 22, 23, \ 485 24, 25, 26, 27, 28, 29, 30, 31, \ 486 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, \ 487 15, 32, 33, 34, 35, 36, 37 } 488 489 490 #define HARD_REGNO_RENAME_OK(FROM, TO) \ 491 s390_hard_regno_rename_ok ((FROM), (TO)) 492 493 /* Maximum number of registers to represent a value of mode MODE 494 in a register of class CLASS. */ 495 #define CLASS_MAX_NREGS(CLASS, MODE) \ 496 s390_class_max_nregs ((CLASS), (MODE)) 497 498 /* We can reverse a CC mode safely if we know whether it comes from a 499 floating point compare or not. With the vector modes it is encoded 500 as part of the mode. 501 FIXME: It might make sense to do this for other cc modes as well. */ 502 #define REVERSIBLE_CC_MODE(MODE) \ 503 ((MODE) == CCVIALLmode || (MODE) == CCVIANYmode \ 504 || (MODE) == CCVFALLmode || (MODE) == CCVFANYmode) 505 506 /* Given a condition code and a mode, return the inverse condition. */ 507 #define REVERSE_CONDITION(CODE, MODE) s390_reverse_condition (MODE, CODE) 508 509 510 /* Register classes. */ 511 512 /* We use the following register classes: 513 GENERAL_REGS All general purpose registers 514 ADDR_REGS All general purpose registers except %r0 515 (These registers can be used in address generation) 516 FP_REGS All floating point registers 517 CC_REGS The condition code register 518 ACCESS_REGS The access registers 519 520 GENERAL_FP_REGS Union of GENERAL_REGS and FP_REGS 521 ADDR_FP_REGS Union of ADDR_REGS and FP_REGS 522 GENERAL_CC_REGS Union of GENERAL_REGS and CC_REGS 523 ADDR_CC_REGS Union of ADDR_REGS and CC_REGS 524 525 NO_REGS No registers 526 ALL_REGS All registers 527 528 Note that the 'fake' frame pointer and argument pointer registers 529 are included amongst the address registers here. */ 530 531 enum reg_class 532 { 533 NO_REGS, CC_REGS, ADDR_REGS, GENERAL_REGS, ACCESS_REGS, 534 ADDR_CC_REGS, GENERAL_CC_REGS, 535 FP_REGS, ADDR_FP_REGS, GENERAL_FP_REGS, 536 VEC_REGS, ADDR_VEC_REGS, GENERAL_VEC_REGS, 537 ALL_REGS, LIM_REG_CLASSES 538 }; 539 #define N_REG_CLASSES (int) LIM_REG_CLASSES 540 541 #define REG_CLASS_NAMES \ 542 { "NO_REGS", "CC_REGS", "ADDR_REGS", "GENERAL_REGS", "ACCESS_REGS", \ 543 "ADDR_CC_REGS", "GENERAL_CC_REGS", \ 544 "FP_REGS", "ADDR_FP_REGS", "GENERAL_FP_REGS", \ 545 "VEC_REGS", "ADDR_VEC_REGS", "GENERAL_VEC_REGS", \ 546 "ALL_REGS" } 547 548 /* Class -> register mapping. */ 549 #define REG_CLASS_CONTENTS \ 550 { \ 551 { 0x00000000, 0x00000000 }, /* NO_REGS */ \ 552 { 0x00000000, 0x00000002 }, /* CC_REGS */ \ 553 { 0x0000fffe, 0x0000000d }, /* ADDR_REGS */ \ 554 { 0x0000ffff, 0x0000000d }, /* GENERAL_REGS */ \ 555 { 0x00000000, 0x00000030 }, /* ACCESS_REGS */ \ 556 { 0x0000fffe, 0x0000000f }, /* ADDR_CC_REGS */ \ 557 { 0x0000ffff, 0x0000000f }, /* GENERAL_CC_REGS */ \ 558 { 0xffff0000, 0x00000000 }, /* FP_REGS */ \ 559 { 0xfffffffe, 0x0000000d }, /* ADDR_FP_REGS */ \ 560 { 0xffffffff, 0x0000000d }, /* GENERAL_FP_REGS */ \ 561 { 0xffff0000, 0x003fffc0 }, /* VEC_REGS */ \ 562 { 0xfffffffe, 0x003fffcd }, /* ADDR_VEC_REGS */ \ 563 { 0xffffffff, 0x003fffcd }, /* GENERAL_VEC_REGS */ \ 564 { 0xffffffff, 0x003fffff }, /* ALL_REGS */ \ 565 } 566 567 /* In some case register allocation order is not enough for IRA to 568 generate a good code. The following macro (if defined) increases 569 cost of REGNO for a pseudo approximately by pseudo usage frequency 570 multiplied by the macro value. 571 572 We avoid usage of BASE_REGNUM by nonzero macro value because the 573 reload can decide not to use the hard register because some 574 constant was forced to be in memory. */ 575 #define IRA_HARD_REGNO_ADD_COST_MULTIPLIER(regno) \ 576 ((regno) != BASE_REGNUM ? 0.0 : 0.5) 577 578 /* Register -> class mapping. */ 579 extern const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER]; 580 #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO]) 581 582 /* ADDR_REGS can be used as base or index register. */ 583 #define INDEX_REG_CLASS ADDR_REGS 584 #define BASE_REG_CLASS ADDR_REGS 585 586 /* Check whether REGNO is a hard register of the suitable class 587 or a pseudo register currently allocated to one such. */ 588 #define REGNO_OK_FOR_INDEX_P(REGNO) \ 589 (((REGNO) < FIRST_PSEUDO_REGISTER \ 590 && REGNO_REG_CLASS ((REGNO)) == ADDR_REGS) \ 591 || ADDR_REGNO_P (reg_renumber[REGNO])) 592 #define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_INDEX_P (REGNO) 593 594 595 /* Stack layout and calling conventions. */ 596 597 /* Our stack grows from higher to lower addresses. However, local variables 598 are accessed by positive offsets, and function arguments are stored at 599 increasing addresses. */ 600 #define STACK_GROWS_DOWNWARD 1 601 #define FRAME_GROWS_DOWNWARD 1 602 /* #undef ARGS_GROW_DOWNWARD */ 603 604 /* The basic stack layout looks like this: the stack pointer points 605 to the register save area for called functions. Above that area 606 is the location to place outgoing arguments. Above those follow 607 dynamic allocations (alloca), and finally the local variables. */ 608 609 /* Offset from stack-pointer to first location of outgoing args. */ 610 #define STACK_POINTER_OFFSET (TARGET_64BIT ? 160 : 96) 611 612 /* Offset from the stack pointer register to an item dynamically 613 allocated on the stack, e.g., by `alloca'. */ 614 #define STACK_DYNAMIC_OFFSET(FUNDECL) \ 615 (STACK_POINTER_OFFSET + crtl->outgoing_args_size) 616 617 /* Offset of first parameter from the argument pointer register value. 618 We have a fake argument pointer register that points directly to 619 the argument area. */ 620 #define FIRST_PARM_OFFSET(FNDECL) 0 621 622 /* Defining this macro makes __builtin_frame_address(0) and 623 __builtin_return_address(0) work with -fomit-frame-pointer. */ 624 #define INITIAL_FRAME_ADDRESS_RTX \ 625 (plus_constant (Pmode, arg_pointer_rtx, -STACK_POINTER_OFFSET)) 626 627 /* The return address of the current frame is retrieved 628 from the initial value of register RETURN_REGNUM. 629 For frames farther back, we use the stack slot where 630 the corresponding RETURN_REGNUM register was saved. */ 631 #define DYNAMIC_CHAIN_ADDRESS(FRAME) \ 632 (TARGET_PACKED_STACK ? \ 633 plus_constant (Pmode, (FRAME), \ 634 STACK_POINTER_OFFSET - UNITS_PER_LONG) : (FRAME)) 635 636 /* For -mpacked-stack this adds 160 - 8 (96 - 4) to the output of 637 builtin_frame_address. Otherwise arg pointer - 638 STACK_POINTER_OFFSET would be returned for 639 __builtin_frame_address(0) what might result in an address pointing 640 somewhere into the middle of the local variables since the packed 641 stack layout generally does not need all the bytes in the register 642 save area. */ 643 #define FRAME_ADDR_RTX(FRAME) \ 644 DYNAMIC_CHAIN_ADDRESS ((FRAME)) 645 646 #define RETURN_ADDR_RTX(COUNT, FRAME) \ 647 s390_return_addr_rtx ((COUNT), DYNAMIC_CHAIN_ADDRESS ((FRAME))) 648 649 /* In 31-bit mode, we need to mask off the high bit of return addresses. */ 650 #define MASK_RETURN_ADDR (TARGET_64BIT ? constm1_rtx : GEN_INT (0x7fffffff)) 651 652 653 /* Exception handling. */ 654 655 /* Describe calling conventions for DWARF-2 exception handling. */ 656 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, RETURN_REGNUM) 657 #define INCOMING_FRAME_SP_OFFSET STACK_POINTER_OFFSET 658 #define DWARF_FRAME_RETURN_COLUMN 14 659 660 /* Describe how we implement __builtin_eh_return. */ 661 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 6 : INVALID_REGNUM) 662 #define EH_RETURN_HANDLER_RTX gen_rtx_MEM (Pmode, return_address_pointer_rtx) 663 664 /* Select a format to encode pointers in exception handling data. */ 665 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ 666 (flag_pic \ 667 ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4 \ 668 : DW_EH_PE_absptr) 669 670 /* Register save slot alignment. */ 671 #define DWARF_CIE_DATA_ALIGNMENT (-UNITS_PER_LONG) 672 673 /* Let the assembler generate debug line info. */ 674 #define DWARF2_ASM_LINE_DEBUG_INFO 1 675 676 /* Define the dwarf register mapping. 677 v16-v31 -> 68-83 678 rX -> X otherwise */ 679 #define DBX_REGISTER_NUMBER(regno) \ 680 (((regno) >= 38 && (regno) <= 53) ? (regno) + 30 : (regno)) 681 682 /* Frame registers. */ 683 684 #define STACK_POINTER_REGNUM 15 685 #define FRAME_POINTER_REGNUM 34 686 #define HARD_FRAME_POINTER_REGNUM 11 687 #define ARG_POINTER_REGNUM 32 688 #define RETURN_ADDRESS_POINTER_REGNUM 35 689 690 /* The static chain must be call-clobbered, but not used for 691 function argument passing. As register 1 is clobbered by 692 the trampoline code, we only have one option. */ 693 #define STATIC_CHAIN_REGNUM 0 694 695 /* Number of hardware registers that go into the DWARF-2 unwind info. 696 To avoid ABI incompatibility, this number must not change even as 697 'fake' hard registers are added or removed. */ 698 #define DWARF_FRAME_REGISTERS 34 699 700 701 /* Frame pointer and argument pointer elimination. */ 702 703 #define ELIMINABLE_REGS \ 704 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ 705 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \ 706 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ 707 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \ 708 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ 709 { RETURN_ADDRESS_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \ 710 { BASE_REGNUM, BASE_REGNUM }} 711 712 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 713 (OFFSET) = s390_initial_elimination_offset ((FROM), (TO)) 714 715 716 /* Stack arguments. */ 717 718 /* We need current_function_outgoing_args to be valid. */ 719 #define ACCUMULATE_OUTGOING_ARGS 1 720 721 722 /* Register arguments. */ 723 724 typedef struct s390_arg_structure 725 { 726 int gprs; /* gpr so far */ 727 int fprs; /* fpr so far */ 728 int vrs; /* vr so far */ 729 } 730 CUMULATIVE_ARGS; 731 732 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, NN, N_NAMED_ARGS) \ 733 ((CUM).gprs=0, (CUM).fprs=0, (CUM).vrs=0) 734 735 #define FIRST_VEC_ARG_REGNO 46 736 #define LAST_VEC_ARG_REGNO 53 737 738 /* Arguments can be placed in general registers 2 to 6, or in floating 739 point registers 0 and 2 for 31 bit and fprs 0, 2, 4 and 6 for 64 740 bit. */ 741 #define FUNCTION_ARG_REGNO_P(N) \ 742 (((N) >=2 && (N) < 7) || (N) == 16 || (N) == 17 \ 743 || (TARGET_64BIT && ((N) == 18 || (N) == 19)) \ 744 || (TARGET_VX && ((N) >= FIRST_VEC_ARG_REGNO && (N) <= LAST_VEC_ARG_REGNO))) 745 746 747 /* Only gpr 2, fpr 0, and v24 are ever used as return registers. */ 748 #define FUNCTION_VALUE_REGNO_P(N) \ 749 ((N) == 2 || (N) == 16 \ 750 || (TARGET_VX && (N) == FIRST_VEC_ARG_REGNO)) 751 752 753 /* Function entry and exit. */ 754 755 /* When returning from a function, the stack pointer does not matter. */ 756 #define EXIT_IGNORE_STACK 1 757 758 759 /* Profiling. */ 760 761 #define FUNCTION_PROFILER(FILE, LABELNO) \ 762 s390_function_profiler ((FILE), ((LABELNO))) 763 764 #define PROFILE_BEFORE_PROLOGUE 1 765 766 767 /* Trampolines for nested functions. */ 768 769 #define TRAMPOLINE_SIZE (TARGET_64BIT ? 32 : 16) 770 #define TRAMPOLINE_ALIGNMENT BITS_PER_WORD 771 772 /* Addressing modes, and classification of registers for them. */ 773 774 /* Recognize any constant value that is a valid address. */ 775 #define CONSTANT_ADDRESS_P(X) 0 776 777 /* Maximum number of registers that can appear in a valid memory address. */ 778 #define MAX_REGS_PER_ADDRESS 2 779 780 /* This definition replaces the formerly used 'm' constraint with a 781 different constraint letter in order to avoid changing semantics of 782 the 'm' constraint when accepting new address formats in 783 TARGET_LEGITIMATE_ADDRESS_P. The constraint letter defined here 784 must not be used in insn definitions or inline assemblies. */ 785 #define TARGET_MEM_CONSTRAINT 'e' 786 787 /* Try a machine-dependent way of reloading an illegitimate address 788 operand. If we find one, push the reload and jump to WIN. This 789 macro is used in only one place: `find_reloads_address' in reload.c. */ 790 #define LEGITIMIZE_RELOAD_ADDRESS(AD, MODE, OPNUM, TYPE, IND, WIN) \ 791 do { \ 792 rtx new_rtx = legitimize_reload_address ((AD), (MODE), \ 793 (OPNUM), (int)(TYPE)); \ 794 if (new_rtx) \ 795 { \ 796 (AD) = new_rtx; \ 797 goto WIN; \ 798 } \ 799 } while (0) 800 801 /* Helper macro for s390.c and s390.md to check for symbolic constants. */ 802 #define SYMBOLIC_CONST(X) \ 803 (GET_CODE (X) == SYMBOL_REF \ 804 || GET_CODE (X) == LABEL_REF \ 805 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X))) 806 807 #define TLS_SYMBOLIC_CONST(X) \ 808 ((GET_CODE (X) == SYMBOL_REF && tls_symbolic_operand (X)) \ 809 || (GET_CODE (X) == CONST && tls_symbolic_reference_mentioned_p (X))) 810 811 812 /* Condition codes. */ 813 814 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, 815 return the mode to be used for the comparison. */ 816 #define SELECT_CC_MODE(OP, X, Y) s390_select_ccmode ((OP), (X), (Y)) 817 818 /* Relative costs of operations. */ 819 820 /* A C expression for the cost of a branch instruction. A value of 1 821 is the default; other values are interpreted relative to that. */ 822 #define BRANCH_COST(speed_p, predictable_p) s390_branch_cost 823 824 /* Nonzero if access to memory by bytes is slow and undesirable. */ 825 #define SLOW_BYTE_ACCESS 1 826 827 /* An integer expression for the size in bits of the largest integer machine 828 mode that should actually be used. We allow pairs of registers. */ 829 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_64BIT ? TImode : DImode) 830 831 /* The maximum number of bytes that a single instruction can move quickly 832 between memory and registers or between two memory locations. */ 833 #define MOVE_MAX (TARGET_ZARCH ? 16 : 8) 834 #define MOVE_MAX_PIECES (TARGET_ZARCH ? 8 : 4) 835 #define MAX_MOVE_MAX 16 836 837 /* Don't perform CSE on function addresses. */ 838 #define NO_FUNCTION_CSE 1 839 840 /* This value is used in tree-sra to decide whether it might benefical 841 to split a struct move into several word-size moves. For S/390 842 only small values make sense here since struct moves are relatively 843 cheap thanks to mvc so the small default value chosen for archs 844 with memmove patterns should be ok. But this value is multiplied 845 in tree-sra with UNITS_PER_WORD to make a decision so we adjust it 846 here to compensate for that factor since mvc costs exactly the same 847 on 31 and 64 bit. */ 848 #define MOVE_RATIO(speed) (TARGET_64BIT? 2 : 4) 849 850 851 /* Sections. */ 852 853 /* Output before read-only data. */ 854 #define TEXT_SECTION_ASM_OP ".text" 855 856 /* Output before writable (initialized) data. */ 857 #define DATA_SECTION_ASM_OP ".data" 858 859 /* Output before writable (uninitialized) data. */ 860 #define BSS_SECTION_ASM_OP ".bss" 861 862 /* S/390 constant pool breaks the devices in crtstuff.c to control section 863 in where code resides. We have to write it as asm code. */ 864 #ifndef __s390x__ 865 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ 866 asm (SECTION_OP "\n\ 867 bras\t%r2,1f\n\ 868 0: .long\t" USER_LABEL_PREFIX #FUNC " - 0b\n\ 869 1: l\t%r3,0(%r2)\n\ 870 bas\t%r14,0(%r3,%r2)\n\ 871 .previous"); 872 #endif 873 874 875 /* Position independent code. */ 876 877 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 12 : INVALID_REGNUM) 878 879 #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X) 880 881 #ifndef TARGET_DEFAULT_PIC_DATA_IS_TEXT_RELATIVE 882 #define TARGET_DEFAULT_PIC_DATA_IS_TEXT_RELATIVE 1 883 #endif 884 885 886 /* Assembler file format. */ 887 888 /* Character to start a comment. */ 889 #define ASM_COMMENT_START "#" 890 891 /* Declare an uninitialized external linkage data object. */ 892 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ 893 asm_output_aligned_bss ((FILE), (DECL), (NAME), (SIZE), (ALIGN)) 894 895 /* Globalizing directive for a label. */ 896 #define GLOBAL_ASM_OP ".globl " 897 898 /* Advance the location counter to a multiple of 2**LOG bytes. */ 899 #define ASM_OUTPUT_ALIGN(FILE, LOG) \ 900 if ((LOG)) fprintf ((FILE), "\t.align\t%d\n", 1 << (LOG)) 901 902 /* Advance the location counter by SIZE bytes. */ 903 #define ASM_OUTPUT_SKIP(FILE, SIZE) \ 904 fprintf ((FILE), "\t.set\t.,.+" HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE)) 905 906 /* The LOCAL_LABEL_PREFIX variable is used by dbxelf.h. */ 907 #define LOCAL_LABEL_PREFIX "." 908 909 #define LABEL_ALIGN(LABEL) \ 910 s390_label_align ((LABEL)) 911 912 /* How to refer to registers in assembler output. This sequence is 913 indexed by compiler's hard-register-number (see above). */ 914 #define REGISTER_NAMES \ 915 { "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", \ 916 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", \ 917 "%f0", "%f2", "%f4", "%f6", "%f1", "%f3", "%f5", "%f7", \ 918 "%f8", "%f10", "%f12", "%f14", "%f9", "%f11", "%f13", "%f15", \ 919 "%ap", "%cc", "%fp", "%rp", "%a0", "%a1", \ 920 "%v16", "%v18", "%v20", "%v22", "%v17", "%v19", "%v21", "%v23", \ 921 "%v24", "%v26", "%v28", "%v30", "%v25", "%v27", "%v29", "%v31" \ 922 } 923 924 #define ADDITIONAL_REGISTER_NAMES \ 925 { { "v0", 16 }, { "v2", 17 }, { "v4", 18 }, { "v6", 19 }, \ 926 { "v1", 20 }, { "v3", 21 }, { "v5", 22 }, { "v7", 23 }, \ 927 { "v8", 24 }, { "v10", 25 }, { "v12", 26 }, { "v14", 27 }, \ 928 { "v9", 28 }, { "v11", 29 }, { "v13", 30 }, { "v15", 31 } }; 929 930 /* Print operand X (an rtx) in assembler syntax to file FILE. */ 931 #define PRINT_OPERAND(FILE, X, CODE) print_operand ((FILE), (X), (CODE)) 932 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address ((FILE), (ADDR)) 933 934 /* Output an element of a case-vector that is absolute. */ 935 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 936 do { \ 937 char buf[32]; \ 938 fputs (integer_asm_op (UNITS_PER_LONG, TRUE), (FILE)); \ 939 ASM_GENERATE_INTERNAL_LABEL (buf, "L", (VALUE)); \ 940 assemble_name ((FILE), buf); \ 941 fputc ('\n', (FILE)); \ 942 } while (0) 943 944 /* Output an element of a case-vector that is relative. */ 945 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 946 do { \ 947 char buf[32]; \ 948 fputs (integer_asm_op (UNITS_PER_LONG, TRUE), (FILE)); \ 949 ASM_GENERATE_INTERNAL_LABEL (buf, "L", (VALUE)); \ 950 assemble_name ((FILE), buf); \ 951 fputc ('-', (FILE)); \ 952 ASM_GENERATE_INTERNAL_LABEL (buf, "L", (REL)); \ 953 assemble_name ((FILE), buf); \ 954 fputc ('\n', (FILE)); \ 955 } while (0) 956 957 /* Mark the return register as used by the epilogue so that we can 958 use it in unadorned (return) and (simple_return) instructions. */ 959 #define EPILOGUE_USES(REGNO) ((REGNO) == RETURN_REGNUM) 960 961 #undef ASM_OUTPUT_FUNCTION_LABEL 962 #define ASM_OUTPUT_FUNCTION_LABEL(FILE, NAME, DECL) \ 963 s390_asm_output_function_label ((FILE), (NAME), (DECL)) 964 965 #if S390_USE_TARGET_ATTRIBUTE 966 /* Hook to output .machine and .machinemode at start of function. */ 967 #undef ASM_OUTPUT_FUNCTION_PREFIX 968 #define ASM_OUTPUT_FUNCTION_PREFIX s390_asm_output_function_prefix 969 970 /* Hook to output .machine and .machinemode at end of function. */ 971 #undef ASM_DECLARE_FUNCTION_SIZE 972 #define ASM_DECLARE_FUNCTION_SIZE s390_asm_declare_function_size 973 #endif 974 975 /* Miscellaneous parameters. */ 976 977 /* Specify the machine mode that this machine uses for the index in the 978 tablejump instruction. */ 979 #define CASE_VECTOR_MODE (TARGET_64BIT ? DImode : SImode) 980 981 /* Specify the machine mode that pointers have. 982 After generation of rtl, the compiler makes no further distinction 983 between pointers and any other objects of this machine mode. */ 984 #define Pmode (TARGET_64BIT ? DImode : SImode) 985 986 /* This is -1 for "pointer mode" extend. See ptr_extend in s390.md. */ 987 #define POINTERS_EXTEND_UNSIGNED -1 988 989 /* A function address in a call instruction is a byte address (for 990 indexing purposes) so give the MEM rtx a byte's mode. */ 991 #define FUNCTION_MODE QImode 992 993 /* Specify the value which is used when clz operand is zero. */ 994 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 64, 1) 995 996 /* Machine-specific symbol_ref flags. */ 997 #define SYMBOL_FLAG_ALIGN_SHIFT SYMBOL_FLAG_MACH_DEP_SHIFT 998 #define SYMBOL_FLAG_ALIGN_MASK \ 999 ((SYMBOL_FLAG_MACH_DEP << 0) | (SYMBOL_FLAG_MACH_DEP << 1)) 1000 1001 #define SYMBOL_FLAG_SET_ALIGN(X, A) \ 1002 (SYMBOL_REF_FLAGS (X) = (SYMBOL_REF_FLAGS (X) & ~SYMBOL_FLAG_ALIGN_MASK) \ 1003 | (A << SYMBOL_FLAG_ALIGN_SHIFT)) 1004 1005 #define SYMBOL_FLAG_GET_ALIGN(X) \ 1006 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_ALIGN_MASK) >> SYMBOL_FLAG_ALIGN_SHIFT) 1007 1008 /* Helpers to access symbol_ref flags. They are used in 1009 check_symref_alignment() and larl_operand to detect if the 1010 available alignment matches the required one. We do not use 1011 a positive check like _ALIGN2 because in that case we would have 1012 to annotate every symbol_ref. However, we only want to touch 1013 the symbol_refs that can be misaligned and assume that the others 1014 are correctly aligned. Hence, if a symbol_ref does not have 1015 a _NOTALIGN flag it is supposed to be correctly aligned. */ 1016 #define SYMBOL_FLAG_SET_NOTALIGN2(X) SYMBOL_FLAG_SET_ALIGN((X), 1) 1017 #define SYMBOL_FLAG_SET_NOTALIGN4(X) SYMBOL_FLAG_SET_ALIGN((X), 2) 1018 #define SYMBOL_FLAG_SET_NOTALIGN8(X) SYMBOL_FLAG_SET_ALIGN((X), 3) 1019 1020 #define SYMBOL_FLAG_NOTALIGN2_P(X) (SYMBOL_FLAG_GET_ALIGN(X) == 1) 1021 #define SYMBOL_FLAG_NOTALIGN4_P(X) (SYMBOL_FLAG_GET_ALIGN(X) == 2 \ 1022 || SYMBOL_FLAG_GET_ALIGN(X) == 1) 1023 #define SYMBOL_FLAG_NOTALIGN8_P(X) (SYMBOL_FLAG_GET_ALIGN(X) == 3 \ 1024 || SYMBOL_FLAG_GET_ALIGN(X) == 2 \ 1025 || SYMBOL_FLAG_GET_ALIGN(X) == 1) 1026 1027 /* Check whether integer displacement is in range for a short displacement. */ 1028 #define SHORT_DISP_IN_RANGE(d) ((d) >= 0 && (d) <= 4095) 1029 1030 /* Check whether integer displacement is in range. */ 1031 #define DISP_IN_RANGE(d) \ 1032 (TARGET_LONG_DISPLACEMENT \ 1033 ? ((d) >= -524288 && (d) <= 524287) \ 1034 : SHORT_DISP_IN_RANGE(d)) 1035 1036 /* Reads can reuse write prefetches, used by tree-ssa-prefetch-loops.c. */ 1037 #define READ_CAN_USE_WRITE_PREFETCH 1 1038 1039 extern const int processor_flags_table[]; 1040 1041 struct s390_processor 1042 { 1043 /* The preferred name to be used in user visible output. */ 1044 const char *const name; 1045 /* CPU name as it should be passed to Binutils via .machine */ 1046 const char *const binutils_name; 1047 const enum processor_type processor; 1048 const struct processor_costs *cost; 1049 int arch_level; 1050 }; 1051 1052 extern const struct s390_processor processor_table[]; 1053 1054 /* The truth element value for vector comparisons. Our instructions 1055 always generate -1 in that case. */ 1056 #define VECTOR_STORE_FLAG_VALUE(MODE) CONSTM1_RTX (GET_MODE_INNER (MODE)) 1057 1058 /* Target pragma. */ 1059 1060 /* resolve_overloaded_builtin cannot be defined the normal way since 1061 it is defined in code which technically belongs to the 1062 front-end. */ 1063 #define REGISTER_TARGET_PRAGMAS() \ 1064 do { \ 1065 s390_register_target_pragmas (); \ 1066 } while (0) 1067 1068 #ifndef USED_FOR_TARGET 1069 /* The following structure is embedded in the machine 1070 specific part of struct function. */ 1071 1072 struct GTY (()) s390_frame_layout 1073 { 1074 /* Offset within stack frame. */ 1075 HOST_WIDE_INT gprs_offset; 1076 HOST_WIDE_INT f0_offset; 1077 HOST_WIDE_INT f4_offset; 1078 HOST_WIDE_INT f8_offset; 1079 HOST_WIDE_INT backchain_offset; 1080 1081 /* Number of first and last gpr where slots in the register 1082 save area are reserved for. */ 1083 int first_save_gpr_slot; 1084 int last_save_gpr_slot; 1085 1086 /* Location (FP register number) where GPRs (r0-r15) should 1087 be saved to. 1088 0 - does not need to be saved at all 1089 -1 - stack slot */ 1090 #define SAVE_SLOT_NONE 0 1091 #define SAVE_SLOT_STACK -1 1092 signed char gpr_save_slots[16]; 1093 1094 /* Number of first and last gpr to be saved, restored. */ 1095 int first_save_gpr; 1096 int first_restore_gpr; 1097 int last_save_gpr; 1098 int last_restore_gpr; 1099 1100 /* Bits standing for floating point registers. Set, if the 1101 respective register has to be saved. Starting with reg 16 (f0) 1102 at the rightmost bit. 1103 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1104 fpr 15 13 11 9 14 12 10 8 7 5 3 1 6 4 2 0 1105 reg 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 */ 1106 unsigned int fpr_bitmap; 1107 1108 /* Number of floating point registers f8-f15 which must be saved. */ 1109 int high_fprs; 1110 1111 /* Set if return address needs to be saved. 1112 This flag is set by s390_return_addr_rtx if it could not use 1113 the initial value of r14 and therefore depends on r14 saved 1114 to the stack. */ 1115 bool save_return_addr_p; 1116 1117 /* Size of stack frame. */ 1118 HOST_WIDE_INT frame_size; 1119 }; 1120 1121 1122 /* Define the structure for the machine field in struct function. */ 1123 1124 struct GTY(()) machine_function 1125 { 1126 struct s390_frame_layout frame_layout; 1127 1128 /* Literal pool base register. */ 1129 rtx base_reg; 1130 1131 bool has_landing_pad_p; 1132 1133 /* True if the current function may contain a tbegin clobbering 1134 FPRs. */ 1135 bool tbegin_p; 1136 1137 /* For -fsplit-stack support: A stack local which holds a pointer to 1138 the stack arguments for a function with a variable number of 1139 arguments. This is set at the start of the function and is used 1140 to initialize the overflow_arg_area field of the va_list 1141 structure. */ 1142 rtx split_stack_varargs_pointer; 1143 1144 enum indirect_branch indirect_branch_jump; 1145 enum indirect_branch indirect_branch_call; 1146 1147 enum indirect_branch function_return_mem; 1148 enum indirect_branch function_return_reg; 1149 }; 1150 #endif 1151 1152 #define TARGET_INDIRECT_BRANCH_NOBP_RET_OPTION \ 1153 (cfun->machine->function_return_reg != indirect_branch_keep \ 1154 || cfun->machine->function_return_mem != indirect_branch_keep) 1155 1156 #define TARGET_INDIRECT_BRANCH_NOBP_RET \ 1157 ((cfun->machine->function_return_reg != indirect_branch_keep \ 1158 && !s390_return_addr_from_memory ()) \ 1159 || (cfun->machine->function_return_mem != indirect_branch_keep \ 1160 && s390_return_addr_from_memory ())) 1161 1162 #define TARGET_INDIRECT_BRANCH_NOBP_JUMP \ 1163 (cfun->machine->indirect_branch_jump != indirect_branch_keep) 1164 1165 #define TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK \ 1166 (cfun->machine->indirect_branch_jump == indirect_branch_thunk \ 1167 || cfun->machine->indirect_branch_jump == indirect_branch_thunk_extern) 1168 1169 #define TARGET_INDIRECT_BRANCH_NOBP_JUMP_INLINE_THUNK \ 1170 (cfun->machine->indirect_branch_jump == indirect_branch_thunk_inline) 1171 1172 #define TARGET_INDIRECT_BRANCH_NOBP_CALL \ 1173 (cfun->machine->indirect_branch_call != indirect_branch_keep) 1174 1175 #ifndef TARGET_DEFAULT_INDIRECT_BRANCH_TABLE 1176 #define TARGET_DEFAULT_INDIRECT_BRANCH_TABLE 0 1177 #endif 1178 1179 #define TARGET_INDIRECT_BRANCH_THUNK_NAME_EXRL "__s390_indirect_jump_r%d" 1180 #define TARGET_INDIRECT_BRANCH_THUNK_NAME_EX "__s390_indirect_jump_r%duse_r%d" 1181 1182 #define TARGET_INDIRECT_BRANCH_TABLE s390_indirect_branch_table 1183 1184 1185 #endif /* S390_H */ 1186