1 /* Register renaming for the GNU compiler.
2 Copyright (C) 2000-2020 Free Software Foundation, Inc.
3
4 This file is part of GCC.
5
6 GCC is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
10
11 GCC is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
19
20 #include "config.h"
21 #include "system.h"
22 #include "coretypes.h"
23 #include "backend.h"
24 #include "target.h"
25 #include "rtl.h"
26 #include "df.h"
27 #include "memmodel.h"
28 #include "tm_p.h"
29 #include "insn-config.h"
30 #include "regs.h"
31 #include "emit-rtl.h"
32 #include "recog.h"
33 #include "addresses.h"
34 #include "cfganal.h"
35 #include "tree-pass.h"
36 #include "function-abi.h"
37 #include "regrename.h"
38
39 /* This file implements the RTL register renaming pass of the compiler. It is
40 a semi-local pass whose goal is to maximize the usage of the register file
41 of the processor by substituting registers for others in the solution given
42 by the register allocator. The algorithm is as follows:
43
44 1. Local def/use chains are built: within each basic block, chains are
45 opened and closed; if a chain isn't closed at the end of the block,
46 it is dropped. We pre-open chains if we have already examined a
47 predecessor block and found chains live at the end which match
48 live registers at the start of the new block.
49
50 2. We try to combine the local chains across basic block boundaries by
51 comparing chains that were open at the start or end of a block to
52 those in successor/predecessor blocks.
53
54 3. For each chain, the set of possible renaming registers is computed.
55 This takes into account the renaming of previously processed chains.
56 Optionally, a preferred class is computed for the renaming register.
57
58 4. The best renaming register is computed for the chain in the above set,
59 using a round-robin allocation. If a preferred class exists, then the
60 round-robin allocation is done within the class first, if possible.
61 The round-robin allocation of renaming registers itself is global.
62
63 5. If a renaming register has been found, it is substituted in the chain.
64
65 Targets can parameterize the pass by specifying a preferred class for the
66 renaming register for a given (super)class of registers to be renamed.
67
68 DEBUG_INSNs are treated specially, in particular registers occurring inside
69 them are treated as requiring ALL_REGS as a class. */
70
71 #if HOST_BITS_PER_WIDE_INT <= MAX_RECOG_OPERANDS
72 #error "Use a different bitmap implementation for untracked_operands."
73 #endif
74
75 enum scan_actions
76 {
77 terminate_write,
78 terminate_dead,
79 mark_all_read,
80 mark_read,
81 mark_write,
82 /* mark_access is for marking the destination regs in
83 REG_FRAME_RELATED_EXPR notes (as if they were read) so that the
84 note is updated properly. */
85 mark_access
86 };
87
88 static const char * const scan_actions_name[] =
89 {
90 "terminate_write",
91 "terminate_dead",
92 "mark_all_read",
93 "mark_read",
94 "mark_write",
95 "mark_access"
96 };
97
98 /* TICK and THIS_TICK are used to record the last time we saw each
99 register. */
100 static int tick[FIRST_PSEUDO_REGISTER];
101 static int this_tick = 0;
102
103 static struct obstack rename_obstack;
104
105 /* If nonnull, the code calling into the register renamer requested
106 information about insn operands, and we store it here. */
107 vec<insn_rr_info> insn_rr;
108
109 static void scan_rtx (rtx_insn *, rtx *, enum reg_class, enum scan_actions,
110 enum op_type);
111 static bool build_def_use (basic_block);
112
113 /* The id to be given to the next opened chain. */
114 static unsigned current_id;
115
116 /* A mapping of unique id numbers to chains. */
117 static vec<du_head_p> id_to_chain;
118
119 /* List of currently open chains. */
120 static class du_head *open_chains;
121
122 /* Bitmap of open chains. The bits set always match the list found in
123 open_chains. */
124 static bitmap_head open_chains_set;
125
126 /* Record the registers being tracked in open_chains. */
127 static HARD_REG_SET live_in_chains;
128
129 /* Record the registers that are live but not tracked. The intersection
130 between this and live_in_chains is empty. */
131 static HARD_REG_SET live_hard_regs;
132
133 /* Set while scanning RTL if INSN_RR is nonnull, i.e. if the current analysis
134 is for a caller that requires operand data. Used in
135 record_operand_use. */
136 static operand_rr_info *cur_operand;
137
138 /* Set while scanning RTL if a register dies. Used to tie chains. */
139 static class du_head *terminated_this_insn;
140
141 /* Return the chain corresponding to id number ID. Take into account that
142 chains may have been merged. */
143 du_head_p
regrename_chain_from_id(unsigned int id)144 regrename_chain_from_id (unsigned int id)
145 {
146 du_head_p first_chain = id_to_chain[id];
147 du_head_p chain = first_chain;
148 while (chain->id != id)
149 {
150 id = chain->id;
151 chain = id_to_chain[id];
152 }
153 first_chain->id = id;
154 return chain;
155 }
156
157 /* Dump all def/use chains, starting at id FROM. */
158
159 static void
dump_def_use_chain(int from)160 dump_def_use_chain (int from)
161 {
162 du_head_p head;
163 int i;
164 FOR_EACH_VEC_ELT_FROM (id_to_chain, i, head, from)
165 {
166 struct du_chain *this_du = head->first;
167
168 fprintf (dump_file, "Register %s (%d):",
169 reg_names[head->regno], head->nregs);
170 while (this_du)
171 {
172 fprintf (dump_file, " %d [%s]", INSN_UID (this_du->insn),
173 reg_class_names[this_du->cl]);
174 this_du = this_du->next_use;
175 }
176 fprintf (dump_file, "\n");
177 head = head->next_chain;
178 }
179 }
180
181 static void
free_chain_data(void)182 free_chain_data (void)
183 {
184 int i;
185 du_head_p ptr;
186 for (i = 0; id_to_chain.iterate (i, &ptr); i++)
187 bitmap_clear (&ptr->conflicts);
188
189 id_to_chain.release ();
190 }
191
192 /* Walk all chains starting with CHAINS and record that they conflict with
193 another chain whose id is ID. */
194
195 static void
mark_conflict(class du_head * chains,unsigned id)196 mark_conflict (class du_head *chains, unsigned id)
197 {
198 while (chains)
199 {
200 bitmap_set_bit (&chains->conflicts, id);
201 chains = chains->next_chain;
202 }
203 }
204
205 /* Examine cur_operand, and if it is nonnull, record information about the
206 use THIS_DU which is part of the chain HEAD. */
207
208 static void
record_operand_use(class du_head * head,struct du_chain * this_du)209 record_operand_use (class du_head *head, struct du_chain *this_du)
210 {
211 if (cur_operand == NULL || cur_operand->failed)
212 return;
213 if (head->cannot_rename)
214 {
215 cur_operand->failed = true;
216 return;
217 }
218 gcc_assert (cur_operand->n_chains < MAX_REGS_PER_ADDRESS);
219 cur_operand->heads[cur_operand->n_chains] = head;
220 cur_operand->chains[cur_operand->n_chains++] = this_du;
221 }
222
223 /* Create a new chain for THIS_NREGS registers starting at THIS_REGNO,
224 and record its occurrence in *LOC, which is being written to in INSN.
225 This access requires a register of class CL. */
226
227 static du_head_p
create_new_chain(unsigned this_regno,unsigned this_nregs,rtx * loc,rtx_insn * insn,enum reg_class cl)228 create_new_chain (unsigned this_regno, unsigned this_nregs, rtx *loc,
229 rtx_insn *insn, enum reg_class cl)
230 {
231 class du_head *head = XOBNEW (&rename_obstack, class du_head);
232 struct du_chain *this_du;
233 int nregs;
234
235 memset ((void *)head, 0, sizeof *head);
236 head->next_chain = open_chains;
237 head->regno = this_regno;
238 head->nregs = this_nregs;
239
240 id_to_chain.safe_push (head);
241 head->id = current_id++;
242
243 bitmap_initialize (&head->conflicts, &bitmap_default_obstack);
244 bitmap_copy (&head->conflicts, &open_chains_set);
245 mark_conflict (open_chains, head->id);
246
247 /* Since we're tracking this as a chain now, remove it from the
248 list of conflicting live hard registers and track it in
249 live_in_chains instead. */
250 nregs = head->nregs;
251 while (nregs-- > 0)
252 {
253 SET_HARD_REG_BIT (live_in_chains, head->regno + nregs);
254 CLEAR_HARD_REG_BIT (live_hard_regs, head->regno + nregs);
255 }
256
257 head->hard_conflicts = live_hard_regs;
258 bitmap_set_bit (&open_chains_set, head->id);
259
260 open_chains = head;
261
262 if (dump_file)
263 {
264 fprintf (dump_file, "Creating chain %s (%d)",
265 reg_names[head->regno], head->id);
266 if (insn != NULL_RTX)
267 fprintf (dump_file, " at insn %d", INSN_UID (insn));
268 fprintf (dump_file, "\n");
269 }
270
271 if (insn == NULL_RTX)
272 {
273 head->first = head->last = NULL;
274 return head;
275 }
276
277 this_du = XOBNEW (&rename_obstack, struct du_chain);
278 head->first = head->last = this_du;
279
280 this_du->next_use = 0;
281 this_du->loc = loc;
282 this_du->insn = insn;
283 this_du->cl = cl;
284 record_operand_use (head, this_du);
285 return head;
286 }
287
288 /* For a def-use chain HEAD, find which registers overlap its lifetime and
289 set the corresponding bits in *PSET. */
290
291 static void
merge_overlapping_regs(HARD_REG_SET * pset,class du_head * head)292 merge_overlapping_regs (HARD_REG_SET *pset, class du_head *head)
293 {
294 bitmap_iterator bi;
295 unsigned i;
296 *pset |= head->hard_conflicts;
297 EXECUTE_IF_SET_IN_BITMAP (&head->conflicts, 0, i, bi)
298 {
299 du_head_p other = regrename_chain_from_id (i);
300 unsigned j = other->nregs;
301 gcc_assert (other != head);
302 while (j-- > 0)
303 SET_HARD_REG_BIT (*pset, other->regno + j);
304 }
305 }
306
307 /* Return true if (reg:MODE REGNO) would be clobbered by a call covered
308 by THIS_HEAD. */
309
310 static bool
call_clobbered_in_chain_p(du_head * this_head,machine_mode mode,unsigned int regno)311 call_clobbered_in_chain_p (du_head *this_head, machine_mode mode,
312 unsigned int regno)
313 {
314 return call_clobbered_in_region_p (this_head->call_abis,
315 this_head->call_clobber_mask,
316 mode, regno);
317 }
318
319 /* Check if NEW_REG can be the candidate register to rename for
320 REG in THIS_HEAD chain. THIS_UNAVAILABLE is a set of unavailable hard
321 registers. */
322
323 static bool
check_new_reg_p(int reg ATTRIBUTE_UNUSED,int new_reg,class du_head * this_head,HARD_REG_SET this_unavailable)324 check_new_reg_p (int reg ATTRIBUTE_UNUSED, int new_reg,
325 class du_head *this_head, HARD_REG_SET this_unavailable)
326 {
327 machine_mode mode = GET_MODE (*this_head->first->loc);
328 int nregs = hard_regno_nregs (new_reg, mode);
329 int i;
330 struct du_chain *tmp;
331
332 for (i = nregs - 1; i >= 0; --i)
333 if (TEST_HARD_REG_BIT (this_unavailable, new_reg + i)
334 || fixed_regs[new_reg + i]
335 || global_regs[new_reg + i]
336 /* Can't use regs which aren't saved by the prologue. */
337 || (! df_regs_ever_live_p (new_reg + i)
338 && ! crtl->abi->clobbers_full_reg_p (new_reg + i))
339 #ifdef LEAF_REGISTERS
340 /* We can't use a non-leaf register if we're in a
341 leaf function. */
342 || (crtl->is_leaf
343 && !LEAF_REGISTERS[new_reg + i])
344 #endif
345 || ! HARD_REGNO_RENAME_OK (reg + i, new_reg + i))
346 return false;
347
348 /* See whether it accepts all modes that occur in
349 definition and uses. */
350 for (tmp = this_head->first; tmp; tmp = tmp->next_use)
351 {
352 /* Completely ignore DEBUG_INSNs, otherwise we can get
353 -fcompare-debug failures. */
354 if (DEBUG_INSN_P (tmp->insn))
355 continue;
356
357 if (!targetm.hard_regno_mode_ok (new_reg, GET_MODE (*tmp->loc))
358 || call_clobbered_in_chain_p (this_head, GET_MODE (*tmp->loc),
359 new_reg))
360 return false;
361 }
362
363 return true;
364 }
365
366 /* For the chain THIS_HEAD, compute and return the best register to
367 rename to. SUPER_CLASS is the superunion of register classes in
368 the chain. UNAVAILABLE is a set of registers that cannot be used.
369 OLD_REG is the register currently used for the chain. BEST_RENAME
370 controls whether the register chosen must be better than the
371 current one or just respect the given constraint. */
372
373 int
find_rename_reg(du_head_p this_head,enum reg_class super_class,HARD_REG_SET * unavailable,int old_reg,bool best_rename)374 find_rename_reg (du_head_p this_head, enum reg_class super_class,
375 HARD_REG_SET *unavailable, int old_reg, bool best_rename)
376 {
377 bool has_preferred_class;
378 enum reg_class preferred_class;
379 int pass;
380 int best_new_reg = old_reg;
381
382 /* Mark registers that overlap this chain's lifetime as unavailable. */
383 merge_overlapping_regs (unavailable, this_head);
384
385 /* Compute preferred rename class of super union of all the classes
386 in the chain. */
387 preferred_class
388 = (enum reg_class) targetm.preferred_rename_class (super_class);
389
390 /* Pick and check the register from the tied chain iff the tied chain
391 is not renamed. */
392 if (this_head->tied_chain && !this_head->tied_chain->renamed
393 && check_new_reg_p (old_reg, this_head->tied_chain->regno,
394 this_head, *unavailable))
395 return this_head->tied_chain->regno;
396
397 /* If PREFERRED_CLASS is not NO_REGS, we iterate in the first pass
398 over registers that belong to PREFERRED_CLASS and try to find the
399 best register within the class. If that failed, we iterate in
400 the second pass over registers that don't belong to the class.
401 If PREFERRED_CLASS is NO_REGS, we iterate over all registers in
402 ascending order without any preference. */
403 has_preferred_class = (preferred_class != NO_REGS);
404 for (pass = (has_preferred_class ? 0 : 1); pass < 2; pass++)
405 {
406 int new_reg;
407 for (new_reg = 0; new_reg < FIRST_PSEUDO_REGISTER; new_reg++)
408 {
409 if (has_preferred_class
410 && (pass == 0)
411 != TEST_HARD_REG_BIT (reg_class_contents[preferred_class],
412 new_reg))
413 continue;
414
415 if (!check_new_reg_p (old_reg, new_reg, this_head, *unavailable))
416 continue;
417
418 if (!best_rename)
419 return new_reg;
420
421 /* In the first pass, we force the renaming of registers that
422 don't belong to PREFERRED_CLASS to registers that do, even
423 though the latters were used not very long ago. */
424 if ((pass == 0
425 && !TEST_HARD_REG_BIT (reg_class_contents[preferred_class],
426 best_new_reg))
427 || tick[best_new_reg] > tick[new_reg])
428 best_new_reg = new_reg;
429 }
430 if (pass == 0 && best_new_reg != old_reg)
431 break;
432 }
433 return best_new_reg;
434 }
435
436 /* Iterate over elements in the chain HEAD in order to:
437 1. Count number of uses, storing it in *PN_USES.
438 2. Narrow the set of registers we can use for renaming, adding
439 unavailable registers to *PUNAVAILABLE, which must be
440 initialized by the caller.
441 3. Compute the superunion of register classes in this chain
442 and return it. */
443 reg_class
regrename_find_superclass(du_head_p head,int * pn_uses,HARD_REG_SET * punavailable)444 regrename_find_superclass (du_head_p head, int *pn_uses,
445 HARD_REG_SET *punavailable)
446 {
447 int n_uses = 0;
448 reg_class super_class = NO_REGS;
449 for (du_chain *tmp = head->first; tmp; tmp = tmp->next_use)
450 {
451 if (DEBUG_INSN_P (tmp->insn))
452 continue;
453 n_uses++;
454 *punavailable |= ~reg_class_contents[tmp->cl];
455 super_class
456 = reg_class_superunion[(int) super_class][(int) tmp->cl];
457 }
458 *pn_uses = n_uses;
459 return super_class;
460 }
461
462 /* Perform register renaming on the current function. */
463 static void
rename_chains(void)464 rename_chains (void)
465 {
466 HARD_REG_SET unavailable;
467 du_head_p this_head;
468 int i;
469
470 memset (tick, 0, sizeof tick);
471
472 CLEAR_HARD_REG_SET (unavailable);
473 /* Don't clobber traceback for noreturn functions. */
474 if (frame_pointer_needed)
475 {
476 add_to_hard_reg_set (&unavailable, Pmode, FRAME_POINTER_REGNUM);
477 if (!HARD_FRAME_POINTER_IS_FRAME_POINTER)
478 add_to_hard_reg_set (&unavailable, Pmode, HARD_FRAME_POINTER_REGNUM);
479 }
480
481 FOR_EACH_VEC_ELT (id_to_chain, i, this_head)
482 {
483 int best_new_reg;
484 int n_uses;
485 HARD_REG_SET this_unavailable;
486 int reg = this_head->regno;
487
488 if (this_head->cannot_rename)
489 continue;
490
491 if (fixed_regs[reg] || global_regs[reg]
492 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER && frame_pointer_needed
493 && reg == HARD_FRAME_POINTER_REGNUM)
494 || (HARD_FRAME_POINTER_IS_FRAME_POINTER && frame_pointer_needed
495 && reg == FRAME_POINTER_REGNUM))
496 continue;
497
498 this_unavailable = unavailable;
499
500 reg_class super_class = regrename_find_superclass (this_head, &n_uses,
501 &this_unavailable);
502 if (n_uses < 2)
503 continue;
504
505 best_new_reg = find_rename_reg (this_head, super_class,
506 &this_unavailable, reg, true);
507
508 if (dump_file)
509 {
510 fprintf (dump_file, "Register %s in insn %d",
511 reg_names[reg], INSN_UID (this_head->first->insn));
512 if (this_head->call_abis)
513 fprintf (dump_file, " crosses a call");
514 }
515
516 if (best_new_reg == reg)
517 {
518 tick[reg] = ++this_tick;
519 if (dump_file)
520 fprintf (dump_file, "; no available better choice\n");
521 continue;
522 }
523
524 if (regrename_do_replace (this_head, best_new_reg))
525 {
526 if (dump_file)
527 fprintf (dump_file, ", renamed as %s\n", reg_names[best_new_reg]);
528 tick[best_new_reg] = ++this_tick;
529 df_set_regs_ever_live (best_new_reg, true);
530 }
531 else
532 {
533 if (dump_file)
534 fprintf (dump_file, ", renaming as %s failed\n",
535 reg_names[best_new_reg]);
536 tick[reg] = ++this_tick;
537 }
538 }
539 }
540
541 /* A structure to record information for each hard register at the start of
542 a basic block. */
543 struct incoming_reg_info {
544 /* Holds the number of registers used in the chain that gave us information
545 about this register. Zero means no information known yet, while a
546 negative value is used for something that is part of, but not the first
547 register in a multi-register value. */
548 int nregs;
549 /* Set to true if we have accesses that conflict in the number of registers
550 used. */
551 bool unusable;
552 };
553
554 /* A structure recording information about each basic block. It is saved
555 and restored around basic block boundaries.
556 A pointer to such a structure is stored in each basic block's aux field
557 during regrename_analyze, except for blocks we know can't be optimized
558 (such as entry and exit blocks). */
559 class bb_rename_info
560 {
561 public:
562 /* The basic block corresponding to this structure. */
563 basic_block bb;
564 /* Copies of the global information. */
565 bitmap_head open_chains_set;
566 bitmap_head incoming_open_chains_set;
567 struct incoming_reg_info incoming[FIRST_PSEUDO_REGISTER];
568 };
569
570 /* Initialize a rename_info structure P for basic block BB, which starts a new
571 scan. */
572 static void
init_rename_info(class bb_rename_info * p,basic_block bb)573 init_rename_info (class bb_rename_info *p, basic_block bb)
574 {
575 int i;
576 df_ref def;
577 HARD_REG_SET start_chains_set;
578
579 p->bb = bb;
580 bitmap_initialize (&p->open_chains_set, &bitmap_default_obstack);
581 bitmap_initialize (&p->incoming_open_chains_set, &bitmap_default_obstack);
582
583 open_chains = NULL;
584 bitmap_clear (&open_chains_set);
585
586 CLEAR_HARD_REG_SET (live_in_chains);
587 REG_SET_TO_HARD_REG_SET (live_hard_regs, df_get_live_in (bb));
588 FOR_EACH_ARTIFICIAL_DEF (def, bb->index)
589 if (DF_REF_FLAGS (def) & DF_REF_AT_TOP)
590 SET_HARD_REG_BIT (live_hard_regs, DF_REF_REGNO (def));
591
592 /* Open chains based on information from (at least one) predecessor
593 block. This gives us a chance later on to combine chains across
594 basic block boundaries. Inconsistencies (in access sizes) will
595 be caught normally and dealt with conservatively by disabling the
596 chain for renaming, and there is no risk of losing optimization
597 opportunities by opening chains either: if we did not open the
598 chains, we'd have to track the live register as a hard reg, and
599 we'd be unable to rename it in any case. */
600 CLEAR_HARD_REG_SET (start_chains_set);
601 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
602 {
603 struct incoming_reg_info *iri = p->incoming + i;
604 if (iri->nregs > 0 && !iri->unusable
605 && range_in_hard_reg_set_p (live_hard_regs, i, iri->nregs))
606 {
607 SET_HARD_REG_BIT (start_chains_set, i);
608 remove_range_from_hard_reg_set (&live_hard_regs, i, iri->nregs);
609 }
610 }
611 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
612 {
613 struct incoming_reg_info *iri = p->incoming + i;
614 if (TEST_HARD_REG_BIT (start_chains_set, i))
615 {
616 du_head_p chain;
617 if (dump_file)
618 fprintf (dump_file, "opening incoming chain\n");
619 chain = create_new_chain (i, iri->nregs, NULL, NULL, NO_REGS);
620 bitmap_set_bit (&p->incoming_open_chains_set, chain->id);
621 }
622 }
623 }
624
625 /* Record in RI that the block corresponding to it has an incoming
626 live value, described by CHAIN. */
627 static void
set_incoming_from_chain(class bb_rename_info * ri,du_head_p chain)628 set_incoming_from_chain (class bb_rename_info *ri, du_head_p chain)
629 {
630 int i;
631 int incoming_nregs = ri->incoming[chain->regno].nregs;
632 int nregs;
633
634 /* If we've recorded the same information before, everything is fine. */
635 if (incoming_nregs == chain->nregs)
636 {
637 if (dump_file)
638 fprintf (dump_file, "reg %d/%d already recorded\n",
639 chain->regno, chain->nregs);
640 return;
641 }
642
643 /* If we have no information for any of the involved registers, update
644 the incoming array. */
645 nregs = chain->nregs;
646 while (nregs-- > 0)
647 if (ri->incoming[chain->regno + nregs].nregs != 0
648 || ri->incoming[chain->regno + nregs].unusable)
649 break;
650 if (nregs < 0)
651 {
652 nregs = chain->nregs;
653 ri->incoming[chain->regno].nregs = nregs;
654 while (nregs-- > 1)
655 ri->incoming[chain->regno + nregs].nregs = -nregs;
656 if (dump_file)
657 fprintf (dump_file, "recorded reg %d/%d\n",
658 chain->regno, chain->nregs);
659 return;
660 }
661
662 /* There must be some kind of conflict. Prevent both the old and
663 new ranges from being used. */
664 if (incoming_nregs < 0)
665 ri->incoming[chain->regno + incoming_nregs].unusable = true;
666 for (i = 0; i < chain->nregs; i++)
667 ri->incoming[chain->regno + i].unusable = true;
668 }
669
670 /* Merge the two chains C1 and C2 so that all conflict information is
671 recorded and C1, and the id of C2 is changed to that of C1. */
672 static void
merge_chains(du_head_p c1,du_head_p c2)673 merge_chains (du_head_p c1, du_head_p c2)
674 {
675 if (c1 == c2)
676 return;
677
678 if (c2->first != NULL)
679 {
680 if (c1->first == NULL)
681 c1->first = c2->first;
682 else
683 c1->last->next_use = c2->first;
684 c1->last = c2->last;
685 }
686
687 c2->first = c2->last = NULL;
688 c2->id = c1->id;
689
690 c1->hard_conflicts |= c2->hard_conflicts;
691 bitmap_ior_into (&c1->conflicts, &c2->conflicts);
692
693 c1->call_clobber_mask |= c2->call_clobber_mask;
694 c1->call_abis |= c2->call_abis;
695 c1->cannot_rename |= c2->cannot_rename;
696 }
697
698 /* Analyze the current function and build chains for renaming. */
699
700 void
regrename_analyze(bitmap bb_mask)701 regrename_analyze (bitmap bb_mask)
702 {
703 class bb_rename_info *rename_info;
704 int i;
705 basic_block bb;
706 int n_bbs;
707 int *inverse_postorder;
708
709 inverse_postorder = XNEWVEC (int, last_basic_block_for_fn (cfun));
710 n_bbs = pre_and_rev_post_order_compute (NULL, inverse_postorder, false);
711
712 /* Gather some information about the blocks in this function. */
713 rename_info = XCNEWVEC (class bb_rename_info, n_basic_blocks_for_fn (cfun));
714 i = 0;
715 FOR_EACH_BB_FN (bb, cfun)
716 {
717 class bb_rename_info *ri = rename_info + i;
718 ri->bb = bb;
719 if (bb_mask != NULL && !bitmap_bit_p (bb_mask, bb->index))
720 bb->aux = NULL;
721 else
722 bb->aux = ri;
723 i++;
724 }
725
726 current_id = 0;
727 id_to_chain.create (0);
728 bitmap_initialize (&open_chains_set, &bitmap_default_obstack);
729
730 /* The order in which we visit blocks ensures that whenever
731 possible, we only process a block after at least one of its
732 predecessors, which provides a "seeding" effect to make the logic
733 in set_incoming_from_chain and init_rename_info useful. */
734
735 for (i = 0; i < n_bbs; i++)
736 {
737 basic_block bb1 = BASIC_BLOCK_FOR_FN (cfun, inverse_postorder[i]);
738 class bb_rename_info *this_info;
739 bool success;
740 edge e;
741 edge_iterator ei;
742 int old_length = id_to_chain.length ();
743
744 this_info = (class bb_rename_info *) bb1->aux;
745 if (this_info == NULL)
746 continue;
747
748 if (dump_file)
749 fprintf (dump_file, "\nprocessing block %d:\n", bb1->index);
750
751 init_rename_info (this_info, bb1);
752
753 success = build_def_use (bb1);
754 if (!success)
755 {
756 if (dump_file)
757 fprintf (dump_file, "failed\n");
758 bb1->aux = NULL;
759 id_to_chain.truncate (old_length);
760 current_id = old_length;
761 bitmap_clear (&this_info->incoming_open_chains_set);
762 open_chains = NULL;
763 if (insn_rr.exists ())
764 {
765 rtx_insn *insn;
766 FOR_BB_INSNS (bb1, insn)
767 {
768 insn_rr_info *p = &insn_rr[INSN_UID (insn)];
769 p->op_info = NULL;
770 }
771 }
772 continue;
773 }
774
775 if (dump_file)
776 dump_def_use_chain (old_length);
777 bitmap_copy (&this_info->open_chains_set, &open_chains_set);
778
779 /* Add successor blocks to the worklist if necessary, and record
780 data about our own open chains at the end of this block, which
781 will be used to pre-open chains when processing the successors. */
782 FOR_EACH_EDGE (e, ei, bb1->succs)
783 {
784 class bb_rename_info *dest_ri;
785 class du_head *chain;
786
787 if (dump_file)
788 fprintf (dump_file, "successor block %d\n", e->dest->index);
789
790 if (e->flags & (EDGE_EH | EDGE_ABNORMAL))
791 continue;
792 dest_ri = (class bb_rename_info *)e->dest->aux;
793 if (dest_ri == NULL)
794 continue;
795 for (chain = open_chains; chain; chain = chain->next_chain)
796 set_incoming_from_chain (dest_ri, chain);
797 }
798 }
799
800 free (inverse_postorder);
801
802 /* Now, combine the chains data we have gathered across basic block
803 boundaries.
804
805 For every basic block, there may be chains open at the start, or at the
806 end. Rather than exclude them from renaming, we look for open chains
807 with matching registers at the other side of the CFG edge.
808
809 For a given chain using register R, open at the start of block B, we
810 must find an open chain using R on the other side of every edge leading
811 to B, if the register is live across this edge. In the code below,
812 N_PREDS_USED counts the number of edges where the register is live, and
813 N_PREDS_JOINED counts those where we found an appropriate chain for
814 joining.
815
816 We perform the analysis for both incoming and outgoing edges, but we
817 only need to merge once (in the second part, after verifying outgoing
818 edges). */
819 FOR_EACH_BB_FN (bb, cfun)
820 {
821 class bb_rename_info *bb_ri = (class bb_rename_info *) bb->aux;
822 unsigned j;
823 bitmap_iterator bi;
824
825 if (bb_ri == NULL)
826 continue;
827
828 if (dump_file)
829 fprintf (dump_file, "processing bb %d in edges\n", bb->index);
830
831 EXECUTE_IF_SET_IN_BITMAP (&bb_ri->incoming_open_chains_set, 0, j, bi)
832 {
833 edge e;
834 edge_iterator ei;
835 class du_head *chain = regrename_chain_from_id (j);
836 int n_preds_used = 0, n_preds_joined = 0;
837
838 FOR_EACH_EDGE (e, ei, bb->preds)
839 {
840 class bb_rename_info *src_ri;
841 unsigned k;
842 bitmap_iterator bi2;
843 HARD_REG_SET live;
844 bool success = false;
845
846 REG_SET_TO_HARD_REG_SET (live, df_get_live_out (e->src));
847 if (!range_overlaps_hard_reg_set_p (live, chain->regno,
848 chain->nregs))
849 continue;
850 n_preds_used++;
851
852 if (e->flags & (EDGE_EH | EDGE_ABNORMAL))
853 continue;
854
855 src_ri = (class bb_rename_info *)e->src->aux;
856 if (src_ri == NULL)
857 continue;
858
859 EXECUTE_IF_SET_IN_BITMAP (&src_ri->open_chains_set,
860 0, k, bi2)
861 {
862 class du_head *outgoing_chain = regrename_chain_from_id (k);
863
864 if (outgoing_chain->regno == chain->regno
865 && outgoing_chain->nregs == chain->nregs)
866 {
867 n_preds_joined++;
868 success = true;
869 break;
870 }
871 }
872 if (!success && dump_file)
873 fprintf (dump_file, "failure to match with pred block %d\n",
874 e->src->index);
875 }
876 if (n_preds_joined < n_preds_used)
877 {
878 if (dump_file)
879 fprintf (dump_file, "cannot rename chain %d\n", j);
880 chain->cannot_rename = 1;
881 }
882 }
883 }
884 FOR_EACH_BB_FN (bb, cfun)
885 {
886 class bb_rename_info *bb_ri = (class bb_rename_info *) bb->aux;
887 unsigned j;
888 bitmap_iterator bi;
889
890 if (bb_ri == NULL)
891 continue;
892
893 if (dump_file)
894 fprintf (dump_file, "processing bb %d out edges\n", bb->index);
895
896 EXECUTE_IF_SET_IN_BITMAP (&bb_ri->open_chains_set, 0, j, bi)
897 {
898 edge e;
899 edge_iterator ei;
900 class du_head *chain = regrename_chain_from_id (j);
901 int n_succs_used = 0, n_succs_joined = 0;
902
903 FOR_EACH_EDGE (e, ei, bb->succs)
904 {
905 bool printed = false;
906 class bb_rename_info *dest_ri;
907 unsigned k;
908 bitmap_iterator bi2;
909 HARD_REG_SET live;
910
911 REG_SET_TO_HARD_REG_SET (live, df_get_live_in (e->dest));
912 if (!range_overlaps_hard_reg_set_p (live, chain->regno,
913 chain->nregs))
914 continue;
915
916 n_succs_used++;
917
918 dest_ri = (class bb_rename_info *)e->dest->aux;
919 if (dest_ri == NULL)
920 continue;
921
922 EXECUTE_IF_SET_IN_BITMAP (&dest_ri->incoming_open_chains_set,
923 0, k, bi2)
924 {
925 class du_head *incoming_chain = regrename_chain_from_id (k);
926
927 if (incoming_chain->regno == chain->regno
928 && incoming_chain->nregs == chain->nregs)
929 {
930 if (dump_file)
931 {
932 if (!printed)
933 fprintf (dump_file,
934 "merging blocks for edge %d -> %d\n",
935 e->src->index, e->dest->index);
936 printed = true;
937 fprintf (dump_file,
938 " merging chains %d (->%d) and %d (->%d) [%s]\n",
939 k, incoming_chain->id, j, chain->id,
940 reg_names[incoming_chain->regno]);
941 }
942
943 merge_chains (chain, incoming_chain);
944 n_succs_joined++;
945 break;
946 }
947 }
948 }
949 if (n_succs_joined < n_succs_used)
950 {
951 if (dump_file)
952 fprintf (dump_file, "cannot rename chain %d\n",
953 j);
954 chain->cannot_rename = 1;
955 }
956 }
957 }
958
959 free (rename_info);
960
961 FOR_EACH_BB_FN (bb, cfun)
962 bb->aux = NULL;
963 }
964
965 /* Attempt to replace all uses of the register in the chain beginning with
966 HEAD with REG. Returns true on success and false if the replacement is
967 rejected because the insns would not validate. The latter can happen
968 e.g. if a match_parallel predicate enforces restrictions on register
969 numbering in its subpatterns. */
970
971 bool
regrename_do_replace(class du_head * head,int reg)972 regrename_do_replace (class du_head *head, int reg)
973 {
974 struct du_chain *chain;
975 unsigned int base_regno = head->regno;
976 machine_mode mode;
977 rtx last_reg = NULL_RTX, last_repl = NULL_RTX;
978
979 for (chain = head->first; chain; chain = chain->next_use)
980 {
981 unsigned int regno = ORIGINAL_REGNO (*chain->loc);
982 class reg_attrs *attr = REG_ATTRS (*chain->loc);
983 int reg_ptr = REG_POINTER (*chain->loc);
984
985 if (DEBUG_INSN_P (chain->insn) && REGNO (*chain->loc) != base_regno)
986 validate_change (chain->insn, &(INSN_VAR_LOCATION_LOC (chain->insn)),
987 gen_rtx_UNKNOWN_VAR_LOC (), true);
988 else
989 {
990 if (*chain->loc != last_reg)
991 {
992 last_repl = gen_raw_REG (GET_MODE (*chain->loc), reg);
993 if (regno >= FIRST_PSEUDO_REGISTER)
994 ORIGINAL_REGNO (last_repl) = regno;
995 REG_ATTRS (last_repl) = attr;
996 REG_POINTER (last_repl) = reg_ptr;
997 last_reg = *chain->loc;
998 }
999 validate_change (chain->insn, chain->loc, last_repl, true);
1000 }
1001 }
1002
1003 if (!apply_change_group ())
1004 return false;
1005
1006 mode = GET_MODE (*head->first->loc);
1007 head->renamed = 1;
1008 head->regno = reg;
1009 head->nregs = hard_regno_nregs (reg, mode);
1010 return true;
1011 }
1012
1013
1014 /* True if we found a register with a size mismatch, which means that we
1015 can't track its lifetime accurately. If so, we abort the current block
1016 without renaming. */
1017 static bool fail_current_block;
1018
1019 /* Return true if OP is a reg for which all bits are set in PSET, false
1020 if all bits are clear.
1021 In other cases, set fail_current_block and return false. */
1022
1023 static bool
verify_reg_in_set(rtx op,HARD_REG_SET * pset)1024 verify_reg_in_set (rtx op, HARD_REG_SET *pset)
1025 {
1026 unsigned regno, nregs;
1027 bool all_live, all_dead;
1028 if (!REG_P (op))
1029 return false;
1030
1031 regno = REGNO (op);
1032 nregs = REG_NREGS (op);
1033 all_live = all_dead = true;
1034 while (nregs-- > 0)
1035 if (TEST_HARD_REG_BIT (*pset, regno + nregs))
1036 all_dead = false;
1037 else
1038 all_live = false;
1039 if (!all_dead && !all_live)
1040 {
1041 fail_current_block = true;
1042 return false;
1043 }
1044 return all_live;
1045 }
1046
1047 /* Return true if OP is a reg that is being tracked already in some form.
1048 May set fail_current_block if it sees an unhandled case of overlap. */
1049
1050 static bool
verify_reg_tracked(rtx op)1051 verify_reg_tracked (rtx op)
1052 {
1053 return (verify_reg_in_set (op, &live_hard_regs)
1054 || verify_reg_in_set (op, &live_in_chains));
1055 }
1056
1057 /* Called through note_stores. DATA points to a rtx_code, either SET or
1058 CLOBBER, which tells us which kind of rtx to look at. If we have a
1059 match, record the set register in live_hard_regs and in the hard_conflicts
1060 bitmap of open chains. */
1061
1062 static void
note_sets_clobbers(rtx x,const_rtx set,void * data)1063 note_sets_clobbers (rtx x, const_rtx set, void *data)
1064 {
1065 enum rtx_code code = *(enum rtx_code *)data;
1066 class du_head *chain;
1067
1068 if (GET_CODE (x) == SUBREG)
1069 x = SUBREG_REG (x);
1070 if (!REG_P (x) || GET_CODE (set) != code)
1071 return;
1072 /* There must not be pseudos at this point. */
1073 gcc_assert (HARD_REGISTER_P (x));
1074 add_to_hard_reg_set (&live_hard_regs, GET_MODE (x), REGNO (x));
1075 for (chain = open_chains; chain; chain = chain->next_chain)
1076 add_to_hard_reg_set (&chain->hard_conflicts, GET_MODE (x), REGNO (x));
1077 }
1078
1079 static void
scan_rtx_reg(rtx_insn * insn,rtx * loc,enum reg_class cl,enum scan_actions action,enum op_type type)1080 scan_rtx_reg (rtx_insn *insn, rtx *loc, enum reg_class cl, enum scan_actions action,
1081 enum op_type type)
1082 {
1083 class du_head **p;
1084 rtx x = *loc;
1085 unsigned this_regno = REGNO (x);
1086 int this_nregs = REG_NREGS (x);
1087
1088 if (action == mark_write)
1089 {
1090 if (type == OP_OUT)
1091 {
1092 du_head_p c;
1093 rtx pat = PATTERN (insn);
1094
1095 c = create_new_chain (this_regno, this_nregs, loc, insn, cl);
1096
1097 /* We try to tie chains in a move instruction for
1098 a single output. */
1099 if (recog_data.n_operands == 2
1100 && GET_CODE (pat) == SET
1101 && GET_CODE (SET_DEST (pat)) == REG
1102 && GET_CODE (SET_SRC (pat)) == REG
1103 && terminated_this_insn
1104 && terminated_this_insn->nregs
1105 == REG_NREGS (recog_data.operand[1]))
1106 {
1107 gcc_assert (terminated_this_insn->regno
1108 == REGNO (recog_data.operand[1]));
1109
1110 c->tied_chain = terminated_this_insn;
1111 terminated_this_insn->tied_chain = c;
1112
1113 if (dump_file)
1114 fprintf (dump_file, "Tying chain %s (%d) with %s (%d)\n",
1115 reg_names[c->regno], c->id,
1116 reg_names[terminated_this_insn->regno],
1117 terminated_this_insn->id);
1118 }
1119 }
1120
1121 return;
1122 }
1123
1124 if ((type == OP_OUT) != (action == terminate_write || action == mark_access))
1125 return;
1126
1127 for (p = &open_chains; *p;)
1128 {
1129 class du_head *head = *p;
1130 class du_head *next = head->next_chain;
1131 int exact_match = (head->regno == this_regno
1132 && head->nregs == this_nregs);
1133 int superset = (this_regno <= head->regno
1134 && this_regno + this_nregs >= head->regno + head->nregs);
1135 int subset = (this_regno >= head->regno
1136 && this_regno + this_nregs <= head->regno + head->nregs);
1137
1138 if (!bitmap_bit_p (&open_chains_set, head->id)
1139 || head->regno + head->nregs <= this_regno
1140 || this_regno + this_nregs <= head->regno)
1141 {
1142 p = &head->next_chain;
1143 continue;
1144 }
1145
1146 if (action == mark_read || action == mark_access)
1147 {
1148 /* ??? Class NO_REGS can happen if the md file makes use of
1149 EXTRA_CONSTRAINTS to match registers. Which is arguably
1150 wrong, but there we are. */
1151
1152 if (cl == NO_REGS || (!exact_match && !DEBUG_INSN_P (insn)))
1153 {
1154 if (dump_file)
1155 fprintf (dump_file,
1156 "Cannot rename chain %s (%d) at insn %d (%s)\n",
1157 reg_names[head->regno], head->id, INSN_UID (insn),
1158 scan_actions_name[(int) action]);
1159 head->cannot_rename = 1;
1160 if (superset)
1161 {
1162 unsigned nregs = this_nregs;
1163 head->regno = this_regno;
1164 head->nregs = this_nregs;
1165 while (nregs-- > 0)
1166 SET_HARD_REG_BIT (live_in_chains, head->regno + nregs);
1167 if (dump_file)
1168 fprintf (dump_file,
1169 "Widening register in chain %s (%d) at insn %d\n",
1170 reg_names[head->regno], head->id, INSN_UID (insn));
1171 }
1172 else if (!subset)
1173 {
1174 fail_current_block = true;
1175 if (dump_file)
1176 fprintf (dump_file,
1177 "Failing basic block due to unhandled overlap\n");
1178 }
1179 }
1180 else
1181 {
1182 struct du_chain *this_du;
1183 this_du = XOBNEW (&rename_obstack, struct du_chain);
1184 this_du->next_use = 0;
1185 this_du->loc = loc;
1186 this_du->insn = insn;
1187 this_du->cl = cl;
1188 if (head->first == NULL)
1189 head->first = this_du;
1190 else
1191 head->last->next_use = this_du;
1192 record_operand_use (head, this_du);
1193 head->last = this_du;
1194 }
1195 /* Avoid adding the same location in a DEBUG_INSN multiple times,
1196 which could happen with non-exact overlap. */
1197 if (DEBUG_INSN_P (insn))
1198 return;
1199 /* Otherwise, find any other chains that do not match exactly;
1200 ensure they all get marked unrenamable. */
1201 p = &head->next_chain;
1202 continue;
1203 }
1204
1205 /* Whether the terminated chain can be used for renaming
1206 depends on the action and this being an exact match.
1207 In either case, we remove this element from open_chains. */
1208
1209 if ((action == terminate_dead || action == terminate_write)
1210 && (superset || subset))
1211 {
1212 unsigned nregs;
1213
1214 if (subset && !superset)
1215 head->cannot_rename = 1;
1216 bitmap_clear_bit (&open_chains_set, head->id);
1217
1218 nregs = head->nregs;
1219 while (nregs-- > 0)
1220 {
1221 CLEAR_HARD_REG_BIT (live_in_chains, head->regno + nregs);
1222 if (subset && !superset
1223 && (head->regno + nregs < this_regno
1224 || head->regno + nregs >= this_regno + this_nregs))
1225 SET_HARD_REG_BIT (live_hard_regs, head->regno + nregs);
1226 }
1227
1228 if (action == terminate_dead)
1229 terminated_this_insn = *p;
1230 *p = next;
1231 if (dump_file)
1232 fprintf (dump_file,
1233 "Closing chain %s (%d) at insn %d (%s%s)\n",
1234 reg_names[head->regno], head->id, INSN_UID (insn),
1235 scan_actions_name[(int) action],
1236 superset ? ", superset" : subset ? ", subset" : "");
1237 }
1238 else if (action == terminate_dead || action == terminate_write)
1239 {
1240 /* In this case, tracking liveness gets too hard. Fail the
1241 entire basic block. */
1242 if (dump_file)
1243 fprintf (dump_file,
1244 "Failing basic block due to unhandled overlap\n");
1245 fail_current_block = true;
1246 return;
1247 }
1248 else
1249 {
1250 head->cannot_rename = 1;
1251 if (dump_file)
1252 fprintf (dump_file,
1253 "Cannot rename chain %s (%d) at insn %d (%s)\n",
1254 reg_names[head->regno], head->id, INSN_UID (insn),
1255 scan_actions_name[(int) action]);
1256 p = &head->next_chain;
1257 }
1258 }
1259 }
1260
1261 /* A wrapper around base_reg_class which returns ALL_REGS if INSN is a
1262 DEBUG_INSN. The arguments MODE, AS, CODE and INDEX_CODE are as for
1263 base_reg_class. */
1264
1265 static reg_class
base_reg_class_for_rename(rtx_insn * insn,machine_mode mode,addr_space_t as,rtx_code code,rtx_code index_code)1266 base_reg_class_for_rename (rtx_insn *insn, machine_mode mode, addr_space_t as,
1267 rtx_code code, rtx_code index_code)
1268 {
1269 if (DEBUG_INSN_P (insn))
1270 return ALL_REGS;
1271 return base_reg_class (mode, as, code, index_code);
1272 }
1273
1274 /* Adapted from find_reloads_address_1. CL is INDEX_REG_CLASS or
1275 BASE_REG_CLASS depending on how the register is being considered. */
1276
1277 static void
scan_rtx_address(rtx_insn * insn,rtx * loc,enum reg_class cl,enum scan_actions action,machine_mode mode,addr_space_t as)1278 scan_rtx_address (rtx_insn *insn, rtx *loc, enum reg_class cl,
1279 enum scan_actions action, machine_mode mode,
1280 addr_space_t as)
1281 {
1282 rtx x = *loc;
1283 RTX_CODE code = GET_CODE (x);
1284 const char *fmt;
1285 int i, j;
1286
1287 if (action == mark_write || action == mark_access)
1288 return;
1289
1290 switch (code)
1291 {
1292 case PLUS:
1293 {
1294 rtx orig_op0 = XEXP (x, 0);
1295 rtx orig_op1 = XEXP (x, 1);
1296 RTX_CODE code0 = GET_CODE (orig_op0);
1297 RTX_CODE code1 = GET_CODE (orig_op1);
1298 rtx op0 = orig_op0;
1299 rtx op1 = orig_op1;
1300 rtx *locI = NULL;
1301 rtx *locB = NULL;
1302 enum rtx_code index_code = SCRATCH;
1303
1304 if (GET_CODE (op0) == SUBREG)
1305 {
1306 op0 = SUBREG_REG (op0);
1307 code0 = GET_CODE (op0);
1308 }
1309
1310 if (GET_CODE (op1) == SUBREG)
1311 {
1312 op1 = SUBREG_REG (op1);
1313 code1 = GET_CODE (op1);
1314 }
1315
1316 if (code0 == MULT || code0 == SIGN_EXTEND || code0 == TRUNCATE
1317 || code0 == ZERO_EXTEND || code1 == MEM)
1318 {
1319 locI = &XEXP (x, 0);
1320 locB = &XEXP (x, 1);
1321 index_code = GET_CODE (*locI);
1322 }
1323 else if (code1 == MULT || code1 == SIGN_EXTEND || code1 == TRUNCATE
1324 || code1 == ZERO_EXTEND || code0 == MEM)
1325 {
1326 locI = &XEXP (x, 1);
1327 locB = &XEXP (x, 0);
1328 index_code = GET_CODE (*locI);
1329 }
1330 else if (code0 == CONST_INT || code0 == CONST
1331 || code0 == SYMBOL_REF || code0 == LABEL_REF)
1332 {
1333 locB = &XEXP (x, 1);
1334 index_code = GET_CODE (XEXP (x, 0));
1335 }
1336 else if (code1 == CONST_INT || code1 == CONST
1337 || code1 == SYMBOL_REF || code1 == LABEL_REF)
1338 {
1339 locB = &XEXP (x, 0);
1340 index_code = GET_CODE (XEXP (x, 1));
1341 }
1342 else if (code0 == REG && code1 == REG)
1343 {
1344 int index_op;
1345 unsigned regno0 = REGNO (op0), regno1 = REGNO (op1);
1346
1347 if (REGNO_OK_FOR_INDEX_P (regno1)
1348 && regno_ok_for_base_p (regno0, mode, as, PLUS, REG))
1349 index_op = 1;
1350 else if (REGNO_OK_FOR_INDEX_P (regno0)
1351 && regno_ok_for_base_p (regno1, mode, as, PLUS, REG))
1352 index_op = 0;
1353 else if (regno_ok_for_base_p (regno0, mode, as, PLUS, REG)
1354 || REGNO_OK_FOR_INDEX_P (regno1))
1355 index_op = 1;
1356 else if (regno_ok_for_base_p (regno1, mode, as, PLUS, REG))
1357 index_op = 0;
1358 else
1359 index_op = 1;
1360
1361 locI = &XEXP (x, index_op);
1362 locB = &XEXP (x, !index_op);
1363 index_code = GET_CODE (*locI);
1364 }
1365 else if (code0 == REG)
1366 {
1367 locI = &XEXP (x, 0);
1368 locB = &XEXP (x, 1);
1369 index_code = GET_CODE (*locI);
1370 }
1371 else if (code1 == REG)
1372 {
1373 locI = &XEXP (x, 1);
1374 locB = &XEXP (x, 0);
1375 index_code = GET_CODE (*locI);
1376 }
1377
1378 if (locI)
1379 {
1380 reg_class iclass = DEBUG_INSN_P (insn) ? ALL_REGS : INDEX_REG_CLASS;
1381 scan_rtx_address (insn, locI, iclass, action, mode, as);
1382 }
1383 if (locB)
1384 {
1385 reg_class bclass = base_reg_class_for_rename (insn, mode, as, PLUS,
1386 index_code);
1387 scan_rtx_address (insn, locB, bclass, action, mode, as);
1388 }
1389 return;
1390 }
1391
1392 case POST_INC:
1393 case POST_DEC:
1394 case POST_MODIFY:
1395 case PRE_INC:
1396 case PRE_DEC:
1397 case PRE_MODIFY:
1398 /* If the target doesn't claim to handle autoinc, this must be
1399 something special, like a stack push. Kill this chain. */
1400 if (!AUTO_INC_DEC)
1401 action = mark_all_read;
1402
1403 break;
1404
1405 case MEM:
1406 {
1407 reg_class bclass = base_reg_class_for_rename (insn, GET_MODE (x),
1408 MEM_ADDR_SPACE (x),
1409 MEM, SCRATCH);
1410 scan_rtx_address (insn, &XEXP (x, 0), bclass, action, GET_MODE (x),
1411 MEM_ADDR_SPACE (x));
1412 }
1413 return;
1414
1415 case REG:
1416 scan_rtx_reg (insn, loc, cl, action, OP_IN);
1417 return;
1418
1419 default:
1420 break;
1421 }
1422
1423 fmt = GET_RTX_FORMAT (code);
1424 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1425 {
1426 if (fmt[i] == 'e')
1427 scan_rtx_address (insn, &XEXP (x, i), cl, action, mode, as);
1428 else if (fmt[i] == 'E')
1429 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
1430 scan_rtx_address (insn, &XVECEXP (x, i, j), cl, action, mode, as);
1431 }
1432 }
1433
1434 static void
scan_rtx(rtx_insn * insn,rtx * loc,enum reg_class cl,enum scan_actions action,enum op_type type)1435 scan_rtx (rtx_insn *insn, rtx *loc, enum reg_class cl, enum scan_actions action,
1436 enum op_type type)
1437 {
1438 const char *fmt;
1439 rtx x = *loc;
1440 int i, j;
1441
1442 enum rtx_code code = GET_CODE (x);
1443 switch (code)
1444 {
1445 case CONST:
1446 CASE_CONST_ANY:
1447 case SYMBOL_REF:
1448 case LABEL_REF:
1449 case CC0:
1450 case PC:
1451 return;
1452
1453 case REG:
1454 scan_rtx_reg (insn, loc, cl, action, type);
1455 return;
1456
1457 case MEM:
1458 {
1459 reg_class bclass = base_reg_class_for_rename (insn, GET_MODE (x),
1460 MEM_ADDR_SPACE (x),
1461 MEM, SCRATCH);
1462
1463 scan_rtx_address (insn, &XEXP (x, 0), bclass, action, GET_MODE (x),
1464 MEM_ADDR_SPACE (x));
1465 }
1466 return;
1467
1468 case SET:
1469 scan_rtx (insn, &SET_SRC (x), cl, action, OP_IN);
1470 scan_rtx (insn, &SET_DEST (x), cl, action,
1471 (GET_CODE (PATTERN (insn)) == COND_EXEC
1472 && verify_reg_tracked (SET_DEST (x))) ? OP_INOUT : OP_OUT);
1473 return;
1474
1475 case STRICT_LOW_PART:
1476 scan_rtx (insn, &XEXP (x, 0), cl, action,
1477 verify_reg_tracked (XEXP (x, 0)) ? OP_INOUT : OP_OUT);
1478 return;
1479
1480 case ZERO_EXTRACT:
1481 case SIGN_EXTRACT:
1482 scan_rtx (insn, &XEXP (x, 0), cl, action,
1483 (type == OP_IN ? OP_IN :
1484 verify_reg_tracked (XEXP (x, 0)) ? OP_INOUT : OP_OUT));
1485 scan_rtx (insn, &XEXP (x, 1), cl, action, OP_IN);
1486 scan_rtx (insn, &XEXP (x, 2), cl, action, OP_IN);
1487 return;
1488
1489 case POST_INC:
1490 case PRE_INC:
1491 case POST_DEC:
1492 case PRE_DEC:
1493 case POST_MODIFY:
1494 case PRE_MODIFY:
1495 /* Should only happen inside MEM. */
1496 gcc_unreachable ();
1497
1498 case CLOBBER:
1499 scan_rtx (insn, &SET_DEST (x), cl, action,
1500 (GET_CODE (PATTERN (insn)) == COND_EXEC
1501 && verify_reg_tracked (SET_DEST (x))) ? OP_INOUT : OP_OUT);
1502 return;
1503
1504 case EXPR_LIST:
1505 scan_rtx (insn, &XEXP (x, 0), cl, action, type);
1506 if (XEXP (x, 1))
1507 scan_rtx (insn, &XEXP (x, 1), cl, action, type);
1508 return;
1509
1510 default:
1511 break;
1512 }
1513
1514 fmt = GET_RTX_FORMAT (code);
1515 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1516 {
1517 if (fmt[i] == 'e')
1518 scan_rtx (insn, &XEXP (x, i), cl, action, type);
1519 else if (fmt[i] == 'E')
1520 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
1521 scan_rtx (insn, &XVECEXP (x, i, j), cl, action, type);
1522 }
1523 }
1524
1525 /* Hide operands of the current insn (of which there are N_OPS) by
1526 substituting pc for them.
1527 Previous values are stored in the OLD_OPERANDS and OLD_DUPS.
1528 For every bit set in DO_NOT_HIDE, we leave the operand alone.
1529 If INOUT_AND_EC_ONLY is set, we only do this for OP_INOUT type operands
1530 and earlyclobbers. */
1531
1532 static void
hide_operands(int n_ops,rtx * old_operands,rtx * old_dups,unsigned HOST_WIDE_INT do_not_hide,bool inout_and_ec_only)1533 hide_operands (int n_ops, rtx *old_operands, rtx *old_dups,
1534 unsigned HOST_WIDE_INT do_not_hide, bool inout_and_ec_only)
1535 {
1536 int i;
1537 const operand_alternative *op_alt = which_op_alt ();
1538 for (i = 0; i < n_ops; i++)
1539 {
1540 old_operands[i] = recog_data.operand[i];
1541 /* Don't squash match_operator or match_parallel here, since
1542 we don't know that all of the contained registers are
1543 reachable by proper operands. */
1544 if (recog_data.constraints[i][0] == '\0')
1545 continue;
1546 if (do_not_hide & (1 << i))
1547 continue;
1548 if (!inout_and_ec_only || recog_data.operand_type[i] == OP_INOUT
1549 || op_alt[i].earlyclobber)
1550 *recog_data.operand_loc[i] = pc_rtx;
1551 }
1552 for (i = 0; i < recog_data.n_dups; i++)
1553 {
1554 int opn = recog_data.dup_num[i];
1555 old_dups[i] = *recog_data.dup_loc[i];
1556 if (do_not_hide & (1 << opn))
1557 continue;
1558 if (!inout_and_ec_only || recog_data.operand_type[opn] == OP_INOUT
1559 || op_alt[opn].earlyclobber)
1560 *recog_data.dup_loc[i] = pc_rtx;
1561 }
1562 }
1563
1564 /* Undo the substitution performed by hide_operands. INSN is the insn we
1565 are processing; the arguments are the same as in hide_operands. */
1566
1567 static void
restore_operands(rtx_insn * insn,int n_ops,rtx * old_operands,rtx * old_dups)1568 restore_operands (rtx_insn *insn, int n_ops, rtx *old_operands, rtx *old_dups)
1569 {
1570 int i;
1571 for (i = 0; i < recog_data.n_dups; i++)
1572 *recog_data.dup_loc[i] = old_dups[i];
1573 for (i = 0; i < n_ops; i++)
1574 *recog_data.operand_loc[i] = old_operands[i];
1575 if (recog_data.n_dups)
1576 df_insn_rescan (insn);
1577 }
1578
1579 /* For each output operand of INSN, call scan_rtx to create a new
1580 open chain. Do this only for normal or earlyclobber outputs,
1581 depending on EARLYCLOBBER. If INSN_INFO is nonnull, use it to
1582 record information about the operands in the insn. */
1583
1584 static void
record_out_operands(rtx_insn * insn,bool earlyclobber,insn_rr_info * insn_info)1585 record_out_operands (rtx_insn *insn, bool earlyclobber, insn_rr_info *insn_info)
1586 {
1587 int n_ops = recog_data.n_operands;
1588 const operand_alternative *op_alt = which_op_alt ();
1589
1590 int i;
1591
1592 for (i = 0; i < n_ops + recog_data.n_dups; i++)
1593 {
1594 int opn = i < n_ops ? i : recog_data.dup_num[i - n_ops];
1595 rtx *loc = (i < n_ops
1596 ? recog_data.operand_loc[opn]
1597 : recog_data.dup_loc[i - n_ops]);
1598 rtx op = *loc;
1599 enum reg_class cl = alternative_class (op_alt, opn);
1600
1601 class du_head *prev_open;
1602
1603 if (recog_data.operand_type[opn] != OP_OUT
1604 || op_alt[opn].earlyclobber != earlyclobber)
1605 continue;
1606
1607 if (insn_info)
1608 cur_operand = insn_info->op_info + i;
1609
1610 prev_open = open_chains;
1611 if (earlyclobber)
1612 scan_rtx (insn, loc, cl, terminate_write, OP_OUT);
1613 scan_rtx (insn, loc, cl, mark_write, OP_OUT);
1614
1615 /* ??? Many targets have output constraints on the SET_DEST
1616 of a call insn, which is stupid, since these are certainly
1617 ABI defined hard registers. For these, and for asm operands
1618 that originally referenced hard registers, we must record that
1619 the chain cannot be renamed. */
1620 if (CALL_P (insn)
1621 || (asm_noperands (PATTERN (insn)) > 0
1622 && REG_P (op)
1623 && REGNO (op) == ORIGINAL_REGNO (op)))
1624 {
1625 if (prev_open != open_chains)
1626 open_chains->cannot_rename = 1;
1627 }
1628 }
1629 cur_operand = NULL;
1630 }
1631
1632 /* Build def/use chain. */
1633
1634 static bool
build_def_use(basic_block bb)1635 build_def_use (basic_block bb)
1636 {
1637 rtx_insn *insn;
1638 unsigned HOST_WIDE_INT untracked_operands;
1639
1640 fail_current_block = false;
1641
1642 for (insn = BB_HEAD (bb); ; insn = NEXT_INSN (insn))
1643 {
1644 if (NONDEBUG_INSN_P (insn))
1645 {
1646 int n_ops;
1647 rtx note;
1648 rtx old_operands[MAX_RECOG_OPERANDS];
1649 rtx old_dups[MAX_DUP_OPERANDS];
1650 int i;
1651 int predicated;
1652 enum rtx_code set_code = SET;
1653 enum rtx_code clobber_code = CLOBBER;
1654 insn_rr_info *insn_info = NULL;
1655 terminated_this_insn = NULL;
1656
1657 /* Process the insn, determining its effect on the def-use
1658 chains and live hard registers. We perform the following
1659 steps with the register references in the insn, simulating
1660 its effect:
1661 (1) Deal with earlyclobber operands and CLOBBERs of non-operands
1662 by creating chains and marking hard regs live.
1663 (2) Any read outside an operand causes any chain it overlaps
1664 with to be marked unrenamable.
1665 (3) Any read inside an operand is added if there's already
1666 an open chain for it.
1667 (4) For any REG_DEAD note we find, close open chains that
1668 overlap it.
1669 (5) For any non-earlyclobber write we find, close open chains
1670 that overlap it.
1671 (6) For any non-earlyclobber write we find in an operand, make
1672 a new chain or mark the hard register as live.
1673 (7) For any REG_UNUSED, close any chains we just opened.
1674 (8) For any REG_CFA_RESTORE or REG_CFA_REGISTER, kill any chain
1675 containing its dest.
1676
1677 We cannot deal with situations where we track a reg in one mode
1678 and see a reference in another mode; these will cause the chain
1679 to be marked unrenamable or even cause us to abort the entire
1680 basic block. */
1681
1682 extract_constrain_insn (insn);
1683 preprocess_constraints (insn);
1684 const operand_alternative *op_alt = which_op_alt ();
1685 n_ops = recog_data.n_operands;
1686 untracked_operands = 0;
1687
1688 if (insn_rr.exists ())
1689 {
1690 insn_info = &insn_rr[INSN_UID (insn)];
1691 insn_info->op_info = XOBNEWVEC (&rename_obstack, operand_rr_info,
1692 recog_data.n_operands);
1693 memset (insn_info->op_info, 0,
1694 sizeof (operand_rr_info) * recog_data.n_operands);
1695 }
1696
1697 /* Simplify the code below by promoting OP_OUT to OP_INOUT in
1698 predicated instructions, but only for register operands
1699 that are already tracked, so that we can create a chain
1700 when the first SET makes a register live. */
1701
1702 predicated = GET_CODE (PATTERN (insn)) == COND_EXEC;
1703 for (i = 0; i < n_ops; ++i)
1704 {
1705 rtx op = recog_data.operand[i];
1706 int matches = op_alt[i].matches;
1707 if (matches >= 0 || op_alt[i].matched >= 0
1708 || (predicated && recog_data.operand_type[i] == OP_OUT))
1709 {
1710 recog_data.operand_type[i] = OP_INOUT;
1711 /* A special case to deal with instruction patterns that
1712 have matching operands with different modes. If we're
1713 not already tracking such a reg, we won't start here,
1714 and we must instead make sure to make the operand visible
1715 to the machinery that tracks hard registers. */
1716 machine_mode i_mode = recog_data.operand_mode[i];
1717 if (matches >= 0)
1718 {
1719 machine_mode matches_mode
1720 = recog_data.operand_mode[matches];
1721
1722 if (maybe_ne (GET_MODE_SIZE (i_mode),
1723 GET_MODE_SIZE (matches_mode))
1724 && !verify_reg_in_set (op, &live_in_chains))
1725 {
1726 untracked_operands |= 1 << i;
1727 untracked_operands |= 1 << matches;
1728 }
1729 }
1730 }
1731 #ifdef STACK_REGS
1732 if (regstack_completed
1733 && REG_P (op)
1734 && IN_RANGE (REGNO (op), FIRST_STACK_REG, LAST_STACK_REG))
1735 untracked_operands |= 1 << i;
1736 #endif
1737 /* If there's an in-out operand with a register that is not
1738 being tracked at all yet, open a chain. */
1739 if (recog_data.operand_type[i] == OP_INOUT
1740 && !(untracked_operands & (1 << i))
1741 && REG_P (op)
1742 && !verify_reg_tracked (op))
1743 create_new_chain (REGNO (op), REG_NREGS (op), NULL, NULL,
1744 NO_REGS);
1745 }
1746
1747 if (fail_current_block)
1748 break;
1749
1750 /* Step 1a: Mark hard registers that are clobbered in this insn,
1751 outside an operand, as live. */
1752 hide_operands (n_ops, old_operands, old_dups, untracked_operands,
1753 false);
1754 note_stores (insn, note_sets_clobbers, &clobber_code);
1755 restore_operands (insn, n_ops, old_operands, old_dups);
1756
1757 /* Step 1b: Begin new chains for earlyclobbered writes inside
1758 operands. */
1759 record_out_operands (insn, true, insn_info);
1760
1761 /* Step 2: Mark chains for which we have reads outside operands
1762 as unrenamable.
1763 We do this by munging all operands into PC, and closing
1764 everything remaining. */
1765
1766 hide_operands (n_ops, old_operands, old_dups, untracked_operands,
1767 false);
1768 scan_rtx (insn, &PATTERN (insn), NO_REGS, mark_all_read, OP_IN);
1769 restore_operands (insn, n_ops, old_operands, old_dups);
1770
1771 /* Step 2B: Can't rename function call argument registers. */
1772 if (CALL_P (insn) && CALL_INSN_FUNCTION_USAGE (insn))
1773 scan_rtx (insn, &CALL_INSN_FUNCTION_USAGE (insn),
1774 NO_REGS, mark_all_read, OP_IN);
1775
1776 /* Step 2C: Can't rename asm operands that were originally
1777 hard registers. */
1778 if (asm_noperands (PATTERN (insn)) > 0)
1779 for (i = 0; i < n_ops; i++)
1780 {
1781 rtx *loc = recog_data.operand_loc[i];
1782 rtx op = *loc;
1783
1784 if (REG_P (op)
1785 && REGNO (op) == ORIGINAL_REGNO (op)
1786 && (recog_data.operand_type[i] == OP_IN
1787 || recog_data.operand_type[i] == OP_INOUT))
1788 scan_rtx (insn, loc, NO_REGS, mark_all_read, OP_IN);
1789 }
1790
1791 /* Step 3: Append to chains for reads inside operands. */
1792 for (i = 0; i < n_ops + recog_data.n_dups; i++)
1793 {
1794 int opn = i < n_ops ? i : recog_data.dup_num[i - n_ops];
1795 rtx *loc = (i < n_ops
1796 ? recog_data.operand_loc[opn]
1797 : recog_data.dup_loc[i - n_ops]);
1798 enum reg_class cl = alternative_class (op_alt, opn);
1799 enum op_type type = recog_data.operand_type[opn];
1800
1801 /* Don't scan match_operand here, since we've no reg class
1802 information to pass down. Any operands that we could
1803 substitute in will be represented elsewhere. */
1804 if (recog_data.constraints[opn][0] == '\0'
1805 || untracked_operands & (1 << opn))
1806 continue;
1807
1808 if (insn_info)
1809 cur_operand = i == opn ? insn_info->op_info + i : NULL;
1810 if (op_alt[opn].is_address)
1811 scan_rtx_address (insn, loc, cl, mark_read,
1812 VOIDmode, ADDR_SPACE_GENERIC);
1813 else
1814 scan_rtx (insn, loc, cl, mark_read, type);
1815 }
1816 cur_operand = NULL;
1817
1818 /* Step 3B: Record updates for regs in REG_INC notes, and
1819 source regs in REG_FRAME_RELATED_EXPR notes. */
1820 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
1821 if (REG_NOTE_KIND (note) == REG_INC
1822 || REG_NOTE_KIND (note) == REG_FRAME_RELATED_EXPR)
1823 scan_rtx (insn, &XEXP (note, 0), ALL_REGS, mark_read,
1824 OP_INOUT);
1825
1826 /* Step 4: Close chains for registers that die here, unless
1827 the register is mentioned in a REG_UNUSED note. In that
1828 case we keep the chain open until step #7 below to ensure
1829 it conflicts with other output operands of this insn.
1830 See PR 52573. Arguably the insn should not have both
1831 notes; it has proven difficult to fix that without
1832 other undesirable side effects. */
1833 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
1834 if (REG_NOTE_KIND (note) == REG_DEAD
1835 && !find_regno_note (insn, REG_UNUSED, REGNO (XEXP (note, 0))))
1836 {
1837 remove_from_hard_reg_set (&live_hard_regs,
1838 GET_MODE (XEXP (note, 0)),
1839 REGNO (XEXP (note, 0)));
1840 scan_rtx (insn, &XEXP (note, 0), NO_REGS, terminate_dead,
1841 OP_IN);
1842 }
1843
1844 /* Step 4B: If this is a call, any chain live at this point
1845 requires a caller-saved reg. */
1846 if (CALL_P (insn))
1847 {
1848 function_abi callee_abi = insn_callee_abi (insn);
1849 class du_head *p;
1850 for (p = open_chains; p; p = p->next_chain)
1851 {
1852 p->call_abis |= (1 << callee_abi.id ());
1853 p->call_clobber_mask
1854 |= callee_abi.full_and_partial_reg_clobbers ();
1855 p->hard_conflicts |= callee_abi.full_reg_clobbers ();
1856 }
1857 }
1858
1859 /* Step 5: Close open chains that overlap writes. Similar to
1860 step 2, we hide in-out operands, since we do not want to
1861 close these chains. We also hide earlyclobber operands,
1862 since we've opened chains for them in step 1, and earlier
1863 chains they would overlap with must have been closed at
1864 the previous insn at the latest, as such operands cannot
1865 possibly overlap with any input operands. */
1866
1867 hide_operands (n_ops, old_operands, old_dups, untracked_operands,
1868 true);
1869 scan_rtx (insn, &PATTERN (insn), NO_REGS, terminate_write, OP_IN);
1870 restore_operands (insn, n_ops, old_operands, old_dups);
1871
1872 /* Step 6a: Mark hard registers that are set in this insn,
1873 outside an operand, as live. */
1874 hide_operands (n_ops, old_operands, old_dups, untracked_operands,
1875 false);
1876 note_stores (insn, note_sets_clobbers, &set_code);
1877 restore_operands (insn, n_ops, old_operands, old_dups);
1878
1879 /* Step 6b: Begin new chains for writes inside operands. */
1880 record_out_operands (insn, false, insn_info);
1881
1882 /* Step 6c: Record destination regs in REG_FRAME_RELATED_EXPR
1883 notes for update. */
1884 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
1885 if (REG_NOTE_KIND (note) == REG_FRAME_RELATED_EXPR)
1886 scan_rtx (insn, &XEXP (note, 0), ALL_REGS, mark_access,
1887 OP_INOUT);
1888
1889 /* Step 7: Close chains for registers that were never
1890 really used here. */
1891 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
1892 if (REG_NOTE_KIND (note) == REG_UNUSED)
1893 {
1894 remove_from_hard_reg_set (&live_hard_regs,
1895 GET_MODE (XEXP (note, 0)),
1896 REGNO (XEXP (note, 0)));
1897 scan_rtx (insn, &XEXP (note, 0), NO_REGS, terminate_dead,
1898 OP_IN);
1899 }
1900
1901 /* Step 8: Kill the chains involving register restores. Those
1902 should restore _that_ register. Similar for REG_CFA_REGISTER. */
1903 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
1904 if (REG_NOTE_KIND (note) == REG_CFA_RESTORE
1905 || REG_NOTE_KIND (note) == REG_CFA_REGISTER)
1906 {
1907 rtx *x = &XEXP (note, 0);
1908 if (!*x)
1909 x = &PATTERN (insn);
1910 if (GET_CODE (*x) == PARALLEL)
1911 x = &XVECEXP (*x, 0, 0);
1912 if (GET_CODE (*x) == SET)
1913 x = &SET_DEST (*x);
1914 scan_rtx (insn, x, NO_REGS, mark_all_read, OP_IN);
1915 }
1916 }
1917 else if (DEBUG_BIND_INSN_P (insn)
1918 && !VAR_LOC_UNKNOWN_P (INSN_VAR_LOCATION_LOC (insn)))
1919 {
1920 scan_rtx (insn, &INSN_VAR_LOCATION_LOC (insn),
1921 ALL_REGS, mark_read, OP_IN);
1922 }
1923 if (insn == BB_END (bb))
1924 break;
1925 }
1926
1927 if (fail_current_block)
1928 return false;
1929
1930 return true;
1931 }
1932
1933 /* Initialize the register renamer. If INSN_INFO is true, ensure that
1934 insn_rr is nonnull. */
1935 void
regrename_init(bool insn_info)1936 regrename_init (bool insn_info)
1937 {
1938 gcc_obstack_init (&rename_obstack);
1939 insn_rr.create (0);
1940 if (insn_info)
1941 insn_rr.safe_grow_cleared (get_max_uid ());
1942 }
1943
1944 /* Free all global data used by the register renamer. */
1945 void
regrename_finish(void)1946 regrename_finish (void)
1947 {
1948 insn_rr.release ();
1949 free_chain_data ();
1950 obstack_free (&rename_obstack, NULL);
1951 }
1952
1953 /* Perform register renaming on the current function. */
1954
1955 static unsigned int
regrename_optimize(void)1956 regrename_optimize (void)
1957 {
1958 df_set_flags (DF_LR_RUN_DCE);
1959 df_note_add_problem ();
1960 df_analyze ();
1961 df_set_flags (DF_DEFER_INSN_RESCAN);
1962
1963 regrename_init (false);
1964
1965 regrename_analyze (NULL);
1966
1967 rename_chains ();
1968
1969 regrename_finish ();
1970
1971 return 0;
1972 }
1973
1974 namespace {
1975
1976 const pass_data pass_data_regrename =
1977 {
1978 RTL_PASS, /* type */
1979 "rnreg", /* name */
1980 OPTGROUP_NONE, /* optinfo_flags */
1981 TV_RENAME_REGISTERS, /* tv_id */
1982 0, /* properties_required */
1983 0, /* properties_provided */
1984 0, /* properties_destroyed */
1985 0, /* todo_flags_start */
1986 TODO_df_finish, /* todo_flags_finish */
1987 };
1988
1989 class pass_regrename : public rtl_opt_pass
1990 {
1991 public:
pass_regrename(gcc::context * ctxt)1992 pass_regrename (gcc::context *ctxt)
1993 : rtl_opt_pass (pass_data_regrename, ctxt)
1994 {}
1995
1996 /* opt_pass methods: */
gate(function *)1997 virtual bool gate (function *)
1998 {
1999 return (optimize > 0 && (flag_rename_registers));
2000 }
2001
execute(function *)2002 virtual unsigned int execute (function *) { return regrename_optimize (); }
2003
2004 }; // class pass_regrename
2005
2006 } // anon namespace
2007
2008 rtl_opt_pass *
make_pass_regrename(gcc::context * ctxt)2009 make_pass_regrename (gcc::context *ctxt)
2010 {
2011 return new pass_regrename (ctxt);
2012 }
2013