1 /* CPU data header for sh. 2 3 THIS FILE IS MACHINE GENERATED WITH CGEN. 4 5 Copyright 1996-2010 Free Software Foundation, Inc. 6 7 This file is part of the GNU Binutils and/or GDB, the GNU debugger. 8 9 This file is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 3, or (at your option) 12 any later version. 13 14 It is distributed in the hope that it will be useful, but WITHOUT 15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 17 License for more details. 18 19 You should have received a copy of the GNU General Public License along 20 with this program; if not, write to the Free Software Foundation, Inc., 21 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. 22 23 */ 24 25 #ifndef SH_CPU_H 26 #define SH_CPU_H 27 28 #define CGEN_ARCH sh 29 30 /* Given symbol S, return sh_cgen_<S>. */ 31 #define CGEN_SYM(s) sh##_cgen_##s 32 33 34 /* Selected cpu families. */ 35 #define HAVE_CPU_SH64 36 37 #define CGEN_INSN_LSB0_P 0 38 39 /* Minimum size of any insn (in bytes). */ 40 #define CGEN_MIN_INSN_SIZE 2 41 42 /* Maximum size of any insn (in bytes). */ 43 #define CGEN_MAX_INSN_SIZE 4 44 45 #define CGEN_INT_INSN_P 1 46 47 /* Maximum number of syntax elements in an instruction. */ 48 #define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 22 49 50 /* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands. 51 e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands 52 we can't hash on everything up to the space. */ 53 #define CGEN_MNEMONIC_OPERANDS 54 55 /* Maximum number of fields in an instruction. */ 56 #define CGEN_ACTUAL_MAX_IFMT_OPERANDS 8 57 58 /* Enums. */ 59 60 /* Enum declaration for . */ 61 typedef enum frc_names { 62 H_FRC_FR0, H_FRC_FR1, H_FRC_FR2, H_FRC_FR3 63 , H_FRC_FR4, H_FRC_FR5, H_FRC_FR6, H_FRC_FR7 64 , H_FRC_FR8, H_FRC_FR9, H_FRC_FR10, H_FRC_FR11 65 , H_FRC_FR12, H_FRC_FR13, H_FRC_FR14, H_FRC_FR15 66 } FRC_NAMES; 67 68 /* Enum declaration for . */ 69 typedef enum drc_names { 70 H_DRC_DR0 = 0, H_DRC_DR2 = 2, H_DRC_DR4 = 4, H_DRC_DR6 = 6 71 , H_DRC_DR8 = 8, H_DRC_DR10 = 10, H_DRC_DR12 = 12, H_DRC_DR14 = 14 72 } DRC_NAMES; 73 74 /* Enum declaration for . */ 75 typedef enum xf_names { 76 H_XF_XF0, H_XF_XF1, H_XF_XF2, H_XF_XF3 77 , H_XF_XF4, H_XF_XF5, H_XF_XF6, H_XF_XF7 78 , H_XF_XF8, H_XF_XF9, H_XF_XF10, H_XF_XF11 79 , H_XF_XF12, H_XF_XF13, H_XF_XF14, H_XF_XF15 80 } XF_NAMES; 81 82 /* Attributes. */ 83 84 /* Enum declaration for machine type selection. */ 85 typedef enum mach_attr { 86 MACH_BASE, MACH_SH2, MACH_SH2E, MACH_SH2A_FPU 87 , MACH_SH2A_NOFPU, MACH_SH3, MACH_SH3E, MACH_SH4_NOFPU 88 , MACH_SH4, MACH_SH4A_NOFPU, MACH_SH4A, MACH_SH4AL 89 , MACH_SH5, MACH_MAX 90 } MACH_ATTR; 91 92 /* Enum declaration for instruction set selection. */ 93 typedef enum isa_attr { 94 ISA_COMPACT, ISA_MEDIA, ISA_MAX 95 } ISA_ATTR; 96 97 /* Enum declaration for sh4 insn groups. */ 98 typedef enum sh4_group_attr { 99 SH4_GROUP_NONE, SH4_GROUP_MT, SH4_GROUP_EX, SH4_GROUP_BR 100 , SH4_GROUP_LS, SH4_GROUP_FE, SH4_GROUP_CO, SH4_GROUP_MAX 101 } SH4_GROUP_ATTR; 102 103 /* Enum declaration for sh4a insn groups. */ 104 typedef enum sh4a_group_attr { 105 SH4A_GROUP_NONE, SH4A_GROUP_MT, SH4A_GROUP_EX, SH4A_GROUP_BR 106 , SH4A_GROUP_LS, SH4A_GROUP_FE, SH4A_GROUP_CO, SH4A_GROUP_MAX 107 } SH4A_GROUP_ATTR; 108 109 /* Number of architecture variants. */ 110 #define MAX_ISAS ((int) ISA_MAX) 111 #define MAX_MACHS ((int) MACH_MAX) 112 113 /* Ifield support. */ 114 115 /* Ifield attribute indices. */ 116 117 /* Enum declaration for cgen_ifld attrs. */ 118 typedef enum cgen_ifld_attr { 119 CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED 120 , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31 121 , CGEN_IFLD_MACH, CGEN_IFLD_ISA, CGEN_IFLD_END_NBOOLS 122 } CGEN_IFLD_ATTR; 123 124 /* Number of non-boolean elements in cgen_ifld_attr. */ 125 #define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1) 126 127 /* cgen_ifld attribute accessor macros. */ 128 #define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset) 129 #define CGEN_ATTR_CGEN_IFLD_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_ISA-CGEN_IFLD_START_NBOOLS-1].bitset) 130 #define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_VIRTUAL)) != 0) 131 #define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_PCREL_ADDR)) != 0) 132 #define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_ABS_ADDR)) != 0) 133 #define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_RESERVED)) != 0) 134 #define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGN_OPT)) != 0) 135 #define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGNED)) != 0) 136 137 /* Enum declaration for sh ifield types. */ 138 typedef enum ifield_type { 139 SH_F_NIL, SH_F_ANYOF, SH_F_OP4, SH_F_OP8 140 , SH_F_OP16, SH_F_SUB4, SH_F_SUB8, SH_F_SUB10 141 , SH_F_RN, SH_F_RM, SH_F_7_1, SH_F_11_1 142 , SH_F_16_4, SH_F_DISP8, SH_F_DISP12, SH_F_IMM8 143 , SH_F_IMM4, SH_F_IMM4X2, SH_F_IMM4X4, SH_F_IMM8X2 144 , SH_F_IMM8X4, SH_F_IMM12X4, SH_F_IMM12X8, SH_F_DN 145 , SH_F_DM, SH_F_VN, SH_F_VM, SH_F_XN 146 , SH_F_XM, SH_F_IMM20_HI, SH_F_IMM20_LO, SH_F_IMM20 147 , SH_F_OP, SH_F_EXT, SH_F_RSVD, SH_F_LEFT 148 , SH_F_RIGHT, SH_F_DEST, SH_F_LEFT_RIGHT, SH_F_TRA 149 , SH_F_TRB, SH_F_LIKELY, SH_F_6_3, SH_F_23_2 150 , SH_F_IMM6, SH_F_IMM10, SH_F_IMM16, SH_F_UIMM6 151 , SH_F_UIMM16, SH_F_DISP6, SH_F_DISP6X32, SH_F_DISP10 152 , SH_F_DISP10X8, SH_F_DISP10X4, SH_F_DISP10X2, SH_F_DISP16 153 , SH_F_MAX 154 } IFIELD_TYPE; 155 156 #define MAX_IFLD ((int) SH_F_MAX) 157 158 /* Hardware attribute indices. */ 159 160 /* Enum declaration for cgen_hw attrs. */ 161 typedef enum cgen_hw_attr { 162 CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE 163 , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_ISA 164 , CGEN_HW_END_NBOOLS 165 } CGEN_HW_ATTR; 166 167 /* Number of non-boolean elements in cgen_hw_attr. */ 168 #define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1) 169 170 /* cgen_hw attribute accessor macros. */ 171 #define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset) 172 #define CGEN_ATTR_CGEN_HW_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_ISA-CGEN_HW_START_NBOOLS-1].bitset) 173 #define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_VIRTUAL)) != 0) 174 #define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_CACHE_ADDR)) != 0) 175 #define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PC)) != 0) 176 #define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PROFILE)) != 0) 177 178 /* Enum declaration for sh hardware types. */ 179 typedef enum cgen_hw_type { 180 HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR 181 , HW_H_IADDR, HW_H_PC, HW_H_GR, HW_H_GRC 182 , HW_H_CR, HW_H_SR, HW_H_FPSCR, HW_H_FRBIT 183 , HW_H_SZBIT, HW_H_PRBIT, HW_H_SBIT, HW_H_MBIT 184 , HW_H_QBIT, HW_H_FR, HW_H_FP, HW_H_FV 185 , HW_H_FMTX, HW_H_DR, HW_H_FSD, HW_H_FMOV 186 , HW_H_TR, HW_H_ENDIAN, HW_H_ISM, HW_H_FRC 187 , HW_H_DRC, HW_H_XF, HW_H_XD, HW_H_FVC 188 , HW_H_GBR, HW_H_VBR, HW_H_PR, HW_H_MACL 189 , HW_H_MACH, HW_H_TBIT, HW_MAX 190 } CGEN_HW_TYPE; 191 192 #define MAX_HW ((int) HW_MAX) 193 194 /* Operand attribute indices. */ 195 196 /* Enum declaration for cgen_operand attrs. */ 197 typedef enum cgen_operand_attr { 198 CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT 199 , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY 200 , CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH, CGEN_OPERAND_ISA 201 , CGEN_OPERAND_END_NBOOLS 202 } CGEN_OPERAND_ATTR; 203 204 /* Number of non-boolean elements in cgen_operand_attr. */ 205 #define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1) 206 207 /* cgen_operand attribute accessor macros. */ 208 #define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset) 209 #define CGEN_ATTR_CGEN_OPERAND_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_ISA-CGEN_OPERAND_START_NBOOLS-1].bitset) 210 #define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_VIRTUAL)) != 0) 211 #define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0) 212 #define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_ABS_ADDR)) != 0) 213 #define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGN_OPT)) != 0) 214 #define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGNED)) != 0) 215 #define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_NEGATIVE)) != 0) 216 #define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_RELAX)) != 0) 217 #define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SEM_ONLY)) != 0) 218 219 /* Enum declaration for sh operand types. */ 220 typedef enum cgen_operand_type { 221 SH_OPERAND_PC, SH_OPERAND_ENDIAN, SH_OPERAND_ISM, SH_OPERAND_RM 222 , SH_OPERAND_RN, SH_OPERAND_R0, SH_OPERAND_FRN, SH_OPERAND_FRM 223 , SH_OPERAND_FR0, SH_OPERAND_FMOVN, SH_OPERAND_FMOVM, SH_OPERAND_FVN 224 , SH_OPERAND_FVM, SH_OPERAND_DRN, SH_OPERAND_DRM, SH_OPERAND_IMM4 225 , SH_OPERAND_IMM8, SH_OPERAND_UIMM8, SH_OPERAND_IMM20, SH_OPERAND_IMM4X2 226 , SH_OPERAND_IMM4X4, SH_OPERAND_IMM8X2, SH_OPERAND_IMM8X4, SH_OPERAND_DISP8 227 , SH_OPERAND_DISP12, SH_OPERAND_IMM12X4, SH_OPERAND_IMM12X8, SH_OPERAND_RM64 228 , SH_OPERAND_RN64, SH_OPERAND_GBR, SH_OPERAND_VBR, SH_OPERAND_PR 229 , SH_OPERAND_FPSCR, SH_OPERAND_TBIT, SH_OPERAND_SBIT, SH_OPERAND_MBIT 230 , SH_OPERAND_QBIT, SH_OPERAND_FPUL, SH_OPERAND_FRBIT, SH_OPERAND_SZBIT 231 , SH_OPERAND_PRBIT, SH_OPERAND_MACL, SH_OPERAND_MACH, SH_OPERAND_FSDM 232 , SH_OPERAND_FSDN, SH_OPERAND_RD, SH_OPERAND_FRG, SH_OPERAND_FRH 233 , SH_OPERAND_FRF, SH_OPERAND_FRGH, SH_OPERAND_FPF, SH_OPERAND_FVG 234 , SH_OPERAND_FVH, SH_OPERAND_FVF, SH_OPERAND_MTRXG, SH_OPERAND_DRG 235 , SH_OPERAND_DRH, SH_OPERAND_DRF, SH_OPERAND_DRGH, SH_OPERAND_CRJ 236 , SH_OPERAND_CRK, SH_OPERAND_TRA, SH_OPERAND_TRB, SH_OPERAND_DISP6 237 , SH_OPERAND_DISP6X32, SH_OPERAND_DISP10, SH_OPERAND_DISP10X2, SH_OPERAND_DISP10X4 238 , SH_OPERAND_DISP10X8, SH_OPERAND_DISP16, SH_OPERAND_IMM6, SH_OPERAND_IMM10 239 , SH_OPERAND_IMM16, SH_OPERAND_UIMM6, SH_OPERAND_UIMM16, SH_OPERAND_LIKELY 240 , SH_OPERAND_MAX 241 } CGEN_OPERAND_TYPE; 242 243 /* Number of operands types. */ 244 #define MAX_OPERANDS 79 245 246 /* Maximum number of operands referenced by any insn. */ 247 #define MAX_OPERAND_INSTANCES 8 248 249 /* Insn attribute indices. */ 250 251 /* Enum declaration for cgen_insn attrs. */ 252 typedef enum cgen_insn_attr { 253 CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI 254 , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED 255 , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_ILLSLOT, CGEN_INSN_FP_INSN 256 , CGEN_INSN_32_BIT_INSN, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH 257 , CGEN_INSN_ISA, CGEN_INSN_SH4_GROUP, CGEN_INSN_SH4A_GROUP, CGEN_INSN_END_NBOOLS 258 } CGEN_INSN_ATTR; 259 260 /* Number of non-boolean elements in cgen_insn_attr. */ 261 #define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1) 262 263 /* cgen_insn attribute accessor macros. */ 264 #define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset) 265 #define CGEN_ATTR_CGEN_INSN_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_ISA-CGEN_INSN_START_NBOOLS-1].bitset) 266 #define CGEN_ATTR_CGEN_INSN_SH4_GROUP_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_SH4_GROUP-CGEN_INSN_START_NBOOLS-1].nonbitset) 267 #define CGEN_ATTR_CGEN_INSN_SH4A_GROUP_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_SH4A_GROUP-CGEN_INSN_START_NBOOLS-1].nonbitset) 268 #define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_ALIAS)) != 0) 269 #define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_VIRTUAL)) != 0) 270 #define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_UNCOND_CTI)) != 0) 271 #define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_COND_CTI)) != 0) 272 #define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_SKIP_CTI)) != 0) 273 #define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_DELAY_SLOT)) != 0) 274 #define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXABLE)) != 0) 275 #define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXED)) != 0) 276 #define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_NO_DIS)) != 0) 277 #define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_PBB)) != 0) 278 #define CGEN_ATTR_CGEN_INSN_ILLSLOT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_ILLSLOT)) != 0) 279 #define CGEN_ATTR_CGEN_INSN_FP_INSN_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_FP_INSN)) != 0) 280 #define CGEN_ATTR_CGEN_INSN_32_BIT_INSN_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_32_BIT_INSN)) != 0) 281 282 /* cgen.h uses things we just defined. */ 283 #include "opcode/cgen.h" 284 285 extern const struct cgen_ifld sh_cgen_ifld_table[]; 286 287 /* Attributes. */ 288 extern const CGEN_ATTR_TABLE sh_cgen_hardware_attr_table[]; 289 extern const CGEN_ATTR_TABLE sh_cgen_ifield_attr_table[]; 290 extern const CGEN_ATTR_TABLE sh_cgen_operand_attr_table[]; 291 extern const CGEN_ATTR_TABLE sh_cgen_insn_attr_table[]; 292 293 /* Hardware decls. */ 294 295 extern CGEN_KEYWORD sh_cgen_opval_h_gr; 296 extern CGEN_KEYWORD sh_cgen_opval_h_grc; 297 extern CGEN_KEYWORD sh_cgen_opval_h_cr; 298 extern CGEN_KEYWORD sh_cgen_opval_h_fr; 299 extern CGEN_KEYWORD sh_cgen_opval_h_fp; 300 extern CGEN_KEYWORD sh_cgen_opval_h_fv; 301 extern CGEN_KEYWORD sh_cgen_opval_h_fmtx; 302 extern CGEN_KEYWORD sh_cgen_opval_h_dr; 303 extern CGEN_KEYWORD sh_cgen_opval_h_fsd; 304 extern CGEN_KEYWORD sh_cgen_opval_h_fmov; 305 extern CGEN_KEYWORD sh_cgen_opval_h_tr; 306 extern CGEN_KEYWORD sh_cgen_opval_frc_names; 307 extern CGEN_KEYWORD sh_cgen_opval_drc_names; 308 extern CGEN_KEYWORD sh_cgen_opval_xf_names; 309 extern CGEN_KEYWORD sh_cgen_opval_frc_names; 310 extern CGEN_KEYWORD sh_cgen_opval_h_fvc; 311 312 extern const CGEN_HW_ENTRY sh_cgen_hw_table[]; 313 314 315 316 #endif /* SH_CPU_H */ 317