1 /***************************************************************************** 2 * 3 * Copyright (C) 2016 Atmel Corporation 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * * Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 12 * * Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in 14 * the documentation and/or other materials provided with the 15 * distribution. 16 * 17 * * Neither the name of the copyright holders nor the names of 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 ****************************************************************************/ 33 34 35 #ifndef _AVR_ATA6614Q_H_INCLUDED 36 #define _AVR_ATA6614Q_H_INCLUDED 37 38 39 #ifndef _AVR_IO_H_ 40 # error "Include <avr/io.h> instead of this file." 41 #endif 42 43 #ifndef _AVR_IOXXX_H_ 44 # define _AVR_IOXXX_H_ "ioa6614q.h" 45 #else 46 # error "Attempt to include more than one <avr/ioXXX.h> file." 47 #endif 48 49 /* Registers and associated bit numbers */ 50 51 #define PINB _SFR_IO8(0x03) 52 #define PINB7 7 53 #define PINB6 6 54 #define PINB5 5 55 #define PINB4 4 56 #define PINB3 3 57 #define PINB2 2 58 #define PINB1 1 59 #define PINB0 0 60 61 #define DDRB _SFR_IO8(0x04) 62 #define DDB0 0 63 #define DDB1 1 64 #define DDB2 2 65 #define DDB3 3 66 #define DDB4 4 67 #define DDB5 5 68 #define DDB6 6 69 #define DDB7 7 70 71 #define PORTB _SFR_IO8(0x05) 72 #define PORTB7 7 73 #define PORTB6 6 74 #define PORTB5 5 75 #define PORTB4 4 76 #define PORTB3 3 77 #define PORTB2 2 78 #define PORTB1 1 79 #define PORTB0 0 80 81 #define PINC _SFR_IO8(0x06) 82 #define PINC6 6 83 #define PINC5 5 84 #define PINC4 4 85 #define PINC3 3 86 #define PINC2 2 87 #define PINC1 1 88 #define PINC0 0 89 90 #define DDRC _SFR_IO8(0x07) 91 #define DDC0 0 92 #define DDC1 1 93 #define DDC2 2 94 #define DDC3 3 95 #define DDC4 4 96 #define DDC5 5 97 #define DDC6 6 98 99 #define PORTC _SFR_IO8(0x08) 100 #define PORTC6 6 101 #define PORTC5 5 102 #define PORTC4 4 103 #define PORTC3 3 104 #define PORTC2 2 105 #define PORTC1 1 106 #define PORTC0 0 107 108 #define PIND _SFR_IO8(0x09) 109 #define PIND7 7 110 #define PIND6 6 111 #define PIND5 5 112 #define PIND4 4 113 #define PIND3 3 114 #define PIND2 2 115 #define PIND1 1 116 #define PIND0 0 117 118 #define DDRD _SFR_IO8(0x0A) 119 #define DDD0 0 120 #define DDD1 1 121 #define DDD2 2 122 #define DDD3 3 123 #define DDD4 4 124 #define DDD5 5 125 #define DDD6 6 126 #define DDD7 7 127 128 #define PORTD _SFR_IO8(0x0B) 129 #define PORTD7 7 130 #define PORTD6 6 131 #define PORTD5 5 132 #define PORTD4 4 133 #define PORTD3 3 134 #define PORTD2 2 135 #define PORTD1 1 136 #define PORTD0 0 137 138 /* Reserved [0x0C..0x14] */ 139 140 #define TIFR0 _SFR_IO8(0x15) 141 #define TOV0 0 142 #define OCF0A 1 143 #define OCF0B 2 144 145 #define TIFR1 _SFR_IO8(0x16) 146 #define TOV1 0 147 #define OCF1A 1 148 #define OCF1B 2 149 #define ICF1 5 150 151 #define TIFR2 _SFR_IO8(0x17) 152 #define TOV2 0 153 #define OCF2A 1 154 #define OCF2B 2 155 156 /* Reserved [0x18..0x1A] */ 157 158 #define PCIFR _SFR_IO8(0x1B) 159 #define PCIF0 0 160 #define PCIF1 1 161 #define PCIF2 2 162 163 #define EIFR _SFR_IO8(0x1C) 164 #define INTF0 0 165 #define INTF1 1 166 167 #define EIMSK _SFR_IO8(0x1D) 168 #define INT0 0 169 #define INT1 1 170 171 #define GPIOR0 _SFR_IO8(0x1E) 172 173 #define EECR _SFR_IO8(0x1F) 174 #define EERE 0 175 #define EEPE 1 176 #define EEMPE 2 177 #define EERIE 3 178 #define EEPM0 4 179 #define EEPM1 5 180 181 #define EEDR _SFR_IO8(0x20) 182 183 /* Combine EEARL and EEARH */ 184 #define EEAR _SFR_IO16(0x21) 185 186 #define EEARL _SFR_IO8(0x21) 187 #define EEARH _SFR_IO8(0x22) 188 189 #define GTCCR _SFR_IO8(0x23) 190 #define PSRSYNC 0 191 #define TSM 7 192 #define PSRASY 1 193 194 #define TCCR0A _SFR_IO8(0x24) 195 #define WGM00 0 196 #define WGM01 1 197 #define COM0B0 4 198 #define COM0B1 5 199 #define COM0A0 6 200 #define COM0A1 7 201 202 #define TCCR0B _SFR_IO8(0x25) 203 #define CS00 0 204 #define CS01 1 205 #define CS02 2 206 #define WGM02 3 207 #define FOC0B 6 208 #define FOC0A 7 209 210 #define TCNT0 _SFR_IO8(0x26) 211 212 #define OCR0A _SFR_IO8(0x27) 213 214 #define OCR0B _SFR_IO8(0x28) 215 216 /* Reserved [0x29] */ 217 218 #define GPIOR1 _SFR_IO8(0x2A) 219 220 #define GPIOR2 _SFR_IO8(0x2B) 221 222 #define SPCR _SFR_IO8(0x2C) 223 #define SPR0 0 224 #define SPR1 1 225 #define CPHA 2 226 #define CPOL 3 227 #define MSTR 4 228 #define DORD 5 229 #define SPE 6 230 #define SPIE 7 231 232 #define SPSR _SFR_IO8(0x2D) 233 #define SPI2X 0 234 #define WCOL 6 235 #define SPIF 7 236 237 #define SPDR _SFR_IO8(0x2E) 238 239 /* Reserved [0x2F] */ 240 241 #define ACSR _SFR_IO8(0x30) 242 #define ACIS0 0 243 #define ACIS1 1 244 #define ACIC 2 245 #define ACIE 3 246 #define ACI 4 247 #define ACO 5 248 #define ACBG 6 249 #define ACD 7 250 251 /* Reserved [0x31..0x32] */ 252 253 #define SMCR _SFR_IO8(0x33) 254 #define SE 0 255 #define SM0 1 256 #define SM1 2 257 #define SM2 3 258 259 #define MCUSR _SFR_IO8(0x34) 260 #define PORF 0 261 #define EXTRF 1 262 #define BORF 2 263 #define WDRF 3 264 265 #define MCUCR _SFR_IO8(0x35) 266 #define IVCE 0 267 #define IVSEL 1 268 #define PUD 4 269 #define BODSE 5 270 #define BODS 6 271 272 /* Reserved [0x36] */ 273 274 #define SPMCSR _SFR_IO8(0x37) 275 #define SELFPRGEN 0 276 #define PGERS 1 277 #define PGWRT 2 278 #define BLBSET 3 279 #define RWWSRE 4 280 #define RWWSB 6 281 #define SPMIE 7 282 283 /* Reserved [0x38..0x3C] */ 284 285 /* SP [0x3D..0x3E] */ 286 287 /* SREG [0x3F] */ 288 289 #define WDTCSR _SFR_MEM8(0x60) 290 #define WDE 3 291 #define WDCE 4 292 #define WDP0 0 293 #define WDP1 1 294 #define WDP2 2 295 #define WDP3 5 296 #define WDIE 6 297 #define WDIF 7 298 299 #define CLKPR _SFR_MEM8(0x61) 300 #define CLKPS0 0 301 #define CLKPS1 1 302 #define CLKPS2 2 303 #define CLKPS3 3 304 #define CLKPCE 7 305 306 /* Reserved [0x62..0x63] */ 307 308 #define PRR _SFR_MEM8(0x64) 309 #define PRADC 0 310 #define PRUSART0 1 311 #define PRSPI 2 312 #define PRTIM1 3 313 #define PRTIM0 5 314 #define PRTIM2 6 315 #define PRTWI 7 316 317 #define __AVR_HAVE_PRR ((1<<PRADC)|(1<<PRUSART0)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRTIM0)|(1<<PRTIM2)|(1<<PRTWI)) 318 #define __AVR_HAVE_PRR_PRADC 319 #define __AVR_HAVE_PRR_PRUSART0 320 #define __AVR_HAVE_PRR_PRSPI 321 #define __AVR_HAVE_PRR_PRTIM1 322 #define __AVR_HAVE_PRR_PRTIM0 323 #define __AVR_HAVE_PRR_PRTIM2 324 #define __AVR_HAVE_PRR_PRTWI 325 326 /* Reserved [0x65] */ 327 328 #define OSCCAL _SFR_MEM8(0x66) 329 #define OSCCAL0 0 330 #define OSCCAL1 1 331 #define OSCCAL2 2 332 #define OSCCAL3 3 333 #define OSCCAL4 4 334 #define OSCCAL5 5 335 #define OSCCAL6 6 336 #define OSCCAL7 7 337 338 /* Reserved [0x67] */ 339 340 #define PCICR _SFR_MEM8(0x68) 341 #define PCIE0 0 342 #define PCIE1 1 343 #define PCIE2 2 344 345 #define EICRA _SFR_MEM8(0x69) 346 #define ISC00 0 347 #define ISC01 1 348 #define ISC10 2 349 #define ISC11 3 350 351 /* Reserved [0x6A] */ 352 353 #define PCMSK0 _SFR_MEM8(0x6B) 354 #define PCINT0 0 355 #define PCINT1 1 356 #define PCINT2 2 357 #define PCINT3 3 358 #define PCINT4 4 359 #define PCINT5 5 360 #define PCINT6 6 361 #define PCINT7 7 362 363 #define PCMSK1 _SFR_MEM8(0x6C) 364 #define PCINT8 0 365 #define PCINT9 1 366 #define PCINT10 2 367 #define PCINT11 3 368 #define PCINT12 4 369 #define PCINT13 5 370 #define PCINT14 6 371 372 #define PCMSK2 _SFR_MEM8(0x6D) 373 #define PCINT16 0 374 #define PCINT17 1 375 #define PCINT18 2 376 #define PCINT19 3 377 #define PCINT20 4 378 #define PCINT21 5 379 #define PCINT22 6 380 #define PCINT23 7 381 382 #define TIMSK0 _SFR_MEM8(0x6E) 383 #define TOIE0 0 384 #define OCIE0A 1 385 #define OCIE0B 2 386 387 #define TIMSK1 _SFR_MEM8(0x6F) 388 #define TOIE1 0 389 #define OCIE1A 1 390 #define OCIE1B 2 391 #define ICIE1 5 392 393 #define TIMSK2 _SFR_MEM8(0x70) 394 #define TOIE2 0 395 #define OCIE2A 1 396 #define OCIE2B 2 397 398 /* Reserved [0x71..0x77] */ 399 400 /* Combine ADCL and ADCH */ 401 #ifndef __ASSEMBLER__ 402 #define ADC _SFR_MEM16(0x78) 403 #endif 404 #define ADCW _SFR_MEM16(0x78) 405 406 #define ADCL _SFR_MEM8(0x78) 407 #define ADCH _SFR_MEM8(0x79) 408 409 #define ADCSRA _SFR_MEM8(0x7A) 410 #define ADPS0 0 411 #define ADPS1 1 412 #define ADPS2 2 413 #define ADIE 3 414 #define ADIF 4 415 #define ADATE 5 416 #define ADSC 6 417 #define ADEN 7 418 419 #define ADCSRB _SFR_MEM8(0x7B) 420 #define ADTS0 0 421 #define ADTS1 1 422 #define ADTS2 2 423 #define ACME 6 424 425 #define ADMUX _SFR_MEM8(0x7C) 426 #define MUX0 0 427 #define MUX1 1 428 #define MUX2 2 429 #define MUX3 3 430 #define ADLAR 5 431 #define REFS0 6 432 #define REFS1 7 433 434 /* Reserved [0x7D] */ 435 436 #define DIDR0 _SFR_MEM8(0x7E) 437 #define ADC0D 0 438 #define ADC1D 1 439 #define ADC2D 2 440 #define ADC3D 3 441 #define ADC4D 4 442 #define ADC5D 5 443 444 #define DIDR1 _SFR_MEM8(0x7F) 445 #define AIN0D 0 446 #define AIN1D 1 447 448 #define TCCR1A _SFR_MEM8(0x80) 449 #define WGM10 0 450 #define WGM11 1 451 #define COM1B0 4 452 #define COM1B1 5 453 #define COM1A0 6 454 #define COM1A1 7 455 456 #define TCCR1B _SFR_MEM8(0x81) 457 #define CS10 0 458 #define CS11 1 459 #define CS12 2 460 #define WGM12 3 461 #define WGM13 4 462 #define ICES1 6 463 #define ICNC1 7 464 465 #define TCCR1C _SFR_MEM8(0x82) 466 #define FOC1B 6 467 #define FOC1A 7 468 469 /* Reserved [0x83] */ 470 471 /* Combine TCNT1L and TCNT1H */ 472 #define TCNT1 _SFR_MEM16(0x84) 473 474 #define TCNT1L _SFR_MEM8(0x84) 475 #define TCNT1H _SFR_MEM8(0x85) 476 477 /* Combine ICR1L and ICR1H */ 478 #define ICR1 _SFR_MEM16(0x86) 479 480 #define ICR1L _SFR_MEM8(0x86) 481 #define ICR1H _SFR_MEM8(0x87) 482 483 /* Combine OCR1AL and OCR1AH */ 484 #define OCR1A _SFR_MEM16(0x88) 485 486 #define OCR1AL _SFR_MEM8(0x88) 487 #define OCR1AH _SFR_MEM8(0x89) 488 489 /* Combine OCR1BL and OCR1BH */ 490 #define OCR1B _SFR_MEM16(0x8A) 491 492 #define OCR1BL _SFR_MEM8(0x8A) 493 #define OCR1BH _SFR_MEM8(0x8B) 494 495 /* Reserved [0x8C..0xAF] */ 496 497 #define TCCR2A _SFR_MEM8(0xB0) 498 #define WGM20 0 499 #define WGM21 1 500 #define COM2B0 4 501 #define COM2B1 5 502 #define COM2A0 6 503 #define COM2A1 7 504 505 #define TCCR2B _SFR_MEM8(0xB1) 506 #define CS20 0 507 #define CS21 1 508 #define CS22 2 509 #define WGM22 3 510 #define FOC2B 6 511 #define FOC2A 7 512 513 #define TCNT2 _SFR_MEM8(0xB2) 514 515 #define OCR2A _SFR_MEM8(0xB3) 516 517 #define OCR2B _SFR_MEM8(0xB4) 518 519 /* Reserved [0xB5] */ 520 521 #define ASSR _SFR_MEM8(0xB6) 522 #define TCR2BUB 0 523 #define TCR2AUB 1 524 #define OCR2BUB 2 525 #define OCR2AUB 3 526 #define TCN2UB 4 527 #define AS2 5 528 #define EXCLK 6 529 530 /* Reserved [0xB7] */ 531 532 #define TWBR _SFR_MEM8(0xB8) 533 534 #define TWSR _SFR_MEM8(0xB9) 535 #define TWPS0 0 536 #define TWPS1 1 537 #define TWS3 3 538 #define TWS4 4 539 #define TWS5 5 540 #define TWS6 6 541 #define TWS7 7 542 543 #define TWAR _SFR_MEM8(0xBA) 544 #define TWGCE 0 545 #define TWA0 1 546 #define TWA1 2 547 #define TWA2 3 548 #define TWA3 4 549 #define TWA4 5 550 #define TWA5 6 551 #define TWA6 7 552 553 #define TWDR _SFR_MEM8(0xBB) 554 555 #define TWCR _SFR_MEM8(0xBC) 556 #define TWIE 0 557 #define TWEN 2 558 #define TWWC 3 559 #define TWSTO 4 560 #define TWSTA 5 561 #define TWEA 6 562 #define TWINT 7 563 564 #define TWAMR _SFR_MEM8(0xBD) 565 #define TWAM0 1 566 #define TWAM1 2 567 #define TWAM2 3 568 #define TWAM3 4 569 #define TWAM4 5 570 #define TWAM5 6 571 #define TWAM6 7 572 573 /* Reserved [0xBE..0xBF] */ 574 575 #define UCSR0A _SFR_MEM8(0xC0) 576 #define MPCM0 0 577 #define U2X0 1 578 #define UPE0 2 579 #define DOR0 3 580 #define FE0 4 581 #define UDRE0 5 582 #define TXC0 6 583 #define RXC0 7 584 585 #define UCSR0B _SFR_MEM8(0xC1) 586 #define TXB80 0 587 #define RXB80 1 588 #define UCSZ02 2 589 #define TXEN0 3 590 #define RXEN0 4 591 #define UDRIE0 5 592 #define TXCIE0 6 593 #define RXCIE0 7 594 595 #define UCSR0C _SFR_MEM8(0xC2) 596 #define UCPOL0 0 597 #define UCPHA0 1 598 #define UDORD0 2 599 #define UCSZ00 1 600 #define UCSZ01 2 601 #define USBS0 3 602 #define UPM00 4 603 #define UPM01 5 604 #define UMSEL00 6 605 #define UMSEL01 7 606 607 /* Reserved [0xC3] */ 608 609 /* Combine UBRR0L and UBRR0H */ 610 #define UBRR0 _SFR_MEM16(0xC4) 611 612 #define UBRR0L _SFR_MEM8(0xC4) 613 #define UBRR0H _SFR_MEM8(0xC5) 614 615 #define UDR0 _SFR_MEM8(0xC6) 616 617 618 619 /* Values and associated defines */ 620 621 622 #define SLEEP_MODE_IDLE (0x00<<1) 623 #define SLEEP_MODE_ADC (0x01<<1) 624 #define SLEEP_MODE_PWR_DOWN (0x02<<1) 625 #define SLEEP_MODE_PWR_SAVE (0x03<<1) 626 #define SLEEP_MODE_STANDBY (0x06<<1) 627 #define SLEEP_MODE_EXT_STANDBY (0x07<<1) 628 629 /* Interrupt vectors */ 630 /* Vector 0 is the reset vector */ 631 /* External Interrupt Request 0 */ 632 #define INT0_vect _VECTOR(1) 633 #define INT0_vect_num 1 634 635 /* External Interrupt Request 1 */ 636 #define INT1_vect _VECTOR(2) 637 #define INT1_vect_num 2 638 639 /* Pin Change Interrupt Request 0 */ 640 #define PCINT0_vect _VECTOR(3) 641 #define PCINT0_vect_num 3 642 643 /* Pin Change Interrupt Request 0 */ 644 #define PCINT1_vect _VECTOR(4) 645 #define PCINT1_vect_num 4 646 647 /* Pin Change Interrupt Request 1 */ 648 #define PCINT2_vect _VECTOR(5) 649 #define PCINT2_vect_num 5 650 651 /* Watchdog Time-out Interrupt */ 652 #define WDT_vect _VECTOR(6) 653 #define WDT_vect_num 6 654 655 /* Timer/Counter2 Compare Match A */ 656 #define TIMER2_COMPA_vect _VECTOR(7) 657 #define TIMER2_COMPA_vect_num 7 658 659 /* Timer/Counter2 Compare Match A */ 660 #define TIMER2_COMPB_vect _VECTOR(8) 661 #define TIMER2_COMPB_vect_num 8 662 663 /* Timer/Counter2 Overflow */ 664 #define TIMER2_OVF_vect _VECTOR(9) 665 #define TIMER2_OVF_vect_num 9 666 667 /* Timer/Counter1 Capture Event */ 668 #define TIMER1_CAPT_vect _VECTOR(10) 669 #define TIMER1_CAPT_vect_num 10 670 671 /* Timer/Counter1 Compare Match A */ 672 #define TIMER1_COMPA_vect _VECTOR(11) 673 #define TIMER1_COMPA_vect_num 11 674 675 /* Timer/Counter1 Compare Match B */ 676 #define TIMER1_COMPB_vect _VECTOR(12) 677 #define TIMER1_COMPB_vect_num 12 678 679 /* Timer/Counter1 Overflow */ 680 #define TIMER1_OVF_vect _VECTOR(13) 681 #define TIMER1_OVF_vect_num 13 682 683 /* TimerCounter0 Compare Match A */ 684 #define TIMER0_COMPA_vect _VECTOR(14) 685 #define TIMER0_COMPA_vect_num 14 686 687 /* TimerCounter0 Compare Match B */ 688 #define TIMER0_COMPB_vect _VECTOR(15) 689 #define TIMER0_COMPB_vect_num 15 690 691 /* Timer/Couner0 Overflow */ 692 #define TIMER0_OVF_vect _VECTOR(16) 693 #define TIMER0_OVF_vect_num 16 694 695 /* SPI Serial Transfer Complete */ 696 #define SPI_STC_vect _VECTOR(17) 697 #define SPI_STC_vect_num 17 698 699 /* USART Rx Complete */ 700 #define USART_RX_vect _VECTOR(18) 701 #define USART_RX_vect_num 18 702 703 /* USART, Data Register Empty */ 704 #define USART_UDRE_vect _VECTOR(19) 705 #define USART_UDRE_vect_num 19 706 707 /* USART Tx Complete */ 708 #define USART_TX_vect _VECTOR(20) 709 #define USART_TX_vect_num 20 710 711 /* ADC Conversion Complete */ 712 #define ADC_vect _VECTOR(21) 713 #define ADC_vect_num 21 714 715 /* EEPROM Ready */ 716 #define EE_READY_vect _VECTOR(22) 717 #define EE_READY_vect_num 22 718 719 /* Analog Comparator */ 720 #define ANALOG_COMP_vect _VECTOR(23) 721 #define ANALOG_COMP_vect_num 23 722 723 /* Two-wire Serial Interface */ 724 #define TWI_vect _VECTOR(24) 725 #define TWI_vect_num 24 726 727 /* Store Program Memory Read */ 728 #define SPM_Ready_vect _VECTOR(25) 729 #define SPM_Ready_vect_num 25 730 731 #define _VECTORS_SIZE 104 732 733 734 /* Constants */ 735 736 #define SPM_PAGESIZE 128 737 #define FLASHSTART 0x0000 738 #define FLASHEND 0x7FFF 739 #define RAMSTART 0x0100 740 #define RAMSIZE 2048 741 #define RAMEND 0x08FF 742 #define E2START 0 743 #define E2SIZE 1024 744 #define E2PAGESIZE 4 745 #define E2END 0x03FF 746 #define XRAMEND RAMEND 747 748 749 /* Fuses */ 750 751 #define FUSE_MEMORY_SIZE 3 752 753 /* Low Fuse Byte */ 754 #define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0) 755 #define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1) 756 #define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2) 757 #define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3) 758 #define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4) 759 #define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5) 760 #define FUSE_CKOUT (unsigned char)~_BV(6) 761 #define FUSE_CKDIV8 (unsigned char)~_BV(7) 762 #define LFUSE_DEFAULT (FUSE_SUT_CKSEL0 & FUSE_SUT_CKSEL2 & FUSE_SUT_CKSEL3 & FUSE_SUT_CKSEL4 & FUSE_CKDIV8) 763 764 765 /* High Fuse Byte */ 766 #define FUSE_BOOTRST (unsigned char)~_BV(0) 767 #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) 768 #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) 769 #define FUSE_EESAVE (unsigned char)~_BV(3) 770 #define FUSE_WDTON (unsigned char)~_BV(4) 771 #define FUSE_SPIEN (unsigned char)~_BV(5) 772 #define FUSE_DWEN (unsigned char)~_BV(6) 773 #define FUSE_RSTDISBL (unsigned char)~_BV(7) 774 #define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN) 775 776 777 /* Extended Fuse Byte */ 778 #define FUSE_BODLEVEL0 (unsigned char)~_BV(0) 779 #define FUSE_BODLEVEL1 (unsigned char)~_BV(1) 780 #define FUSE_BODLEVEL2 (unsigned char)~_BV(2) 781 #define EFUSE_DEFAULT (0xFF) 782 783 784 785 /* Lock Bits */ 786 #define __LOCK_BITS_EXIST 787 #define __BOOT_LOCK_BITS_0_EXIST 788 #define __BOOT_LOCK_BITS_1_EXIST 789 790 791 /* Signature */ 792 #define SIGNATURE_0 0x1E 793 #define SIGNATURE_1 0x95 794 #define SIGNATURE_2 0x0F 795 796 797 #endif /* #ifdef _AVR_ATA6614Q_H_INCLUDED */ 798 799