1 /***************************************************************************** 2 * 3 * Copyright (C) 2014 Atmel Corporation 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * * Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 12 * * Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in 14 * the documentation and/or other materials provided with the 15 * distribution. 16 * 17 * * Neither the name of the copyright holders nor the names of 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 ****************************************************************************/ 33 34 35 /* $Id: iotn828.h 2460 2014-12-03 05:39:25Z pitchumani $ */ 36 37 #ifndef _AVR_ATTINY828_H_INCLUDED 38 #define _AVR_ATTINY828_H_INCLUDED 39 40 41 #ifndef _AVR_IO_H_ 42 # error "Include <avr/io.h> instead of this file." 43 #endif 44 45 #ifndef _AVR_IOXXX_H_ 46 # define _AVR_IOXXX_H_ "iotn828.h" 47 #else 48 # error "Attempt to include more than one <avr/ioXXX.h> file." 49 #endif 50 51 /* Registers and associated bit numbers */ 52 53 #define PINA _SFR_IO8(0x00) 54 #define PINA7 7 55 #define PINA6 6 56 #define PINA5 5 57 #define PINA4 4 58 #define PINA3 3 59 #define PINA2 2 60 #define PINA1 1 61 #define PINA0 0 62 63 #define DDRA _SFR_IO8(0x01) 64 #define DDRA7 7 65 #define DDRA6 6 66 #define DDRA5 5 67 #define DDRA4 4 68 #define DDRA3 3 69 #define DDRA2 2 70 #define DDRA1 1 71 #define DDRA0 0 72 73 #define PORTA _SFR_IO8(0x02) 74 #define PORTA7 7 75 #define PORTA6 6 76 #define PORTA5 5 77 #define PORTA4 4 78 #define PORTA3 3 79 #define PORTA2 2 80 #define PORTA1 1 81 #define PORTA0 0 82 83 #define PUEA _SFR_IO8(0x03) 84 85 #define PINB _SFR_IO8(0x04) 86 #define PINB7 7 87 #define PINB6 6 88 #define PINB5 5 89 #define PINB4 4 90 #define PINB3 3 91 #define PINB2 2 92 #define PINB1 1 93 #define PINB0 0 94 95 #define DDRB _SFR_IO8(0x05) 96 #define DDRB7 7 97 #define DDRB6 6 98 #define DDRB5 5 99 #define DDRB4 4 100 #define DDRB3 3 101 #define DDRB2 2 102 #define DDRB1 1 103 #define DDRB0 0 104 105 #define PORTB _SFR_IO8(0x06) 106 #define PORTB7 7 107 #define PORTB6 6 108 #define PORTB5 5 109 #define PORTB4 4 110 #define PORTB3 3 111 #define PORTB2 2 112 #define PORTB1 1 113 #define PORTB0 0 114 115 #define PUEB _SFR_IO8(0x07) 116 117 #define PINC _SFR_IO8(0x08) 118 #define PINC7 7 119 #define PINC6 6 120 #define PINC5 5 121 #define PINC4 4 122 #define PINC3 3 123 #define PINC2 2 124 #define PINC1 1 125 #define PINC0 0 126 127 #define DDRC _SFR_IO8(0x09) 128 #define DDRC7 7 129 #define DDRC6 6 130 #define DDRC5 5 131 #define DDRC4 4 132 #define DDRC3 3 133 #define DDRC2 2 134 #define DDRC1 1 135 #define DDRC0 0 136 137 #define PORTC _SFR_IO8(0x0A) 138 #define PORTC7 7 139 #define PORTC6 6 140 #define PORTC5 5 141 #define PORTC4 4 142 #define PORTC3 3 143 #define PORTC2 2 144 #define PORTC1 1 145 #define PORTC0 0 146 147 #define PUEC _SFR_IO8(0x0B) 148 149 #define PIND _SFR_IO8(0x0C) 150 #define PIND3 3 151 #define PIND2 2 152 #define PIND1 1 153 #define PIND0 0 154 155 #define DDRD _SFR_IO8(0x0D) 156 #define DDRD3 3 157 #define DDRD2 2 158 #define DDRD1 1 159 #define DDRD0 0 160 161 #define PORTD _SFR_IO8(0x0E) 162 #define PORTD3 3 163 #define PORTD2 2 164 #define PORTD1 1 165 #define PORTD0 0 166 167 #define PUED _SFR_IO8(0x0F) 168 169 /* Reserved [0x10..0x13] */ 170 171 #define PHDE _SFR_IO8(0x14) 172 #define PHDEC 2 173 174 #define TIFR0 _SFR_IO8(0x15) 175 #define TOV0 0 176 #define OCF0A 1 177 #define OCF0B 2 178 179 #define TIFR1 _SFR_IO8(0x16) 180 #define TOV1 0 181 #define OCF1A 1 182 #define OCF1B 2 183 #define ICF1 5 184 185 /* Reserved [0x17..0x1A] */ 186 187 #define PCIFR _SFR_IO8(0x1B) 188 #define PCIF0 0 189 #define PCIF1 1 190 #define PCIF2 2 191 #define PCIF3 3 192 193 #define EIFR _SFR_IO8(0x1C) 194 #define INTF0 0 195 #define INTF1 1 196 197 #define EIMSK _SFR_IO8(0x1D) 198 #define INT0 0 199 #define INT1 1 200 201 #define GPIOR0 _SFR_IO8(0x1E) 202 203 #define EECR _SFR_IO8(0x1F) 204 #define EERE 0 205 #define EEPE 1 206 #define EEMPE 2 207 #define EERIE 3 208 #define EEPM0 4 209 #define EEPM1 5 210 211 #define EEDR _SFR_IO8(0x20) 212 213 #define EEAR _SFR_IO8(0x21) 214 215 /* Reserved [0x22] */ 216 217 #define GTCCR _SFR_IO8(0x23) 218 #define PSRSYNC 0 219 #define TSM 7 220 221 #define TCCR0A _SFR_IO8(0x24) 222 #define WGM00 0 223 #define WGM01 1 224 #define COM0B0 4 225 #define COM0B1 5 226 #define COM0A0 6 227 #define COM0A1 7 228 229 #define TCCR0B _SFR_IO8(0x25) 230 #define CS00 0 231 #define CS01 1 232 #define CS02 2 233 #define WGM02 3 234 #define FOC0B 6 235 #define FOC0A 7 236 237 #define TCNT0 _SFR_IO8(0x26) 238 239 #define OCR0A _SFR_IO8(0x27) 240 241 #define OCR0B _SFR_IO8(0x28) 242 243 /* Reserved [0x29] */ 244 245 #define GPIOR1 _SFR_IO8(0x2A) 246 247 #define GPIOR2 _SFR_IO8(0x2B) 248 249 #define SPCR _SFR_IO8(0x2C) 250 #define SPR0 0 251 #define SPR1 1 252 #define CPHA 2 253 #define CPOL 3 254 #define MSTR 4 255 #define DORD 5 256 #define SPE 6 257 #define SPIE 7 258 259 #define SPSR _SFR_IO8(0x2D) 260 #define SPI2X 0 261 #define WCOL 6 262 #define SPIF 7 263 264 #define SPDR _SFR_IO8(0x2E) 265 266 #define ACSRB _SFR_IO8(0x2F) 267 #define ACPMUX0 0 268 #define ACPMUX1 1 269 #define ACNMUX0 2 270 #define ACNMUX1 3 271 #define HLEV 6 272 #define HSEL 7 273 274 #define ACSRA _SFR_IO8(0x30) 275 #define ACIS0 0 276 #define ACIS1 1 277 #define ACIC 2 278 #define ACIE 3 279 #define ACI 4 280 #define ACO 5 281 #define ACPMUX2 6 282 #define ACD 7 283 284 /* Reserved [0x31..0x32] */ 285 286 #define SMCR _SFR_IO8(0x33) 287 #define SE 0 288 #define SM0 1 289 #define SM1 2 290 291 #define MCUSR _SFR_IO8(0x34) 292 #define PORF 0 293 #define EXTRF 1 294 #define BORF 2 295 #define WDRF 3 296 297 #define MCUCR _SFR_IO8(0x35) 298 #define IVSEL 1 299 300 #define CCP _SFR_IO8(0x36) 301 302 #define SPMCSR _SFR_IO8(0x37) 303 #define SPMEN 0 304 #define PGERS 1 305 #define PGWRT 2 306 #define RWFLB 3 307 #define RWWSRE 4 308 #define RSIG 5 309 #define RWWSB 6 310 #define SPMIE 7 311 312 /* Reserved [0x38..0x3C] */ 313 314 /* SP [0x3D..0x3E] */ 315 316 /* SREG [0x3F] */ 317 318 #define WDTCSR _SFR_MEM8(0x60) 319 #define WDE 3 320 #define WDP0 0 321 #define WDP1 1 322 #define WDP2 2 323 #define WDP3 5 324 #define WDIE 6 325 #define WDIF 7 326 327 #define CLKPR _SFR_MEM8(0x61) 328 #define CLKPS0 0 329 #define CLKPS1 1 330 #define CLKPS2 2 331 #define CLKPS3 3 332 333 /* Reserved [0x62..0x63] */ 334 335 #define PRR _SFR_MEM8(0x64) 336 #define PRADC 0 337 #define PRUSART0 1 338 #define PRSPI 2 339 #define PRTIM1 3 340 #define PRTIM0 5 341 #define PRTWI 7 342 343 #define __AVR_HAVE_PRR ((1<<PRADC)|(1<<PRUSART0)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRTIM0)|(1<<PRTWI)) 344 #define __AVR_HAVE_PRR_PRADC 345 #define __AVR_HAVE_PRR_PRUSART0 346 #define __AVR_HAVE_PRR_PRSPI 347 #define __AVR_HAVE_PRR_PRTIM1 348 #define __AVR_HAVE_PRR_PRTIM0 349 #define __AVR_HAVE_PRR_PRTWI 350 351 /* Reserved [0x65] */ 352 353 #define OSCCAL0 _SFR_MEM8(0x66) 354 355 #define OSCCAL1 _SFR_MEM8(0x67) 356 357 #define PCICR _SFR_MEM8(0x68) 358 #define PCIE0 0 359 #define PCIE1 1 360 #define PCIE2 2 361 #define PCIE3 3 362 363 #define EICRA _SFR_MEM8(0x69) 364 #define ISC00 0 365 #define ISC01 1 366 #define ISC10 2 367 #define ISC11 3 368 369 /* Reserved [0x6A] */ 370 371 #define PCMSK0 _SFR_MEM8(0x6B) 372 #define PCINT0 0 373 #define PCINT1 1 374 #define PCINT2 2 375 #define PCINT3 3 376 #define PCINT4 4 377 #define PCINT5 5 378 #define PCINT6 6 379 #define PCINT7 7 380 381 #define PCMSK1 _SFR_MEM8(0x6C) 382 #define PCINT8 0 383 #define PCINT9 1 384 #define PCINT10 2 385 #define PCINT11 3 386 #define PCINT12 4 387 #define PCINT13 5 388 #define PCINT14 6 389 #define PCINT15 7 390 391 #define PCMSK2 _SFR_MEM8(0x6D) 392 #define PCINT16 0 393 #define PCINT17 1 394 #define PCINT18 2 395 #define PCINT19 3 396 #define PCINT20 4 397 #define PCINT21 5 398 #define PCINT22 6 399 #define PCINT23 7 400 401 #define TIMSK0 _SFR_MEM8(0x6E) 402 #define TOIE0 0 403 #define OCIE0A 1 404 #define OCIE0B 2 405 406 #define TIMSK1 _SFR_MEM8(0x6F) 407 #define TOIE1 0 408 #define OCIE1A 1 409 #define OCIE1B 2 410 #define ICIE1 5 411 412 /* Reserved [0x70..0x72] */ 413 414 #define PCMSK3 _SFR_MEM8(0x73) 415 #define PCINT24 0 416 #define PCINT25 1 417 #define PCINT26 2 418 #define PCINT27 3 419 420 /* Reserved [0x74..0x77] */ 421 422 /* Combine ADCL and ADCH */ 423 #ifndef __ASSEMBLER__ 424 #define ADC _SFR_MEM16(0x78) 425 #endif 426 #define ADCW _SFR_MEM16(0x78) 427 428 #define ADCL _SFR_MEM8(0x78) 429 #define ADCH _SFR_MEM8(0x79) 430 431 #define ADCSRA _SFR_MEM8(0x7A) 432 #define ADPS0 0 433 #define ADPS1 1 434 #define ADPS2 2 435 #define ADIE 3 436 #define ADIF 4 437 #define ADATE 5 438 #define ADSC 6 439 #define ADEN 7 440 441 #define ADCSRB _SFR_MEM8(0x7B) 442 #define ADTS0 0 443 #define ADTS1 1 444 #define ADTS2 2 445 #define ADLAR 3 446 447 #define ADMUXA _SFR_MEM8(0x7C) 448 #define MUX0 0 449 #define MUX1 1 450 #define MUX2 2 451 #define MUX3 3 452 #define MUX4 4 453 454 #define ADMUXB _SFR_MEM8(0x7D) 455 #define MUX5 0 456 #define REFS 5 457 458 #define DIDR0 _SFR_MEM8(0x7E) 459 #define ADC0D 0 460 #define ADC1D 1 461 #define ADC2D 2 462 #define ADC3D 3 463 #define ADC4D 4 464 #define ADC5D 5 465 #define ADC6D 6 466 #define ADC7D 7 467 468 #define DIDR1 _SFR_MEM8(0x7F) 469 #define ADC8D 0 470 #define ADC9D 1 471 #define ADC10D 2 472 #define ADC11D 3 473 #define ADC12D 4 474 #define ADC13D 5 475 #define ADC14D 6 476 #define ADC15D 7 477 478 #define TCCR1A _SFR_MEM8(0x80) 479 #define WGM10 0 480 #define WGM11 1 481 #define COM1B0 4 482 #define COM1B1 5 483 #define COM1A0 6 484 #define COM1A1 7 485 486 #define TCCR1B _SFR_MEM8(0x81) 487 #define CS10 0 488 #define CS11 1 489 #define CS12 2 490 #define WGM12 3 491 #define WGM13 4 492 #define ICES1 6 493 #define ICNC1 7 494 495 #define TCCR1C _SFR_MEM8(0x82) 496 #define FOC1B 6 497 #define FOC1A 7 498 499 /* Reserved [0x83] */ 500 501 /* Combine TCNT1L and TCNT1H */ 502 #define TCNT1 _SFR_MEM16(0x84) 503 504 #define TCNT1L _SFR_MEM8(0x84) 505 #define TCNT1H _SFR_MEM8(0x85) 506 507 /* Combine ICR1L and ICR1H */ 508 #define ICR1 _SFR_MEM16(0x86) 509 510 #define ICR1L _SFR_MEM8(0x86) 511 #define ICR1H _SFR_MEM8(0x87) 512 513 /* Combine OCR1AL and OCR1AH */ 514 #define OCR1A _SFR_MEM16(0x88) 515 516 #define OCR1AL _SFR_MEM8(0x88) 517 #define OCR1AH _SFR_MEM8(0x89) 518 519 /* Combine OCR1BL and OCR1BH */ 520 #define OCR1B _SFR_MEM16(0x8A) 521 522 #define OCR1BL _SFR_MEM8(0x8A) 523 #define OCR1BH _SFR_MEM8(0x8B) 524 525 /* Reserved [0x8C..0xB7] */ 526 527 #define TWSCRA _SFR_MEM8(0xB8) 528 #define TWSME 0 529 #define TWPME 1 530 #define TWSIE 2 531 #define TWEN 3 532 #define TWASIE 4 533 #define TWDIE 5 534 #define TWSHE 7 535 536 #define TWSCRB _SFR_MEM8(0xB9) 537 #define TWCMD0 0 538 #define TWCMD1 1 539 #define TWAA 2 540 #define TWHNM 3 541 542 #define TWSSRA _SFR_MEM8(0xBA) 543 #define TWAS 0 544 #define TWDIR 1 545 #define TWBE 2 546 #define TWC 3 547 #define TWRA 4 548 #define TWCH 5 549 #define TWASIF 6 550 #define TWDIF 7 551 552 #define TWSAM _SFR_MEM8(0xBB) 553 #define TWAE 0 554 #define TWSAM1 1 555 #define TWSAM2 2 556 #define TWSAM3 3 557 #define TWSAM4 4 558 #define TWSAM5 5 559 #define TWSAM6 6 560 #define TWSAM7 7 561 562 #define TWSA _SFR_MEM8(0xBC) 563 564 #define TWSD _SFR_MEM8(0xBD) 565 #define TWSD0 0 566 #define TWSD1 1 567 #define TWSD2 2 568 #define TWSD3 3 569 #define TWSD4 4 570 #define TWSD5 5 571 #define TWSD6 6 572 #define TWSD7 7 573 574 /* Reserved [0xBE..0xBF] */ 575 576 #define UCSRA _SFR_MEM8(0xC0) 577 #define MPCM 0 578 #define U2X 1 579 #define UPE 2 580 #define DOR 3 581 #define FE 4 582 #define UDRE 5 583 #define TXC 6 584 #define RXC 7 585 586 #define UCSRB _SFR_MEM8(0xC1) 587 #define TXB8 0 588 #define RXB8 1 589 #define UCSZ2 2 590 #define TXEN 3 591 #define RXEN 4 592 #define UDRIE 5 593 #define TXCIE 6 594 #define RXCIE 7 595 596 #define UCSRC _SFR_MEM8(0xC2) 597 #define UCPOL 0 598 #define UCSZ0 1 599 #define UCSZ1 2 600 #define USBS 3 601 #define UPM0 4 602 #define UPM1 5 603 #define UMSEL0 6 604 #define UMSEL1 7 605 606 #define UCSRD _SFR_MEM8(0xC3) 607 #define SFDE 5 608 #define RXS 6 609 #define RXSIE 7 610 611 /* Combine UBRRL and UBRRH */ 612 #define UBRR _SFR_MEM16(0xC4) 613 614 #define UBRRL _SFR_MEM8(0xC4) 615 #define UBRRH _SFR_MEM8(0xC5) 616 617 #define UDR _SFR_MEM8(0xC6) 618 619 /* Reserved [0xC7..0xDD] */ 620 621 #define DIDR2 _SFR_MEM8(0xDE) 622 #define ADC16D 0 623 #define ADC17D 1 624 #define ADC18D 2 625 #define ADC19D 3 626 #define ADC20D 4 627 #define ADC21D 5 628 #define ADC22D 6 629 #define ADC23D 7 630 631 #define DIDR3 _SFR_MEM8(0xDF) 632 #define ADC24D 0 633 #define ADC25D 1 634 #define ADC26D 2 635 #define ADC27D 3 636 637 /* Reserved [0xE0..0xE1] */ 638 639 #define TOCPMCOE _SFR_MEM8(0xE2) 640 #define TOCC0OE 0 641 #define TOCC1OE 1 642 #define TOCC2OE 2 643 #define TOCC3OE 3 644 #define TOCC4OE 4 645 #define TOCC5OE 5 646 #define TOCC6OE 6 647 #define TOCC7OE 7 648 649 /* Reserved [0xE3..0xE7] */ 650 651 #define TOCPMSA0 _SFR_MEM8(0xE8) 652 #define TOCC0S0 0 653 #define TOCC0S1 1 654 #define TOCC1S0 2 655 #define TOCC1S1 3 656 #define TOCC2S0 4 657 #define TOCC2S1 5 658 #define TOCC3S0 6 659 #define TOCC3S1 7 660 661 #define TOCPMSA1 _SFR_MEM8(0xE9) 662 #define TOCC4S0 0 663 #define TOCC4S1 1 664 #define TOCC5S0 2 665 #define TOCC5S1 3 666 #define TOCC6S0 4 667 #define TOCC6S1 5 668 #define TOCC7S0 6 669 #define TOCC7S1 7 670 671 /* Reserved [0xEA..0xEF] */ 672 673 #define OSCTCAL0A _SFR_MEM8(0xF0) 674 675 #define OSCTCAL0B _SFR_MEM8(0xF1) 676 677 678 679 /* Interrupt vectors */ 680 /* Vector 0 is the reset vector */ 681 /* External Interrupt Request 0 */ 682 #define INT0_vect _VECTOR(1) 683 #define INT0_vect_num 1 684 685 /* External Interrupt Request 1 */ 686 #define INT1_vect _VECTOR(2) 687 #define INT1_vect_num 2 688 689 /* Pin Change Interrupt Request 0 */ 690 #define PCINT0_vect _VECTOR(3) 691 #define PCINT0_vect_num 3 692 693 /* Pin Change Interrupt Request 1 */ 694 #define PCINT1_vect _VECTOR(4) 695 #define PCINT1_vect_num 4 696 697 /* Pin Change Interrupt Request 2 */ 698 #define PCINT2_vect _VECTOR(5) 699 #define PCINT2_vect_num 5 700 701 /* Pin Change Interrupt Request 3 */ 702 #define PCINT3_vect _VECTOR(6) 703 #define PCINT3_vect_num 6 704 705 /* Watchdog Time-out Interrupt */ 706 #define WDT_vect _VECTOR(7) 707 #define WDT_vect_num 7 708 709 /* Timer/Counter1 Capture Event */ 710 #define TIMER1_CAPT_vect _VECTOR(8) 711 #define TIMER1_CAPT_vect_num 8 712 713 /* Timer/Counter1 Compare Match A */ 714 #define TIMER1_COMPA_vect _VECTOR(9) 715 #define TIMER1_COMPA_vect_num 9 716 717 /* Timer/Counter1 Compare Match B */ 718 #define TIMER1_COMPB_vect _VECTOR(10) 719 #define TIMER1_COMPB_vect_num 10 720 721 /* Timer/Counter1 Overflow */ 722 #define TIMER1_OVF_vect _VECTOR(11) 723 #define TIMER1_OVF_vect_num 11 724 725 /* Timer/Counter0 Compare Match A */ 726 #define TIMER0_COMPA_vect _VECTOR(12) 727 #define TIMER0_COMPA_vect_num 12 728 729 /* Timer/Counter0 Compare Match B */ 730 #define TIMER0_COMPB_vect _VECTOR(13) 731 #define TIMER0_COMPB_vect_num 13 732 733 /* Timer/Counter0 Overflow */ 734 #define TIMER0_OVF_vect _VECTOR(14) 735 #define TIMER0_OVF_vect_num 14 736 737 /* SPI Serial Transfer Complete */ 738 #define SPI_STC_vect _VECTOR(15) 739 #define SPI_STC_vect_num 15 740 741 /* USART, Start */ 742 #define USART_START_vect _VECTOR(16) 743 #define USART_START_vect_num 16 744 745 /* USART Rx Complete */ 746 #define USART_RX_vect _VECTOR(17) 747 #define USART_RX_vect_num 17 748 749 /* USART, Data Register Empty */ 750 #define USART_UDRE_vect _VECTOR(18) 751 #define USART_UDRE_vect_num 18 752 753 /* USART Tx Complete */ 754 #define USART_TX_vect _VECTOR(19) 755 #define USART_TX_vect_num 19 756 757 /* ADC Conversion Complete */ 758 #define ADC_vect _VECTOR(20) 759 #define ADC_vect_num 20 760 761 /* EEPROM Ready */ 762 #define EE_READY_vect _VECTOR(21) 763 #define EE_READY_vect_num 21 764 765 /* Analog Comparator */ 766 #define ANALOG_COMP_vect _VECTOR(22) 767 #define ANALOG_COMP_vect_num 22 768 769 /* Two-wire Serial Interface */ 770 #define TWI_SLAVE_vect _VECTOR(23) 771 #define TWI_SLAVE_vect_num 23 772 773 /* Store Program Memory Read */ 774 #define SPM_Ready_vect _VECTOR(24) 775 #define SPM_Ready_vect_num 24 776 777 /* Touch Sensing */ 778 #define QTRIP_vect _VECTOR(25) 779 #define QTRIP_vect_num 25 780 781 #define _VECTORS_SIZE 52 782 783 784 /* Constants */ 785 786 #define SPM_PAGESIZE 64 787 #define FLASHSTART 0x0000 788 #define FLASHEND 0x1FFF 789 #define RAMSTART 0x0100 790 #define RAMSIZE 512 791 #define RAMEND 0x02FF 792 #define E2START 0 793 #define E2SIZE 256 794 #define E2PAGESIZE 4 795 #define E2END 0x00FF 796 #define XRAMEND RAMEND 797 798 799 /* Fuses */ 800 801 #define FUSE_MEMORY_SIZE 3 802 803 /* Low Fuse Byte */ 804 #define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0) 805 #define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1) 806 #define FUSE_CKOUT (unsigned char)~_BV(6) 807 #define FUSE_CKDIV8 (unsigned char)~_BV(7) 808 809 /* High Fuse Byte */ 810 #define FUSE_BODLEVEL0 (unsigned char)~_BV(0) 811 #define FUSE_BODLEVEL1 (unsigned char)~_BV(1) 812 #define FUSE_BODLEVEL2 (unsigned char)~_BV(2) 813 #define FUSE_EESAVE (unsigned char)~_BV(3) 814 #define FUSE_WDTON (unsigned char)~_BV(4) 815 #define FUSE_SPIEN (unsigned char)~_BV(5) 816 #define FUSE_DWEN (unsigned char)~_BV(6) 817 #define FUSE_RSTDISBL (unsigned char)~_BV(7) 818 819 /* Extended Fuse Byte */ 820 #define FUSE_BOOTRST (unsigned char)~_BV(0) 821 #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) 822 #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) 823 #define FUSE_BODACT0 (unsigned char)~_BV(4) 824 #define FUSE_BODACT1 (unsigned char)~_BV(5) 825 #define FUSE_BODPD0 (unsigned char)~_BV(6) 826 #define FUSE_BODPD1 (unsigned char)~_BV(7) 827 828 829 /* Lock Bits */ 830 #define __LOCK_BITS_EXIST 831 #define __BOOT_LOCK_BITS_0_EXIST 832 #define __BOOT_LOCK_BITS_1_EXIST 833 834 835 /* Signature */ 836 #define SIGNATURE_0 0x1E 837 #define SIGNATURE_1 0x93 838 #define SIGNATURE_2 0x14 839 840 841 842 #define SLEEP_MODE_IDLE (0x00<<1) 843 #define SLEEP_MODE_ADC (0x01<<1) 844 #define SLEEP_MODE_PWR_DOWN (0x02<<1) 845 846 #endif /* #ifdef _AVR_ATTINY828_H_INCLUDED */ 847 848