1 /* Copyright (c) 2006, Anatoly Sokolov 2 All rights reserved. 3 4 Redistribution and use in source and binary forms, with or without 5 modification, are permitted provided that the following conditions are met: 6 7 * Redistributions of source code must retain the above copyright 8 notice, this list of conditions and the following disclaimer. 9 10 * Redistributions in binary form must reproduce the above copyright 11 notice, this list of conditions and the following disclaimer in 12 the documentation and/or other materials provided with the 13 distribution. 14 15 * Neither the name of the copyright holders nor the names of 16 contributors may be used to endorse or promote products derived 17 from this software without specific prior written permission. 18 19 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 POSSIBILITY OF SUCH DAMAGE. */ 30 31 /* $Id: iousbxx6_7.h 2483 2015-08-06 09:16:30Z pitchumani $ */ 32 33 /* iousbxx6_7.h - definitions for AT90USB646, AT90USB647, AT90USB1286 34 and AT90USB1287 */ 35 36 #ifndef _AVR_IOUSBXX6_7_H_ 37 #define _AVR_IOUSBXX6_7_H_ 1 38 39 /* This file should only be included from <avr/io.h>, never directly. */ 40 41 #ifndef _AVR_IO_H_ 42 # error "Include <avr/io.h> instead of this file." 43 #endif 44 45 #ifndef _AVR_IOXXX_H_ 46 # define _AVR_IOXXX_H_ "iousbxx6_7.h" 47 #else 48 # error "Attempt to include more than one <avr/ioXXX.h> file." 49 #endif 50 51 #if defined(__AVR_AT90USB646__) || defined(__AVR_AT90USB1286__) 52 # define __AT90USBxx6__ 1 53 #elif defined(__AVR_AT90USB647__) || defined(__AVR_AT90USB1287__) 54 # define __AT90USBxx7__ 1 55 #endif 56 57 /* Registers and associated bit numbers */ 58 59 #define PINA _SFR_IO8(0X00) 60 #define PINA7 7 61 #define PINA6 6 62 #define PINA5 5 63 #define PINA4 4 64 #define PINA3 3 65 #define PINA2 2 66 #define PINA1 1 67 #define PINA0 0 68 69 #define DDRA _SFR_IO8(0X01) 70 #define DDA7 7 71 #define DDA6 6 72 #define DDA5 5 73 #define DDA4 4 74 #define DDA3 3 75 #define DDA2 2 76 #define DDA1 1 77 #define DDA0 0 78 79 #define PORTA _SFR_IO8(0X02) 80 #define PA7 7 81 #define PA6 6 82 #define PA5 5 83 #define PA4 4 84 #define PA3 3 85 #define PA2 2 86 #define PA1 1 87 #define PA0 0 88 89 #define PINB _SFR_IO8(0X03) 90 #define PINB7 7 91 #define PINB6 6 92 #define PINB5 5 93 #define PINB4 4 94 #define PINB3 3 95 #define PINB2 2 96 #define PINB1 1 97 #define PINB0 0 98 99 #define DDRB _SFR_IO8(0x04) 100 #define DDB7 7 101 #define DDB6 6 102 #define DDB5 5 103 #define DDB4 4 104 #define DDB3 3 105 #define DDB2 2 106 #define DDB1 1 107 #define DDB0 0 108 109 #define PORTB _SFR_IO8(0x05) 110 #define PB7 7 111 #define PB6 6 112 #define PB5 5 113 #define PB4 4 114 #define PB3 3 115 #define PB2 2 116 #define PB1 1 117 #define PB0 0 118 119 #define PINC _SFR_IO8(0x06) 120 #define PINC7 7 121 #define PINC6 6 122 #define PINC5 5 123 #define PINC4 4 124 #define PINC3 3 125 #define PINC2 2 126 #define PINC1 1 127 #define PINC0 0 128 129 #define DDRC _SFR_IO8(0x07) 130 #define DDC7 7 131 #define DDC6 6 132 #define DDC5 5 133 #define DDC4 4 134 #define DDC3 3 135 #define DDC2 2 136 #define DDC1 1 137 #define DDC0 0 138 139 #define PORTC _SFR_IO8(0x08) 140 #define PC7 7 141 #define PC6 6 142 #define PC5 5 143 #define PC4 4 144 #define PC3 3 145 #define PC2 2 146 #define PC1 1 147 #define PC0 0 148 149 #define PIND _SFR_IO8(0x09) 150 #define PIND7 7 151 #define PIND6 6 152 #define PIND5 5 153 #define PIND4 4 154 #define PIND3 3 155 #define PIND2 2 156 #define PIND1 1 157 #define PIND0 0 158 159 #define DDRD _SFR_IO8(0x0A) 160 #define DDD7 7 161 #define DDD6 6 162 #define DDD5 5 163 #define DDD4 4 164 #define DDD3 3 165 #define DDD2 2 166 #define DDD1 1 167 #define DDD0 0 168 169 #define PORTD _SFR_IO8(0x0B) 170 #define PD7 7 171 #define PD6 6 172 #define PD5 5 173 #define PD4 4 174 #define PD3 3 175 #define PD2 2 176 #define PD1 1 177 #define PD0 0 178 179 #define PINE _SFR_IO8(0x0C) 180 #define PINE7 7 181 #define PINE6 6 182 #define PINE5 5 183 #define PINE4 4 184 #define PINE3 3 185 #define PINE2 2 186 #define PINE1 1 187 #define PINE0 0 188 189 #define DDRE _SFR_IO8(0x0D) 190 #define DDE7 7 191 #define DDE6 6 192 #define DDE5 5 193 #define DDE4 4 194 #define DDE3 3 195 #define DDE2 2 196 #define DDE1 1 197 #define DDE0 0 198 199 #define PORTE _SFR_IO8(0x0E) 200 #define PE7 7 201 #define PE6 6 202 #define PE5 5 203 #define PE4 4 204 #define PE3 3 205 #define PE2 2 206 #define PE1 1 207 #define PE0 0 208 209 #define PINF _SFR_IO8(0x0F) 210 #define PINF7 7 211 #define PINF6 6 212 #define PINF5 5 213 #define PINF4 4 214 #define PINF3 3 215 #define PINF2 2 216 #define PINF1 1 217 #define PINF0 0 218 219 #define DDRF _SFR_IO8(0x10) 220 #define DDF7 7 221 #define DDF6 6 222 #define DDF5 5 223 #define DDF4 4 224 #define DDF3 3 225 #define DDF2 2 226 #define DDF1 1 227 #define DDF0 0 228 229 #define PORTF _SFR_IO8(0x11) 230 #define PF7 7 231 #define PF6 6 232 #define PF5 5 233 #define PF4 4 234 #define PF3 3 235 #define PF2 2 236 #define PF1 1 237 #define PF0 0 238 239 /* Reserved [0x12..0x14] */ 240 241 #define TIFR0 _SFR_IO8(0x15) 242 #define OCF0B 2 243 #define OCF0A 1 244 #define TOV0 0 245 246 #define TIFR1 _SFR_IO8(0x16) 247 #define ICF1 5 248 #define OCF1C 3 249 #define OCF1B 2 250 #define OCF1A 1 251 #define TOV1 0 252 253 #define TIFR2 _SFR_IO8(0x17) 254 #define OCF2B 2 255 #define OCF2A 1 256 #define TOV2 0 257 258 #define TIFR3 _SFR_IO8(0x18) 259 #define ICF3 5 260 #define OCF3C 3 261 #define OCF3B 2 262 #define OCF3A 1 263 #define TOV3 0 264 265 /* Reserved [0x19..0x1A] */ 266 267 #define PCIFR _SFR_IO8(0x1B) 268 #define PCIF0 0 269 270 #define EIFR _SFR_IO8(0x1C) 271 #define INTF7 7 272 #define INTF6 6 273 #define INTF5 5 274 #define INTF4 4 275 #define INTF3 3 276 #define INTF2 2 277 #define INTF1 1 278 #define INTF0 0 279 280 #define EIMSK _SFR_IO8(0x1D) 281 #define INT7 7 282 #define INT6 6 283 #define INT5 5 284 #define INT4 4 285 #define INT3 3 286 #define INT2 2 287 #define INT1 1 288 #define INT0 0 289 290 #define GPIOR0 _SFR_IO8(0x1E) 291 292 #define EECR _SFR_IO8(0x1F) 293 #define EEPM1 5 294 #define EEPM0 4 295 #define EERIE 3 296 #define EEMPE 2 297 #define EEPE 1 298 #define EERE 0 299 300 #define EEDR _SFR_IO8(0x20) 301 302 #define EEAR _SFR_IO16(0x21) 303 #define EEARL _SFR_IO8(0x21) 304 #define EEARH _SFR_IO8(0x22) 305 306 /* 6-char sequence denoting where to find the EEPROM registers in memory space. 307 Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM 308 subroutines. 309 First two letters: EECR address. 310 Second two letters: EEDR address. 311 Last two letters: EEAR address. */ 312 #define __EEPROM_REG_LOCATIONS__ 1F2021 313 314 #define GTCCR _SFR_IO8(0x23) 315 #define TSM 7 316 #define PSRASY 1 317 #define PSRSYNC 0 318 319 #define TCCR0A _SFR_IO8(0x24) 320 #define COM0A1 7 321 #define COM0A0 6 322 #define COM0B1 5 323 #define COM0B0 4 324 #define WGM01 1 325 #define WGM00 0 326 327 #define TCCR0B _SFR_IO8(0x25) 328 #define FOC0A 7 329 #define FOC0B 6 330 #define WGM02 3 331 #define CS02 2 332 #define CS01 1 333 #define CS00 0 334 335 #define TCNT0 _SFR_IO8(0X26) 336 337 #define OCR0A _SFR_IO8(0x27) 338 339 #define OCR0B _SFR_IO8(0X28) 340 341 #define PLLCSR _SFR_IO8(0x29) 342 #define PLLP2 4 343 #define PLLP1 3 344 #define PLLP0 2 345 #define PLLE 1 346 #define PLOCK 0 347 348 #define GPIOR1 _SFR_IO8(0x2A) 349 350 #define GPIOR2 _SFR_IO8(0x2B) 351 352 #define SPCR _SFR_IO8(0x2C) 353 #define SPIE 7 354 #define SPE 6 355 #define DORD 5 356 #define MSTR 4 357 #define CPOL 3 358 #define CPHA 2 359 #define SPR1 1 360 #define SPR0 0 361 362 #define SPSR _SFR_IO8(0x2D) 363 #define SPIF 7 364 #define WCOL 6 365 #define SPI2X 0 366 367 #define SPDR _SFR_IO8(0x2E) 368 369 /* Reserved [0x2F] */ 370 371 #define ACSR _SFR_IO8(0x30) 372 #define ACD 7 373 #define ACBG 6 374 #define ACO 5 375 #define ACI 4 376 #define ACIE 3 377 #define ACIC 2 378 #define ACIS1 1 379 #define ACIS0 0 380 381 #define MONDR _SFR_IO8(0x31) 382 #define OCDR _SFR_IO8(0x31) 383 #define IDRD 7 384 #define OCDR7 7 385 #define OCDR6 6 386 #define OCDR5 5 387 #define OCDR4 4 388 #define OCDR3 3 389 #define OCDR2 2 390 #define OCDR1 1 391 #define OCDR0 0 392 393 /* Reserved [0x32] */ 394 395 #define SMCR _SFR_IO8(0x33) 396 #define SM2 3 397 #define SM1 2 398 #define SM0 1 399 #define SE 0 400 401 #define MCUSR _SFR_IO8(0x34) 402 #define JTRF 4 403 #define WDRF 3 404 #define BORF 2 405 #define EXTRF 1 406 #define PORF 0 407 408 #define MCUCR _SFR_IO8(0x35) 409 #define JTD 7 410 #define PUD 4 411 #define IVSEL 1 412 #define IVCE 0 413 414 /* Reserved [0x36] */ 415 416 #define SPMCSR _SFR_IO8(0x37) 417 #define SPMIE 7 418 #define RWWSB 6 419 #define SIGRD 5 420 #define RWWSRE 4 421 #define BLBSET 3 422 #define PGWRT 2 423 #define PGERS 1 424 #define SPMEN 0 425 426 /* Reserved [0x38..0x3A] */ 427 428 #if defined(__AVR_AT90USB1286__) || defined(__AVR_AT90USB1287__) 429 #define RAMPZ _SFR_IO8(0x3B) 430 #endif 431 432 /* Reserved [0x3C] */ 433 434 /* SP [0x3D..0x3E] */ 435 /* SREG [0x3F] */ 436 437 #define WDTCSR _SFR_MEM8(0x60) 438 #define WDIF 7 439 #define WDIE 6 440 #define WDP3 5 441 #define WDCE 4 442 #define WDE 3 443 #define WDP2 2 444 #define WDP1 1 445 #define WDP0 0 446 447 #define CLKPR _SFR_MEM8(0x61) 448 #define CLKPCE 7 449 #define CLKPS3 3 450 #define CLKPS2 2 451 #define CLKPS1 1 452 #define CLKPS0 0 453 454 /* Reserved [0x62..0x63] */ 455 456 #define PRR0 _SFR_MEM8(0x64) 457 #define PRTWI 7 458 #define PRTIM2 6 459 #define PRTIM0 5 460 #define PRTIM1 3 461 #define PRSPI 2 462 #define PRADC 0 463 464 #define __AVR_HAVE_PRR0 ((1<<PRADC)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRTIM0)|(1<<PRTIM2)|(1<<PRTWI)) 465 #define __AVR_HAVE_PRR0_PRADC 466 #define __AVR_HAVE_PRR0_PRSPI 467 #define __AVR_HAVE_PRR0_PRTIM1 468 #define __AVR_HAVE_PRR0_PRTIM0 469 #define __AVR_HAVE_PRR0_PRTIM2 470 #define __AVR_HAVE_PRR0_PRTWI 471 472 #define PRR1 _SFR_MEM8(0x65) 473 #define PRUSB 7 474 #define PRTIM3 3 475 #define PRUSART1 0 476 477 #define __AVR_HAVE_PRR1 ((1<<PRUSART1)|(1<<PRTIM3)|(1<<PRUSB)) 478 #define __AVR_HAVE_PRR1_PRUSART1 479 #define __AVR_HAVE_PRR1_PRTIM3 480 #define __AVR_HAVE_PRR1_PRUSB 481 482 #define OSCCAL _SFR_MEM8(0x66) 483 484 /* Reserved [0x67] */ 485 486 #define PCICR _SFR_MEM8(0x68) 487 #define PCIE0 0 488 489 #define EICRA _SFR_MEM8(0x69) 490 #define ISC31 7 491 #define ISC30 6 492 #define ISC21 5 493 #define ISC20 4 494 #define ISC11 3 495 #define ISC10 2 496 #define ISC01 1 497 #define ISC00 0 498 499 #define EICRB _SFR_MEM8(0x6A) 500 #define ISC71 7 501 #define ISC70 6 502 #define ISC61 5 503 #define ISC60 4 504 #define ISC51 3 505 #define ISC50 2 506 #define ISC41 1 507 #define ISC40 0 508 509 #define PCMSK0 _SFR_MEM8(0x6B) 510 #define PCINT7 7 511 #define PCINT6 6 512 #define PCINT5 5 513 #define PCINT4 4 514 #define PCINT3 3 515 #define PCINT2 2 516 #define PCINT1 1 517 #define PCINT0 0 518 519 /* Reserved [0x6C..0x6D] */ 520 521 #define TIMSK0 _SFR_MEM8(0x6E) 522 #define OCIE0B 2 523 #define OCIE0A 1 524 #define TOIE0 0 525 526 #define TIMSK1 _SFR_MEM8(0x6F) 527 #define ICIE1 5 528 #define OCIE1C 3 529 #define OCIE1B 2 530 #define OCIE1A 1 531 #define TOIE1 0 532 533 #define TIMSK2 _SFR_MEM8(0x70) 534 #define OCIE2B 2 535 #define OCIE2A 1 536 #define TOIE2 0 537 538 #define TIMSK3 _SFR_MEM8(0x71) 539 #define ICIE3 5 540 #define OCIE3C 3 541 #define OCIE3B 2 542 #define OCIE3A 1 543 #define TOIE3 0 544 545 /* Reserved [0x72..0x73] */ 546 547 #define XMCRA _SFR_MEM8(0x74) 548 #define SRE 7 549 #define SRL2 6 550 #define SRL1 5 551 #define SRL0 4 552 #define SRW11 3 553 #define SRW10 2 554 #define SRW01 1 555 #define SRW00 0 556 557 #define XMCRB _SFR_MEM8(0x75) 558 #define XMBK 7 559 #define XMM2 2 560 #define XMM1 1 561 #define XMM0 0 562 563 /* Reserved [0x76..0x77] */ 564 565 /* RegDef: ADC Data Register */ 566 #ifndef __ASSEMBLER__ 567 #define ADC _SFR_MEM16(0x78) 568 #endif 569 #define ADCW _SFR_MEM16(0x78) 570 #define ADCL _SFR_MEM8(0x78) 571 #define ADCH _SFR_MEM8(0x79) 572 573 #define ADCSRA _SFR_MEM8(0x7A) 574 #define ADEN 7 575 #define ADSC 6 576 #define ADATE 5 577 #define ADIF 4 578 #define ADIE 3 579 #define ADPS2 2 580 #define ADPS1 1 581 #define ADPS0 0 582 583 #define ADCSRB _SFR_MEM8(0x7B) 584 #define ADHSM 7 585 #define ACME 6 586 #define ADTS2 2 587 #define ADTS1 1 588 #define ADTS0 0 589 590 #define ADMUX _SFR_MEM8(0x7C) 591 #define REFS1 7 592 #define REFS0 6 593 #define ADLAR 5 594 #define MUX4 4 595 #define MUX3 3 596 #define MUX2 2 597 #define MUX1 1 598 #define MUX0 0 599 600 /* Reserved [0x7D] */ 601 602 #define DIDR0 _SFR_MEM8(0x7E) 603 #define ADC7D 7 604 #define ADC6D 6 605 #define ADC5D 5 606 #define ADC4D 4 607 #define ADC3D 3 608 #define ADC2D 2 609 #define ADC1D 1 610 #define ADC0D 0 611 612 #define DIDR1 _SFR_MEM8(0x7F) 613 #define AIN1D 1 614 #define AIN0D 0 615 616 #define TCCR1A _SFR_MEM8(0x80) 617 #define COM1A1 7 618 #define COM1A0 6 619 #define COM1B1 5 620 #define COM1B0 4 621 #define COM1C1 3 622 #define COM1C0 2 623 #define WGM11 1 624 #define WGM10 0 625 626 #define TCCR1B _SFR_MEM8(0x81) 627 #define ICNC1 7 628 #define ICES1 6 629 #define WGM13 4 630 #define WGM12 3 631 #define CS12 2 632 #define CS11 1 633 #define CS10 0 634 635 #define TCCR1C _SFR_MEM8(0x82) 636 #define FOC1A 7 637 #define FOC1B 6 638 #define FOC1C 5 639 640 /* Reserved [0x83] */ 641 642 /* Combine TCNT1L and TCNT1H */ 643 #define TCNT1 _SFR_MEM16(0x84) 644 645 #define TCNT1L _SFR_MEM8(0x84) 646 #define TCNT1H _SFR_MEM8(0x85) 647 648 /* Combine ICR1L and ICR1H */ 649 #define ICR1 _SFR_MEM16(0x86) 650 651 #define ICR1L _SFR_MEM8(0x86) 652 #define ICR1H _SFR_MEM8(0x87) 653 654 /* Combine OCR1AL and OCR1AH */ 655 #define OCR1A _SFR_MEM16(0x88) 656 657 #define OCR1AL _SFR_MEM8(0x88) 658 #define OCR1AH _SFR_MEM8(0x89) 659 660 /* Combine OCR1BL and OCR1BH */ 661 #define OCR1B _SFR_MEM16(0x8A) 662 663 #define OCR1BL _SFR_MEM8(0x8A) 664 #define OCR1BH _SFR_MEM8(0x8B) 665 666 /* Combine OCR1CL and OCR1CH */ 667 #define OCR1C _SFR_MEM16(0x8C) 668 669 #define OCR1CL _SFR_MEM8(0x8C) 670 #define OCR1CH _SFR_MEM8(0x8D) 671 672 /* Reserved [0x8E..0x8F] */ 673 674 #define TCCR3A _SFR_MEM8(0x90) 675 #define COM3A1 7 676 #define COM3A0 6 677 #define COM3B1 5 678 #define COM3B0 4 679 #define COM3C1 3 680 #define COM3C0 2 681 #define WGM31 1 682 #define WGM30 0 683 684 #define TCCR3B _SFR_MEM8(0x91) 685 #define ICNC3 7 686 #define ICES3 6 687 #define WGM33 4 688 #define WGM32 3 689 #define CS32 2 690 #define CS31 1 691 #define CS30 0 692 693 #define TCCR3C _SFR_MEM8(0x92) 694 #define FOC3A 7 695 #define FOC3B 6 696 #define FOC3C 5 697 698 /* Reserved [0x93] */ 699 700 /* Combine TCNT3L and TCNT3H */ 701 #define TCNT3 _SFR_MEM16(0x94) 702 703 #define TCNT3L _SFR_MEM8(0x94) 704 #define TCNT3H _SFR_MEM8(0x95) 705 706 /* Combine ICR3L and ICR3H */ 707 #define ICR3 _SFR_MEM16(0x96) 708 709 #define ICR3L _SFR_MEM8(0x96) 710 #define ICR3H _SFR_MEM8(0x97) 711 712 /* Combine OCR3AL and OCR3AH */ 713 #define OCR3A _SFR_MEM16(0x98) 714 715 #define OCR3AL _SFR_MEM8(0x98) 716 #define OCR3AH _SFR_MEM8(0x99) 717 718 /* Combine OCR3BL and OCR3BH */ 719 #define OCR3B _SFR_MEM16(0x9A) 720 721 #define OCR3BL _SFR_MEM8(0x9A) 722 #define OCR3BH _SFR_MEM8(0x9B) 723 724 /* Combine OCR3CL and OCR3CH */ 725 #define OCR3C _SFR_MEM16(0x9C) 726 727 #define OCR3CL _SFR_MEM8(0x9C) 728 #define OCR3CH _SFR_MEM8(0x9D) 729 730 #if defined(__AT90USBxx7__) 731 732 #define UHCON _SFR_MEM8(0x9E) 733 #define RESUME 2 734 #define RESET 1 735 #define SOFEN 0 736 737 #define UHINT _SFR_MEM8(0x9F) 738 #define HWUPI 6 739 #define HSOFI 5 740 #define RXRSMI 4 741 #define RSMEDI 3 742 #define RSTI 2 743 #define DDISCI 1 744 #define DCONNI 0 745 746 #define UHIEN _SFR_MEM8(0xA0) 747 #define HWUPE 6 748 #define HSOFE 5 749 #define RXRSME 4 750 #define RSMEDE 3 751 #define RSTE 2 752 #define DDISCE 1 753 #define DCONNE 0 754 755 #define UHADDR _SFR_MEM8(0xA1) 756 757 /* Combine UHFNUML and UHFNUMH */ 758 #define UHFNUM _SFR_MEM16(0xA2) 759 760 #define UHFNUML _SFR_MEM8(0xA2) 761 #define UHFNUMH _SFR_MEM8(0xA3) 762 763 #define UHFLEN _SFR_MEM8(0xA4) 764 765 #define UPINRQX _SFR_MEM8(0xA5) 766 767 #define UPINTX _SFR_MEM8(0xA6) 768 #define FIFOCON 7 769 #define NAKEDI 6 770 #define RWAL 5 771 #define PERRI 4 772 #define TXSTPI 3 773 #define TXOUTI 2 774 #define RXSTALLI 1 775 #define RXINI 0 776 777 #define UPNUM _SFR_MEM8(0xA7) 778 779 #define UPRST _SFR_MEM8(0xA8) 780 #define PRST6 6 781 #define PRST5 5 782 #define PRST4 4 783 #define PRST3 3 784 #define PRST2 2 785 #define PRST1 1 786 #define PRST0 0 787 788 #define UPCONX _SFR_MEM8(0xA9) 789 #define PFREEZE 6 790 #define INMODE 5 791 /* #define AUTOSW 4 */ /* Reserved */ 792 #define RSTDT 3 793 #define PEN 0 794 795 #define UPCFG0X _SFR_MEM8(0XAA) 796 #define PTYPE1 7 797 #define PTYPE0 6 798 #define PTOKEN1 5 799 #define PTOKEN0 4 800 #define PEPNUM3 3 801 #define PEPNUM2 2 802 #define PEPNUM1 1 803 #define PEPNUM0 0 804 805 #define UPCFG1X _SFR_MEM8(0XAB) 806 #define PSIZE2 6 807 #define PSIZE1 5 808 #define PSIZE0 4 809 #define PBK1 3 810 #define PBK0 2 811 #define ALLOC 1 812 813 #define UPSTAX _SFR_MEM8(0XAC) 814 #define CFGOK 7 815 #define OVERFI 6 816 #define UNDERFI 5 817 #define DTSEQ1 3 818 #define DTSEQ0 2 819 #define NBUSYBK1 1 820 #define NBUSYBK0 0 821 822 #define UPCFG2X _SFR_MEM8(0XAD) 823 824 #define UPIENX _SFR_MEM8(0XAE) 825 #define FLERRE 7 826 #define NAKEDE 6 827 #define PERRE 4 828 #define TXSTPE 3 829 #define TXOUTE 2 830 #define RXSTALLE 1 831 #define RXINE 0 832 833 #define UPDATX _SFR_MEM8(0XAF) 834 835 #endif /* __AT90USBxx7__ */ 836 837 #define TCCR2A _SFR_MEM8(0xB0) 838 #define COM2A1 7 839 #define COM2A0 6 840 #define COM2B1 5 841 #define COM2B0 4 842 #define WGM21 1 843 #define WGM20 0 844 845 #define TCCR2B _SFR_MEM8(0xB1) 846 #define FOC2A 7 847 #define FOC2B 6 848 #define WGM22 3 849 #define CS22 2 850 #define CS21 1 851 #define CS20 0 852 853 #define TCNT2 _SFR_MEM8(0xB2) 854 855 #define OCR2A _SFR_MEM8(0xB3) 856 857 #define OCR2B _SFR_MEM8(0xB4) 858 859 /* Reserved [0xB5] */ 860 861 #define ASSR _SFR_MEM8(0xB6) 862 #define EXCLK 6 863 #define AS2 5 864 #define TCN2UB 4 865 #define OCR2AUB 3 866 #define OCR2BUB 2 867 #define TCR2AUB 1 868 #define TCR2BUB 0 869 870 /* Reserved [0xB7] */ 871 872 #define TWBR _SFR_MEM8(0xB8) 873 874 #define TWSR _SFR_MEM8(0xB9) 875 #define TWS7 7 876 #define TWS6 6 877 #define TWS5 5 878 #define TWS4 4 879 #define TWS3 3 880 #define TWPS1 1 881 #define TWPS0 0 882 883 #define TWAR _SFR_MEM8(0xBA) 884 #define TWA6 7 885 #define TWA5 6 886 #define TWA4 5 887 #define TWA3 4 888 #define TWA2 3 889 #define TWA1 2 890 #define TWA0 1 891 #define TWGCE 0 892 893 #define TWDR _SFR_MEM8(0xBB) 894 895 #define TWCR _SFR_MEM8(0xBC) 896 #define TWINT 7 897 #define TWEA 6 898 #define TWSTA 5 899 #define TWSTO 4 900 #define TWWC 3 901 #define TWEN 2 902 #define TWIE 0 903 904 #define TWAMR _SFR_MEM8(0xBD) 905 #define TWAM6 7 906 #define TWAM5 6 907 #define TWAM4 5 908 #define TWAM3 4 909 #define TWAM2 3 910 #define TWAM1 2 911 #define TWAM0 1 912 913 /* Reserved [0xBE..0xC7] */ 914 915 #define UCSR1A _SFR_MEM8(0xC8) 916 #define RXC1 7 917 #define TXC1 6 918 #define UDRE1 5 919 #define FE1 4 920 #define DOR1 3 921 #define UPE1 2 922 #define U2X1 1 923 #define MPCM1 0 924 925 #define UCSR1B _SFR_MEM8(0XC9) 926 #define RXCIE1 7 927 #define TXCIE1 6 928 #define UDRIE1 5 929 #define RXEN1 4 930 #define TXEN1 3 931 #define UCSZ12 2 932 #define RXB81 1 933 #define TXB81 0 934 935 #define UCSR1C _SFR_MEM8(0xCA) 936 #define UMSEL11 7 937 #define UMSEL10 6 938 #define UPM11 5 939 #define UPM10 4 940 #define USBS1 3 941 #define UCSZ11 2 942 #define UCSZ10 1 943 #define UCPOL1 0 944 945 /* Reserved [0xCB] */ 946 947 /* Combine UBRR1L and UBRR1H */ 948 #define UBRR1 _SFR_MEM16(0xCC) 949 950 #define UBRR1L _SFR_MEM8(0xCC) 951 #define UBRR1H _SFR_MEM8(0xCD) 952 953 #define UDR1 _SFR_MEM8(0XCE) 954 955 /* Reserved [0xCF..0xD6] */ 956 957 #define UHWCON _SFR_MEM8(0XD7) 958 #define UIMOD 7 959 #define UIDE 6 960 #define UVCONE 4 961 #define UVREGE 0 962 963 #define USBCON _SFR_MEM8(0XD8) 964 #define USBE 7 965 #define HOST 6 966 #define FRZCLK 5 967 #define OTGPADE 4 968 #define IDTE 1 969 #define VBUSTE 0 970 971 #define USBSTA _SFR_MEM8(0XD9) 972 #define SPEED 3 973 #define ID 1 974 #define VBUS 0 975 976 #define USBINT _SFR_MEM8(0XDA) 977 #define IDTI 1 978 #define VBUSTI 0 979 980 /* Combine UDPADDL and UDPADDH */ 981 #define UDPADD _SFR_MEM16(0xDB) 982 983 #define UDPADDL _SFR_MEM8(0xDB) 984 #define UDPADDH _SFR_MEM8(0xDC) 985 #define DPACC 7 986 987 #if defined(__AT90USBxx7__) 988 989 #define OTGCON _SFR_MEM8(0XDD) 990 #define HNPREQ 5 991 #define SRPREQ 4 992 #define SRPSEL 3 993 #define VBUSHWC 2 994 #define VBUSREQ 1 995 #define VBUSRQC 0 996 997 #define OTGIEN _SFR_MEM8(0XDE) 998 #define STOE 5 999 #define HNPERRE 4 1000 #define ROLEEXE 3 1001 #define BCERRE 2 1002 #define VBERRE 1 1003 #define SRPE 0 1004 1005 #define OTGINT _SFR_MEM8(0XDF) 1006 #define STOI 5 1007 #define HNPERRI 4 1008 #define ROLEEXI 3 1009 #define BCERRI 2 1010 #define VBERRI 1 1011 #define SRPI 0 1012 1013 #endif /* __AT90USBxx7__ */ 1014 1015 #define UDCON _SFR_MEM8(0XE0) 1016 #define LSM 2 1017 #define RMWKUP 1 1018 #define DETACH 0 1019 1020 #define UDINT _SFR_MEM8(0XE1) 1021 #define UPRSMI 6 1022 #define EORSMI 5 1023 #define WAKEUPI 4 1024 #define EORSTI 3 1025 #define SOFI 2 1026 /* #define MSOFI 1 */ /* Reserved */ 1027 #define SUSPI 0 1028 1029 #define UDIEN _SFR_MEM8(0XE2) 1030 #define UPRSME 6 1031 #define EORSME 5 1032 #define WAKEUPE 4 1033 #define EORSTE 3 1034 #define SOFE 2 1035 /* #define MSOFE 1 */ /* Reserved */ 1036 #define SUSPE 0 1037 1038 #define UDADDR _SFR_MEM8(0XE3) 1039 #define ADDEN 7 1040 1041 /* Combine UDFNUML and UDFNUMH */ 1042 #define UDFNUM _SFR_MEM16(0xE4) 1043 1044 #define UDFNUML _SFR_MEM8(0xE4) 1045 #define UDFNUMH _SFR_MEM8(0xE5) 1046 1047 #define UDMFN _SFR_MEM8(0XE6) 1048 #define FNCERR 4 1049 1050 #define UDTST _SFR_MEM8(0XE7) 1051 #define OPMODE2 5 1052 #define TSTPCKT 4 1053 #define TSTK 3 1054 #define TSTJ 2 1055 1056 #define UEINTX _SFR_MEM8(0XE8) 1057 #define FIFOCON 7 1058 #define NAKINI 6 1059 #define RWAL 5 1060 #define NAKOUTI 4 1061 #define RXSTPI 3 1062 #define RXOUTI 2 1063 #define STALLEDI 1 1064 #define TXINI 0 1065 1066 #define UENUM _SFR_MEM8(0XE9) 1067 1068 #define UERST _SFR_MEM8(0XEA) 1069 #define EPRST6 6 1070 #define EPRST5 5 1071 #define EPRST4 4 1072 #define EPRST3 3 1073 #define EPRST2 2 1074 #define EPRST1 1 1075 #define EPRST0 0 1076 1077 #define UECONX _SFR_MEM8(0XEB) 1078 #define STALLRQ 5 1079 #define STALLRQC 4 1080 #define RSTDT 3 1081 #define EPEN 0 1082 1083 #define UECFG0X _SFR_MEM8(0XEC) 1084 #define EPTYPE1 7 1085 #define EPTYPE0 6 1086 /* #define ISOSW 3 */ /* Reserved */ 1087 /* #define AUTOSW 2 */ /* Reserved */ 1088 /* #define NYETSDIS 1 */ /* Reserved */ 1089 #define EPDIR 0 1090 1091 #define UECFG1X _SFR_MEM8(0XED) 1092 #define EPSIZE2 6 1093 #define EPSIZE1 5 1094 #define EPSIZE0 4 1095 #define EPBK1 3 1096 #define EPBK0 2 1097 #define ALLOC 1 1098 1099 #define UESTA0X _SFR_MEM8(0XEE) 1100 #define CFGOK 7 1101 #define OVERFI 6 1102 #define UNDERFI 5 1103 #define ZLPSEEN 4 1104 #define DTSEQ1 3 1105 #define DTSEQ0 2 1106 #define NBUSYBK1 1 1107 #define NBUSYBK0 0 1108 1109 #define UESTA1X _SFR_MEM8(0XEF) 1110 #define CTRLDIR 2 1111 #define CURRBK1 1 1112 #define CURRBK0 0 1113 1114 #define UEIENX _SFR_MEM8(0XF0) 1115 #define FLERRE 7 1116 #define NAKINE 6 1117 #define NAKOUTE 4 1118 #define RXSTPE 3 1119 #define RXOUTE 2 1120 #define STALLEDE 1 1121 #define TXINE 0 1122 1123 #define UEDATX _SFR_MEM8(0XF1) 1124 1125 /* Combine UEBCLX and UEBCHX */ 1126 #define UEBCX _SFR_MEM16(0xF2) 1127 1128 #define UEBCLX _SFR_MEM8(0xF2) 1129 #define UEBCHX _SFR_MEM8(0xF3) 1130 1131 #define UEINT _SFR_MEM8(0XF4) 1132 #define EPINT6 6 1133 #define EPINT5 5 1134 #define EPINT4 4 1135 #define EPINT3 3 1136 #define EPINT2 2 1137 #define EPINT1 1 1138 #define EPINT0 0 1139 1140 #if defined(__AT90USBxx7__) 1141 1142 #define UPERRX _SFR_MEM8(0XF5) 1143 #define COUNTER1 6 1144 #define COUNTER0 5 1145 #define CRC16 4 1146 #define TIMEOUT 3 1147 #define PID 2 1148 #define DATAPID 1 1149 #define DATATGL 0 1150 1151 /* Combine UPBCLX and UPBCHX */ 1152 #define UPBCX _SFR_MEM16(0xF6) 1153 1154 #define UPBCLX _SFR_MEM8(0xF6) 1155 #define UPBCHX _SFR_MEM8(0xF7) 1156 1157 #define UPINT _SFR_MEM8(0XF8) 1158 #define PINT6 6 1159 #define PINT5 5 1160 #define PINT4 4 1161 #define PINT3 3 1162 #define PINT2 2 1163 #define PINT1 1 1164 #define PINT0 0 1165 1166 #define OTGTCON _SFR_MEM8(0XF9) 1167 #define PAGE1 6 1168 #define PAGE0 5 1169 #define VALUE1 1 1170 #define VALUE0 0 1171 1172 #endif /* __AT90USBxx7__ */ 1173 1174 /* Reserved [0xFA..0xFF] */ 1175 1176 /* Interrupt vectors */ 1177 1178 /* External Interrupt Request 0 */ 1179 #define INT0_vect_num 1 1180 #define INT0_vect _VECTOR(1) 1181 1182 /* External Interrupt Request 1 */ 1183 #define INT1_vect_num 2 1184 #define INT1_vect _VECTOR(2) 1185 1186 /* External Interrupt Request 2 */ 1187 #define INT2_vect_num 3 1188 #define INT2_vect _VECTOR(3) 1189 1190 /* External Interrupt Request 3 */ 1191 #define INT3_vect_num 4 1192 #define INT3_vect _VECTOR(4) 1193 1194 /* External Interrupt Request 4 */ 1195 #define INT4_vect_num 5 1196 #define INT4_vect _VECTOR(5) 1197 1198 /* External Interrupt Request 5 */ 1199 #define INT5_vect_num 6 1200 #define INT5_vect _VECTOR(6) 1201 1202 /* External Interrupt Request 6 */ 1203 #define INT6_vect_num 7 1204 #define INT6_vect _VECTOR(7) 1205 1206 /* External Interrupt Request 7 */ 1207 #define INT7_vect_num 8 1208 #define INT7_vect _VECTOR(8) 1209 1210 /* Pin Change Interrupt Request 0 */ 1211 #define PCINT0_vect_num 9 1212 #define PCINT0_vect _VECTOR(9) 1213 1214 /* USB General Interrupt Request */ 1215 #define USB_GEN_vect_num 10 1216 #define USB_GEN_vect _VECTOR(10) 1217 1218 /* USB Endpoint/Pipe Interrupt Communication Request */ 1219 #define USB_COM_vect_num 11 1220 #define USB_COM_vect _VECTOR(11) 1221 1222 /* Watchdog Time-out Interrupt */ 1223 #define WDT_vect_num 12 1224 #define WDT_vect _VECTOR(12) 1225 1226 /* Timer/Counter2 Compare Match A */ 1227 #define TIMER2_COMPA_vect_num 13 1228 #define TIMER2_COMPA_vect _VECTOR(13) 1229 1230 /* Timer/Counter2 Compare Match B */ 1231 #define TIMER2_COMPB_vect_num 14 1232 #define TIMER2_COMPB_vect _VECTOR(14) 1233 1234 /* Timer/Counter2 Overflow */ 1235 #define TIMER2_OVF_vect_num 15 1236 #define TIMER2_OVF_vect _VECTOR(15) 1237 1238 /* Timer/Counter1 Capture Event */ 1239 #define TIMER1_CAPT_vect_num 16 1240 #define TIMER1_CAPT_vect _VECTOR(16) 1241 1242 /* Timer/Counter1 Compare Match A */ 1243 #define TIMER1_COMPA_vect_num 17 1244 #define TIMER1_COMPA_vect _VECTOR(17) 1245 1246 /* Timer/Counter1 Compare Match B */ 1247 #define TIMER1_COMPB_vect_num 18 1248 #define TIMER1_COMPB_vect _VECTOR(18) 1249 1250 /* Timer/Counter1 Compare Match C */ 1251 #define TIMER1_COMPC_vect_num 19 1252 #define TIMER1_COMPC_vect _VECTOR(19) 1253 1254 /* Timer/Counter1 Overflow */ 1255 #define TIMER1_OVF_vect_num 20 1256 #define TIMER1_OVF_vect _VECTOR(20) 1257 1258 /* Timer/Counter0 Compare Match A */ 1259 #define TIMER0_COMPA_vect_num 21 1260 #define TIMER0_COMPA_vect _VECTOR(21) 1261 1262 /* Timer/Counter0 Compare Match B */ 1263 #define TIMER0_COMPB_vect_num 22 1264 #define TIMER0_COMPB_vect _VECTOR(22) 1265 1266 /* Timer/Counter0 Overflow */ 1267 #define TIMER0_OVF_vect_num 23 1268 #define TIMER0_OVF_vect _VECTOR(23) 1269 1270 /* SPI Serial Transfer Complete */ 1271 #define SPI_STC_vect_num 24 1272 #define SPI_STC_vect _VECTOR(24) 1273 1274 /* USART1, Rx Complete */ 1275 #define USART1_RX_vect_num 25 1276 #define USART1_RX_vect _VECTOR(25) 1277 1278 /* USART1 Data register Empty */ 1279 #define USART1_UDRE_vect_num 26 1280 #define USART1_UDRE_vect _VECTOR(26) 1281 1282 /* USART1, Tx Complete */ 1283 #define USART1_TX_vect_num 27 1284 #define USART1_TX_vect _VECTOR(27) 1285 1286 /* Analog Comparator */ 1287 #define ANALOG_COMP_vect_num 28 1288 #define ANALOG_COMP_vect _VECTOR(28) 1289 1290 /* ADC Conversion Complete */ 1291 #define ADC_vect_num 29 1292 #define ADC_vect _VECTOR(29) 1293 1294 /* EEPROM Ready */ 1295 #define EE_READY_vect_num 30 1296 #define EE_READY_vect _VECTOR(30) 1297 1298 /* Timer/Counter3 Capture Event */ 1299 #define TIMER3_CAPT_vect_num 31 1300 #define TIMER3_CAPT_vect _VECTOR(31) 1301 1302 /* Timer/Counter3 Compare Match A */ 1303 #define TIMER3_COMPA_vect_num 32 1304 #define TIMER3_COMPA_vect _VECTOR(32) 1305 1306 /* Timer/Counter3 Compare Match B */ 1307 #define TIMER3_COMPB_vect_num 33 1308 #define TIMER3_COMPB_vect _VECTOR(33) 1309 1310 /* Timer/Counter3 Compare Match C */ 1311 #define TIMER3_COMPC_vect_num 34 1312 #define TIMER3_COMPC_vect _VECTOR(34) 1313 1314 /* Timer/Counter3 Overflow */ 1315 #define TIMER3_OVF_vect_num 35 1316 #define TIMER3_OVF_vect _VECTOR(35) 1317 1318 /* 2-wire Serial Interface */ 1319 #define TWI_vect_num 36 1320 #define TWI_vect _VECTOR(36) 1321 1322 /* Store Program Memory Read */ 1323 #define SPM_READY_vect_num 37 1324 #define SPM_READY_vect _VECTOR(37) 1325 1326 #define _VECTORS_SIZE 152 1327 1328 #if defined(__AT90USBxx6__) 1329 # undef __AT90USBxx6__ 1330 #endif /* __AT90USBxx6__ */ 1331 1332 #if defined(__AT90USBxx7__) 1333 # undef __AT90USBxx7__ 1334 #endif /* __AT90USBxx7__ */ 1335 1336 #endif /* _AVR_IOUSBXX6_7_H_ */ 1337