1;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ******************** 2;***** Created: 2011-02-09 12:03 ******* Source: ATmega1280.xml ********** 3;************************************************************************* 4;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y 5;* 6;* Number : AVR000 7;* File Name : "m1280def.inc" 8;* Title : Register/Bit Definitions for the ATmega1280 9;* Date : 2011-02-09 10;* Version : 2.35 11;* Support E-mail : avr@atmel.com 12;* Target MCU : ATmega1280 13;* 14;* DESCRIPTION 15;* When including this file in the assembly program file, all I/O register 16;* names and I/O register bit names appearing in the data book can be used. 17;* In addition, the six registers forming the three data pointers X, Y and 18;* Z have been assigned names XL - ZH. Highest RAM address for Internal 19;* SRAM is also defined 20;* 21;* The Register names are represented by their hexadecimal address. 22;* 23;* The Register Bit names are represented by their bit number (0-7). 24;* 25;* Please observe the difference in using the bit names with instructions 26;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" 27;* (skip if bit in register set/cleared). The following example illustrates 28;* this: 29;* 30;* in r16,PORTB ;read PORTB latch 31;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#) 32;* out PORTB,r16 ;output to PORTB 33;* 34;* in r16,TIFR ;read the Timer Interrupt Flag Register 35;* sbrc r16,TOV0 ;test the overflow flag (use bit#) 36;* rjmp TOV0_is_set ;jump if set 37;* ... ;otherwise do something else 38;************************************************************************* 39 40#ifndef _M1280DEF_INC_ 41#define _M1280DEF_INC_ 42 43 44#pragma partinc 0 45 46; ***** SPECIFY DEVICE *************************************************** 47.device ATmega1280 48#pragma AVRPART ADMIN PART_NAME ATmega1280 49.equ SIGNATURE_000 = 0x1e 50.equ SIGNATURE_001 = 0x97 51.equ SIGNATURE_002 = 0x03 52 53#pragma AVRPART CORE CORE_VERSION V3 54 55 56; ***** I/O REGISTER DEFINITIONS ***************************************** 57; NOTE: 58; Definitions marked "MEMORY MAPPED"are extended I/O ports 59; and cannot be used with IN/OUT instructions 60.equ UDR3 = 0x136 ; MEMORY MAPPED 61.equ UBRR3L = 0x134 ; MEMORY MAPPED 62.equ UBRR3H = 0x135 ; MEMORY MAPPED 63.equ UCSR3C = 0x132 ; MEMORY MAPPED 64.equ UCSR3B = 0x131 ; MEMORY MAPPED 65.equ UCSR3A = 0x130 ; MEMORY MAPPED 66.equ OCR5CL = 0x12c ; MEMORY MAPPED 67.equ OCR5CH = 0x12d ; MEMORY MAPPED 68.equ OCR5BL = 0x12a ; MEMORY MAPPED 69.equ OCR5BH = 0x12b ; MEMORY MAPPED 70.equ OCR5AL = 0x128 ; MEMORY MAPPED 71.equ OCR5AH = 0x129 ; MEMORY MAPPED 72.equ ICR5H = 0x127 ; MEMORY MAPPED 73.equ ICR5L = 0x126 ; MEMORY MAPPED 74.equ TCNT5L = 0x124 ; MEMORY MAPPED 75.equ TCNT5H = 0x125 ; MEMORY MAPPED 76.equ TCCR5C = 0x122 ; MEMORY MAPPED 77.equ TCCR5B = 0x121 ; MEMORY MAPPED 78.equ TCCR5A = 0x120 ; MEMORY MAPPED 79.equ PORTL = 0x10b ; MEMORY MAPPED 80.equ DDRL = 0x10a ; MEMORY MAPPED 81.equ PINL = 0x109 ; MEMORY MAPPED 82.equ PORTK = 0x108 ; MEMORY MAPPED 83.equ DDRK = 0x107 ; MEMORY MAPPED 84.equ PINK = 0x106 ; MEMORY MAPPED 85.equ PORTJ = 0x105 ; MEMORY MAPPED 86.equ DDRJ = 0x104 ; MEMORY MAPPED 87.equ PINJ = 0x103 ; MEMORY MAPPED 88.equ PORTH = 0x102 ; MEMORY MAPPED 89.equ DDRH = 0x101 ; MEMORY MAPPED 90.equ PINH = 0x100 ; MEMORY MAPPED 91.equ UDR2 = 0xd6 ; MEMORY MAPPED 92.equ UBRR2L = 0xd4 ; MEMORY MAPPED 93.equ UBRR2H = 0xd5 ; MEMORY MAPPED 94.equ UCSR2C = 0xd2 ; MEMORY MAPPED 95.equ UCSR2B = 0xd1 ; MEMORY MAPPED 96.equ UCSR2A = 0xd0 ; MEMORY MAPPED 97.equ UDR1 = 0xce ; MEMORY MAPPED 98.equ UBRR1L = 0xcc ; MEMORY MAPPED 99.equ UBRR1H = 0xcd ; MEMORY MAPPED 100.equ UCSR1C = 0xca ; MEMORY MAPPED 101.equ UCSR1B = 0xc9 ; MEMORY MAPPED 102.equ UCSR1A = 0xc8 ; MEMORY MAPPED 103.equ UDR0 = 0xc6 ; MEMORY MAPPED 104.equ UBRR0L = 0xc4 ; MEMORY MAPPED 105.equ UBRR0H = 0xc5 ; MEMORY MAPPED 106.equ UCSR0C = 0xc2 ; MEMORY MAPPED 107.equ UCSR0B = 0xc1 ; MEMORY MAPPED 108.equ UCSR0A = 0xc0 ; MEMORY MAPPED 109.equ TWAMR = 0xbd ; MEMORY MAPPED 110.equ TWCR = 0xbc ; MEMORY MAPPED 111.equ TWDR = 0xbb ; MEMORY MAPPED 112.equ TWAR = 0xba ; MEMORY MAPPED 113.equ TWSR = 0xb9 ; MEMORY MAPPED 114.equ TWBR = 0xb8 ; MEMORY MAPPED 115.equ ASSR = 0xb6 ; MEMORY MAPPED 116.equ OCR2B = 0xb4 ; MEMORY MAPPED 117.equ OCR2A = 0xb3 ; MEMORY MAPPED 118.equ TCNT2 = 0xb2 ; MEMORY MAPPED 119.equ TCCR2B = 0xb1 ; MEMORY MAPPED 120.equ TCCR2A = 0xb0 ; MEMORY MAPPED 121.equ OCR4CL = 0xac ; MEMORY MAPPED 122.equ OCR4CH = 0xad ; MEMORY MAPPED 123.equ OCR4BL = 0xaa ; MEMORY MAPPED 124.equ OCR4BH = 0xab ; MEMORY MAPPED 125.equ OCR4AL = 0xa8 ; MEMORY MAPPED 126.equ OCR4AH = 0xa9 ; MEMORY MAPPED 127.equ ICR4L = 0xa6 ; MEMORY MAPPED 128.equ ICR4H = 0xa7 ; MEMORY MAPPED 129.equ TCNT4L = 0xa4 ; MEMORY MAPPED 130.equ TCNT4H = 0xa5 ; MEMORY MAPPED 131.equ TCCR4C = 0xa2 ; MEMORY MAPPED 132.equ TCCR4B = 0xa1 ; MEMORY MAPPED 133.equ TCCR4A = 0xa0 ; MEMORY MAPPED 134.equ OCR3CL = 0x9c ; MEMORY MAPPED 135.equ OCR3CH = 0x9d ; MEMORY MAPPED 136.equ OCR3BL = 0x9a ; MEMORY MAPPED 137.equ OCR3BH = 0x9b ; MEMORY MAPPED 138.equ OCR3AL = 0x98 ; MEMORY MAPPED 139.equ OCR3AH = 0x99 ; MEMORY MAPPED 140.equ ICR3L = 0x96 ; MEMORY MAPPED 141.equ ICR3H = 0x97 ; MEMORY MAPPED 142.equ TCNT3L = 0x94 ; MEMORY MAPPED 143.equ TCNT3H = 0x95 ; MEMORY MAPPED 144.equ TCCR3C = 0x92 ; MEMORY MAPPED 145.equ TCCR3B = 0x91 ; MEMORY MAPPED 146.equ TCCR3A = 0x90 ; MEMORY MAPPED 147.equ OCR1CL = 0x8c ; MEMORY MAPPED 148.equ OCR1CH = 0x8d ; MEMORY MAPPED 149.equ OCR1BL = 0x8a ; MEMORY MAPPED 150.equ OCR1BH = 0x8b ; MEMORY MAPPED 151.equ OCR1AL = 0x88 ; MEMORY MAPPED 152.equ OCR1AH = 0x89 ; MEMORY MAPPED 153.equ ICR1L = 0x86 ; MEMORY MAPPED 154.equ ICR1H = 0x87 ; MEMORY MAPPED 155.equ TCNT1L = 0x84 ; MEMORY MAPPED 156.equ TCNT1H = 0x85 ; MEMORY MAPPED 157.equ TCCR1C = 0x82 ; MEMORY MAPPED 158.equ TCCR1B = 0x81 ; MEMORY MAPPED 159.equ TCCR1A = 0x80 ; MEMORY MAPPED 160.equ DIDR1 = 0x7f ; MEMORY MAPPED 161.equ DIDR0 = 0x7e ; MEMORY MAPPED 162.equ DIDR2 = 0x7d ; MEMORY MAPPED 163.equ ADMUX = 0x7c ; MEMORY MAPPED 164.equ ADCSRB = 0x7b ; MEMORY MAPPED 165.equ ADCSRA = 0x7a ; MEMORY MAPPED 166.equ ADCH = 0x79 ; MEMORY MAPPED 167.equ ADCL = 0x78 ; MEMORY MAPPED 168.equ XMCRB = 0x75 ; MEMORY MAPPED 169.equ XMCRA = 0x74 ; MEMORY MAPPED 170.equ TIMSK5 = 0x73 ; MEMORY MAPPED 171.equ TIMSK4 = 0x72 ; MEMORY MAPPED 172.equ TIMSK3 = 0x71 ; MEMORY MAPPED 173.equ TIMSK2 = 0x70 ; MEMORY MAPPED 174.equ TIMSK1 = 0x6f ; MEMORY MAPPED 175.equ TIMSK0 = 0x6e ; MEMORY MAPPED 176.equ PCMSK2 = 0x6d ; MEMORY MAPPED 177.equ PCMSK1 = 0x6c ; MEMORY MAPPED 178.equ PCMSK0 = 0x6b ; MEMORY MAPPED 179.equ EICRB = 0x6a ; MEMORY MAPPED 180.equ EICRA = 0x69 ; MEMORY MAPPED 181.equ PCICR = 0x68 ; MEMORY MAPPED 182.equ OSCCAL = 0x66 ; MEMORY MAPPED 183.equ PRR1 = 0x65 ; MEMORY MAPPED 184.equ PRR0 = 0x64 ; MEMORY MAPPED 185.equ CLKPR = 0x61 ; MEMORY MAPPED 186.equ WDTCSR = 0x60 ; MEMORY MAPPED 187.equ SREG = 0x3f 188.equ SPL = 0x3d 189.equ SPH = 0x3e 190.equ EIND = 0x3c 191.equ RAMPZ = 0x3b 192.equ SPMCSR = 0x37 193.equ MCUCR = 0x35 194.equ MCUSR = 0x34 195.equ SMCR = 0x33 196.equ OCDR = 0x31 197.equ ACSR = 0x30 198.equ SPDR = 0x2e 199.equ SPSR = 0x2d 200.equ SPCR = 0x2c 201.equ GPIOR2 = 0x2b 202.equ GPIOR1 = 0x2a 203.equ OCR0B = 0x28 204.equ OCR0A = 0x27 205.equ TCNT0 = 0x26 206.equ TCCR0B = 0x25 207.equ TCCR0A = 0x24 208.equ GTCCR = 0x23 209.equ EEARH = 0x22 210.equ EEARL = 0x21 211.equ EEDR = 0x20 212.equ EECR = 0x1f 213.equ GPIOR0 = 0x1e 214.equ EIMSK = 0x1d 215.equ EIFR = 0x1c 216.equ PCIFR = 0x1b 217.equ TIFR5 = 0x1a 218.equ TIFR4 = 0x19 219.equ TIFR3 = 0x18 220.equ TIFR2 = 0x17 221.equ TIFR1 = 0x16 222.equ TIFR0 = 0x15 223.equ PORTG = 0x14 224.equ DDRG = 0x13 225.equ PING = 0x12 226.equ PORTF = 0x11 227.equ DDRF = 0x10 228.equ PINF = 0x0f 229.equ PORTE = 0x0e 230.equ DDRE = 0x0d 231.equ PINE = 0x0c 232.equ PORTD = 0x0b 233.equ DDRD = 0x0a 234.equ PIND = 0x09 235.equ PORTC = 0x08 236.equ DDRC = 0x07 237.equ PINC = 0x06 238.equ PORTB = 0x05 239.equ DDRB = 0x04 240.equ PINB = 0x03 241.equ PORTA = 0x02 242.equ DDRA = 0x01 243.equ PINA = 0x00 244 245 246; ***** BIT DEFINITIONS ************************************************** 247 248; ***** ANALOG_COMPARATOR ************ 249; ADCSRB - ADC Control and Status Register B 250.equ ACME = 6 ; Analog Comparator Multiplexer Enable 251 252; ACSR - Analog Comparator Control And Status Register 253.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0 254.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1 255.equ ACIC = 2 ; Analog Comparator Input Capture Enable 256.equ ACIE = 3 ; Analog Comparator Interrupt Enable 257.equ ACI = 4 ; Analog Comparator Interrupt Flag 258.equ ACO = 5 ; Analog Compare Output 259.equ ACBG = 6 ; Analog Comparator Bandgap Select 260.equ ACD = 7 ; Analog Comparator Disable 261 262; DIDR1 - Digital Input Disable Register 1 263.equ AIN0D = 0 ; AIN0 Digital Input Disable 264.equ AIN1D = 1 ; AIN1 Digital Input Disable 265 266 267; ***** USART0 *********************** 268; UDR0 - USART I/O Data Register 269.equ UDR0_0 = 0 ; USART I/O Data Register bit 0 270.equ UDR0_1 = 1 ; USART I/O Data Register bit 1 271.equ UDR0_2 = 2 ; USART I/O Data Register bit 2 272.equ UDR0_3 = 3 ; USART I/O Data Register bit 3 273.equ UDR0_4 = 4 ; USART I/O Data Register bit 4 274.equ UDR0_5 = 5 ; USART I/O Data Register bit 5 275.equ UDR0_6 = 6 ; USART I/O Data Register bit 6 276.equ UDR0_7 = 7 ; USART I/O Data Register bit 7 277 278; UCSR0A - USART Control and Status Register A 279.equ MPCM0 = 0 ; Multi-processor Communication Mode 280.equ U2X0 = 1 ; Double the USART transmission speed 281.equ UPE0 = 2 ; Parity Error 282.equ DOR0 = 3 ; Data overRun 283.equ FE0 = 4 ; Framing Error 284.equ UDRE0 = 5 ; USART Data Register Empty 285.equ TXC0 = 6 ; USART Transmitt Complete 286.equ RXC0 = 7 ; USART Receive Complete 287 288; UCSR0B - USART Control and Status Register B 289.equ TXB80 = 0 ; Transmit Data Bit 8 290.equ RXB80 = 1 ; Receive Data Bit 8 291.equ UCSZ02 = 2 ; Character Size 292.equ TXEN0 = 3 ; Transmitter Enable 293.equ RXEN0 = 4 ; Receiver Enable 294.equ UDRIE0 = 5 ; USART Data register Empty Interrupt Enable 295.equ TXCIE0 = 6 ; TX Complete Interrupt Enable 296.equ RXCIE0 = 7 ; RX Complete Interrupt Enable 297 298; UCSR0C - USART Control and Status Register C 299.equ UCPOL0 = 0 ; Clock Polarity 300.equ UCSZ00 = 1 ; Character Size 301.equ UCPHA0 = UCSZ00 ; For compatibility 302.equ UCSZ01 = 2 ; Character Size 303.equ UDORD0 = UCSZ01 ; For compatibility 304.equ USBS0 = 3 ; Stop Bit Select 305.equ UPM00 = 4 ; Parity Mode Bit 0 306.equ UPM01 = 5 ; Parity Mode Bit 1 307.equ UMSEL00 = 6 ; USART Mode Select 308.equ UMSEL0 = UMSEL00 ; For compatibility 309.equ UMSEL01 = 7 ; USART Mode Select 310.equ UMSEL1 = UMSEL01 ; For compatibility 311 312; UBRR0H - USART Baud Rate Register High Byte 313.equ UBRR8 = 0 ; USART Baud Rate Register bit 8 314.equ UBRR9 = 1 ; USART Baud Rate Register bit 9 315.equ UBRR10 = 2 ; USART Baud Rate Register bit 10 316.equ UBRR11 = 3 ; USART Baud Rate Register bit 11 317 318; UBRR0L - USART Baud Rate Register Low Byte 319.equ _UBRR0 = 0 ; USART Baud Rate Register bit 0 320.equ _UBRR1 = 1 ; USART Baud Rate Register bit 1 321.equ UBRR2 = 2 ; USART Baud Rate Register bit 2 322.equ UBRR3 = 3 ; USART Baud Rate Register bit 3 323.equ UBRR4 = 4 ; USART Baud Rate Register bit 4 324.equ UBRR5 = 5 ; USART Baud Rate Register bit 5 325.equ UBRR6 = 6 ; USART Baud Rate Register bit 6 326.equ UBRR7 = 7 ; USART Baud Rate Register bit 7 327 328 329; ***** TWI ************************** 330; TWAMR - TWI (Slave) Address Mask Register 331.equ TWAM0 = 1 ; 332.equ TWAMR0 = TWAM0 ; For compatibility 333.equ TWAM1 = 2 ; 334.equ TWAMR1 = TWAM1 ; For compatibility 335.equ TWAM2 = 3 ; 336.equ TWAMR2 = TWAM2 ; For compatibility 337.equ TWAM3 = 4 ; 338.equ TWAMR3 = TWAM3 ; For compatibility 339.equ TWAM4 = 5 ; 340.equ TWAMR4 = TWAM4 ; For compatibility 341.equ TWAM5 = 6 ; 342.equ TWAMR5 = TWAM5 ; For compatibility 343.equ TWAM6 = 7 ; 344.equ TWAMR6 = TWAM6 ; For compatibility 345 346; TWBR - TWI Bit Rate register 347.equ TWBR0 = 0 ; 348.equ TWBR1 = 1 ; 349.equ TWBR2 = 2 ; 350.equ TWBR3 = 3 ; 351.equ TWBR4 = 4 ; 352.equ TWBR5 = 5 ; 353.equ TWBR6 = 6 ; 354.equ TWBR7 = 7 ; 355 356; TWCR - TWI Control Register 357.equ TWIE = 0 ; TWI Interrupt Enable 358.equ TWEN = 2 ; TWI Enable Bit 359.equ TWWC = 3 ; TWI Write Collition Flag 360.equ TWSTO = 4 ; TWI Stop Condition Bit 361.equ TWSTA = 5 ; TWI Start Condition Bit 362.equ TWEA = 6 ; TWI Enable Acknowledge Bit 363.equ TWINT = 7 ; TWI Interrupt Flag 364 365; TWSR - TWI Status Register 366.equ TWPS0 = 0 ; TWI Prescaler 367.equ TWPS1 = 1 ; TWI Prescaler 368.equ TWS3 = 3 ; TWI Status 369.equ TWS4 = 4 ; TWI Status 370.equ TWS5 = 5 ; TWI Status 371.equ TWS6 = 6 ; TWI Status 372.equ TWS7 = 7 ; TWI Status 373 374; TWDR - TWI Data register 375.equ TWD0 = 0 ; TWI Data Register Bit 0 376.equ TWD1 = 1 ; TWI Data Register Bit 1 377.equ TWD2 = 2 ; TWI Data Register Bit 2 378.equ TWD3 = 3 ; TWI Data Register Bit 3 379.equ TWD4 = 4 ; TWI Data Register Bit 4 380.equ TWD5 = 5 ; TWI Data Register Bit 5 381.equ TWD6 = 6 ; TWI Data Register Bit 6 382.equ TWD7 = 7 ; TWI Data Register Bit 7 383 384; TWAR - TWI (Slave) Address register 385.equ TWGCE = 0 ; TWI General Call Recognition Enable Bit 386.equ TWA0 = 1 ; TWI (Slave) Address register Bit 0 387.equ TWA1 = 2 ; TWI (Slave) Address register Bit 1 388.equ TWA2 = 3 ; TWI (Slave) Address register Bit 2 389.equ TWA3 = 4 ; TWI (Slave) Address register Bit 3 390.equ TWA4 = 5 ; TWI (Slave) Address register Bit 4 391.equ TWA5 = 6 ; TWI (Slave) Address register Bit 5 392.equ TWA6 = 7 ; TWI (Slave) Address register Bit 6 393 394 395; ***** SPI ************************** 396; SPDR - SPI Data Register 397.equ SPDR0 = 0 ; SPI Data Register bit 0 398.equ SPDR1 = 1 ; SPI Data Register bit 1 399.equ SPDR2 = 2 ; SPI Data Register bit 2 400.equ SPDR3 = 3 ; SPI Data Register bit 3 401.equ SPDR4 = 4 ; SPI Data Register bit 4 402.equ SPDR5 = 5 ; SPI Data Register bit 5 403.equ SPDR6 = 6 ; SPI Data Register bit 6 404.equ SPDR7 = 7 ; SPI Data Register bit 7 405 406; SPSR - SPI Status Register 407.equ SPI2X = 0 ; Double SPI Speed Bit 408.equ WCOL = 6 ; Write Collision Flag 409.equ SPIF = 7 ; SPI Interrupt Flag 410 411; SPCR - SPI Control Register 412.equ SPR0 = 0 ; SPI Clock Rate Select 0 413.equ SPR1 = 1 ; SPI Clock Rate Select 1 414.equ CPHA = 2 ; Clock Phase 415.equ CPOL = 3 ; Clock polarity 416.equ MSTR = 4 ; Master/Slave Select 417.equ DORD = 5 ; Data Order 418.equ SPE = 6 ; SPI Enable 419.equ SPIE = 7 ; SPI Interrupt Enable 420 421 422; ***** PORTA ************************ 423; PORTA - Port A Data Register 424.equ PORTA0 = 0 ; Port A Data Register bit 0 425.equ PA0 = 0 ; For compatibility 426.equ PORTA1 = 1 ; Port A Data Register bit 1 427.equ PA1 = 1 ; For compatibility 428.equ PORTA2 = 2 ; Port A Data Register bit 2 429.equ PA2 = 2 ; For compatibility 430.equ PORTA3 = 3 ; Port A Data Register bit 3 431.equ PA3 = 3 ; For compatibility 432.equ PORTA4 = 4 ; Port A Data Register bit 4 433.equ PA4 = 4 ; For compatibility 434.equ PORTA5 = 5 ; Port A Data Register bit 5 435.equ PA5 = 5 ; For compatibility 436.equ PORTA6 = 6 ; Port A Data Register bit 6 437.equ PA6 = 6 ; For compatibility 438.equ PORTA7 = 7 ; Port A Data Register bit 7 439.equ PA7 = 7 ; For compatibility 440 441; DDRA - Port A Data Direction Register 442.equ DDA0 = 0 ; Data Direction Register, Port A, bit 0 443.equ DDA1 = 1 ; Data Direction Register, Port A, bit 1 444.equ DDA2 = 2 ; Data Direction Register, Port A, bit 2 445.equ DDA3 = 3 ; Data Direction Register, Port A, bit 3 446.equ DDA4 = 4 ; Data Direction Register, Port A, bit 4 447.equ DDA5 = 5 ; Data Direction Register, Port A, bit 5 448.equ DDA6 = 6 ; Data Direction Register, Port A, bit 6 449.equ DDA7 = 7 ; Data Direction Register, Port A, bit 7 450 451; PINA - Port A Input Pins 452.equ PINA0 = 0 ; Input Pins, Port A bit 0 453.equ PINA1 = 1 ; Input Pins, Port A bit 1 454.equ PINA2 = 2 ; Input Pins, Port A bit 2 455.equ PINA3 = 3 ; Input Pins, Port A bit 3 456.equ PINA4 = 4 ; Input Pins, Port A bit 4 457.equ PINA5 = 5 ; Input Pins, Port A bit 5 458.equ PINA6 = 6 ; Input Pins, Port A bit 6 459.equ PINA7 = 7 ; Input Pins, Port A bit 7 460 461 462; ***** PORTB ************************ 463; PORTB - Port B Data Register 464.equ PORTB0 = 0 ; Port B Data Register bit 0 465.equ PB0 = 0 ; For compatibility 466.equ PORTB1 = 1 ; Port B Data Register bit 1 467.equ PB1 = 1 ; For compatibility 468.equ PORTB2 = 2 ; Port B Data Register bit 2 469.equ PB2 = 2 ; For compatibility 470.equ PORTB3 = 3 ; Port B Data Register bit 3 471.equ PB3 = 3 ; For compatibility 472.equ PORTB4 = 4 ; Port B Data Register bit 4 473.equ PB4 = 4 ; For compatibility 474.equ PORTB5 = 5 ; Port B Data Register bit 5 475.equ PB5 = 5 ; For compatibility 476.equ PORTB6 = 6 ; Port B Data Register bit 6 477.equ PB6 = 6 ; For compatibility 478.equ PORTB7 = 7 ; Port B Data Register bit 7 479.equ PB7 = 7 ; For compatibility 480 481; DDRB - Port B Data Direction Register 482.equ DDB0 = 0 ; Port B Data Direction Register bit 0 483.equ DDB1 = 1 ; Port B Data Direction Register bit 1 484.equ DDB2 = 2 ; Port B Data Direction Register bit 2 485.equ DDB3 = 3 ; Port B Data Direction Register bit 3 486.equ DDB4 = 4 ; Port B Data Direction Register bit 4 487.equ DDB5 = 5 ; Port B Data Direction Register bit 5 488.equ DDB6 = 6 ; Port B Data Direction Register bit 6 489.equ DDB7 = 7 ; Port B Data Direction Register bit 7 490 491; PINB - Port B Input Pins 492.equ PINB0 = 0 ; Port B Input Pins bit 0 493.equ PINB1 = 1 ; Port B Input Pins bit 1 494.equ PINB2 = 2 ; Port B Input Pins bit 2 495.equ PINB3 = 3 ; Port B Input Pins bit 3 496.equ PINB4 = 4 ; Port B Input Pins bit 4 497.equ PINB5 = 5 ; Port B Input Pins bit 5 498.equ PINB6 = 6 ; Port B Input Pins bit 6 499.equ PINB7 = 7 ; Port B Input Pins bit 7 500 501 502; ***** PORTC ************************ 503; PORTC - Port C Data Register 504.equ PORTC0 = 0 ; Port C Data Register bit 0 505.equ PC0 = 0 ; For compatibility 506.equ PORTC1 = 1 ; Port C Data Register bit 1 507.equ PC1 = 1 ; For compatibility 508.equ PORTC2 = 2 ; Port C Data Register bit 2 509.equ PC2 = 2 ; For compatibility 510.equ PORTC3 = 3 ; Port C Data Register bit 3 511.equ PC3 = 3 ; For compatibility 512.equ PORTC4 = 4 ; Port C Data Register bit 4 513.equ PC4 = 4 ; For compatibility 514.equ PORTC5 = 5 ; Port C Data Register bit 5 515.equ PC5 = 5 ; For compatibility 516.equ PORTC6 = 6 ; Port C Data Register bit 6 517.equ PC6 = 6 ; For compatibility 518.equ PORTC7 = 7 ; Port C Data Register bit 7 519.equ PC7 = 7 ; For compatibility 520 521; DDRC - Port C Data Direction Register 522.equ DDC0 = 0 ; Port C Data Direction Register bit 0 523.equ DDC1 = 1 ; Port C Data Direction Register bit 1 524.equ DDC2 = 2 ; Port C Data Direction Register bit 2 525.equ DDC3 = 3 ; Port C Data Direction Register bit 3 526.equ DDC4 = 4 ; Port C Data Direction Register bit 4 527.equ DDC5 = 5 ; Port C Data Direction Register bit 5 528.equ DDC6 = 6 ; Port C Data Direction Register bit 6 529.equ DDC7 = 7 ; Port C Data Direction Register bit 7 530 531; PINC - Port C Input Pins 532.equ PINC0 = 0 ; Port C Input Pins bit 0 533.equ PINC1 = 1 ; Port C Input Pins bit 1 534.equ PINC2 = 2 ; Port C Input Pins bit 2 535.equ PINC3 = 3 ; Port C Input Pins bit 3 536.equ PINC4 = 4 ; Port C Input Pins bit 4 537.equ PINC5 = 5 ; Port C Input Pins bit 5 538.equ PINC6 = 6 ; Port C Input Pins bit 6 539.equ PINC7 = 7 ; Port C Input Pins bit 7 540 541 542; ***** PORTD ************************ 543; PORTD - Port D Data Register 544.equ PORTD0 = 0 ; Port D Data Register bit 0 545.equ PD0 = 0 ; For compatibility 546.equ PORTD1 = 1 ; Port D Data Register bit 1 547.equ PD1 = 1 ; For compatibility 548.equ PORTD2 = 2 ; Port D Data Register bit 2 549.equ PD2 = 2 ; For compatibility 550.equ PORTD3 = 3 ; Port D Data Register bit 3 551.equ PD3 = 3 ; For compatibility 552.equ PORTD4 = 4 ; Port D Data Register bit 4 553.equ PD4 = 4 ; For compatibility 554.equ PORTD5 = 5 ; Port D Data Register bit 5 555.equ PD5 = 5 ; For compatibility 556.equ PORTD6 = 6 ; Port D Data Register bit 6 557.equ PD6 = 6 ; For compatibility 558.equ PORTD7 = 7 ; Port D Data Register bit 7 559.equ PD7 = 7 ; For compatibility 560 561; DDRD - Port D Data Direction Register 562.equ DDD0 = 0 ; Port D Data Direction Register bit 0 563.equ DDD1 = 1 ; Port D Data Direction Register bit 1 564.equ DDD2 = 2 ; Port D Data Direction Register bit 2 565.equ DDD3 = 3 ; Port D Data Direction Register bit 3 566.equ DDD4 = 4 ; Port D Data Direction Register bit 4 567.equ DDD5 = 5 ; Port D Data Direction Register bit 5 568.equ DDD6 = 6 ; Port D Data Direction Register bit 6 569.equ DDD7 = 7 ; Port D Data Direction Register bit 7 570 571; PIND - Port D Input Pins 572.equ PIND0 = 0 ; Port D Input Pins bit 0 573.equ PIND1 = 1 ; Port D Input Pins bit 1 574.equ PIND2 = 2 ; Port D Input Pins bit 2 575.equ PIND3 = 3 ; Port D Input Pins bit 3 576.equ PIND4 = 4 ; Port D Input Pins bit 4 577.equ PIND5 = 5 ; Port D Input Pins bit 5 578.equ PIND6 = 6 ; Port D Input Pins bit 6 579.equ PIND7 = 7 ; Port D Input Pins bit 7 580 581 582; ***** PORTE ************************ 583; PORTE - Data Register, Port E 584.equ PORTE0 = 0 ; 585.equ PE0 = 0 ; For compatibility 586.equ PORTE1 = 1 ; 587.equ PE1 = 1 ; For compatibility 588.equ PORTE2 = 2 ; 589.equ PE2 = 2 ; For compatibility 590.equ PORTE3 = 3 ; 591.equ PE3 = 3 ; For compatibility 592.equ PORTE4 = 4 ; 593.equ PE4 = 4 ; For compatibility 594.equ PORTE5 = 5 ; 595.equ PE5 = 5 ; For compatibility 596.equ PORTE6 = 6 ; 597.equ PE6 = 6 ; For compatibility 598.equ PORTE7 = 7 ; 599.equ PE7 = 7 ; For compatibility 600 601; DDRE - Data Direction Register, Port E 602.equ DDE0 = 0 ; 603.equ DDE1 = 1 ; 604.equ DDE2 = 2 ; 605.equ DDE3 = 3 ; 606.equ DDE4 = 4 ; 607.equ DDE5 = 5 ; 608.equ DDE6 = 6 ; 609.equ DDE7 = 7 ; 610 611; PINE - Input Pins, Port E 612.equ PINE0 = 0 ; 613.equ PINE1 = 1 ; 614.equ PINE2 = 2 ; 615.equ PINE3 = 3 ; 616.equ PINE4 = 4 ; 617.equ PINE5 = 5 ; 618.equ PINE6 = 6 ; 619.equ PINE7 = 7 ; 620 621 622; ***** PORTF ************************ 623; PORTF - Data Register, Port F 624.equ PORTF0 = 0 ; 625.equ PF0 = 0 ; For compatibility 626.equ PORTF1 = 1 ; 627.equ PF1 = 1 ; For compatibility 628.equ PORTF2 = 2 ; 629.equ PF2 = 2 ; For compatibility 630.equ PORTF3 = 3 ; 631.equ PF3 = 3 ; For compatibility 632.equ PORTF4 = 4 ; 633.equ PF4 = 4 ; For compatibility 634.equ PORTF5 = 5 ; 635.equ PF5 = 5 ; For compatibility 636.equ PORTF6 = 6 ; 637.equ PF6 = 6 ; For compatibility 638.equ PORTF7 = 7 ; 639.equ PF7 = 7 ; For compatibility 640 641; DDRF - Data Direction Register, Port F 642.equ DDF0 = 0 ; 643.equ DDF1 = 1 ; 644.equ DDF2 = 2 ; 645.equ DDF3 = 3 ; 646.equ DDF4 = 4 ; 647.equ DDF5 = 5 ; 648.equ DDF6 = 6 ; 649.equ DDF7 = 7 ; 650 651; PINF - Input Pins, Port F 652.equ PINF0 = 0 ; 653.equ PINF1 = 1 ; 654.equ PINF2 = 2 ; 655.equ PINF3 = 3 ; 656.equ PINF4 = 4 ; 657.equ PINF5 = 5 ; 658.equ PINF6 = 6 ; 659.equ PINF7 = 7 ; 660 661 662; ***** PORTG ************************ 663; PORTG - Data Register, Port G 664.equ PORTG0 = 0 ; 665.equ PG0 = 0 ; For compatibility 666.equ PORTG1 = 1 ; 667.equ PG1 = 1 ; For compatibility 668.equ PORTG2 = 2 ; 669.equ PG2 = 2 ; For compatibility 670.equ PORTG3 = 3 ; 671.equ PG3 = 3 ; For compatibility 672.equ PORTG4 = 4 ; 673.equ PG4 = 4 ; For compatibility 674.equ PORTG5 = 5 ; 675.equ PG5 = 5 ; For compatibility 676 677; DDRG - Data Direction Register, Port G 678.equ DDG0 = 0 ; 679.equ DDG1 = 1 ; 680.equ DDG2 = 2 ; 681.equ DDG3 = 3 ; 682.equ DDG4 = 4 ; 683.equ DDG5 = 5 ; 684 685; PING - Input Pins, Port G 686.equ PING0 = 0 ; 687.equ PING1 = 1 ; 688.equ PING2 = 2 ; 689.equ PING3 = 3 ; 690.equ PING4 = 4 ; 691.equ PING5 = 5 ; 692 693 694; ***** PORTH ************************ 695; PORTH - PORT H Data Register 696.equ PORTH0 = 0 ; PORT H Data Register bit 0 697.equ PH0 = 0 ; For compatibility 698.equ PORTH1 = 1 ; PORT H Data Register bit 1 699.equ PH1 = 1 ; For compatibility 700.equ PORTH2 = 2 ; PORT H Data Register bit 2 701.equ PH2 = 2 ; For compatibility 702.equ PORTH3 = 3 ; PORT H Data Register bit 3 703.equ PH3 = 3 ; For compatibility 704.equ PORTH4 = 4 ; PORT H Data Register bit 4 705.equ PH4 = 4 ; For compatibility 706.equ PORTH5 = 5 ; PORT H Data Register bit 5 707.equ PH5 = 5 ; For compatibility 708.equ PORTH6 = 6 ; PORT H Data Register bit 6 709.equ PH6 = 6 ; For compatibility 710.equ PORTH7 = 7 ; PORT H Data Register bit 7 711.equ PH7 = 7 ; For compatibility 712 713; DDRH - PORT H Data Direction Register 714.equ DDH0 = 0 ; PORT H Data Direction Register bit 0 715.equ DDH1 = 1 ; PORT H Data Direction Register bit 1 716.equ DDH2 = 2 ; PORT H Data Direction Register bit 2 717.equ DDH3 = 3 ; PORT H Data Direction Register bit 3 718.equ DDH4 = 4 ; PORT H Data Direction Register bit 4 719.equ DDH5 = 5 ; PORT H Data Direction Register bit 5 720.equ DDH6 = 6 ; PORT H Data Direction Register bit 6 721.equ DDH7 = 7 ; PORT H Data Direction Register bit 7 722 723; PINH - PORT H Input Pins 724.equ PINH0 = 0 ; PORT H Input Pins bit 0 725.equ PINH1 = 1 ; PORT H Input Pins bit 1 726.equ PINH2 = 2 ; PORT H Input Pins bit 2 727.equ PINH3 = 3 ; PORT H Input Pins bit 3 728.equ PINH4 = 4 ; PORT H Input Pins bit 4 729.equ PINH5 = 5 ; PORT H Input Pins bit 5 730.equ PINH6 = 6 ; PORT H Input Pins bit 6 731.equ PINH7 = 7 ; PORT H Input Pins bit 7 732 733 734; ***** PORTJ ************************ 735; PORTJ - PORT J Data Register 736.equ PORTJ0 = 0 ; PORT J Data Register bit 0 737.equ PJ0 = 0 ; For compatibility 738.equ PORTJ1 = 1 ; PORT J Data Register bit 1 739.equ PJ1 = 1 ; For compatibility 740.equ PORTJ2 = 2 ; PORT J Data Register bit 2 741.equ PJ2 = 2 ; For compatibility 742.equ PORTJ3 = 3 ; PORT J Data Register bit 3 743.equ PJ3 = 3 ; For compatibility 744.equ PORTJ4 = 4 ; PORT J Data Register bit 4 745.equ PJ4 = 4 ; For compatibility 746.equ PORTJ5 = 5 ; PORT J Data Register bit 5 747.equ PJ5 = 5 ; For compatibility 748.equ PORTJ6 = 6 ; PORT J Data Register bit 6 749.equ PJ6 = 6 ; For compatibility 750.equ PORTJ7 = 7 ; PORT J Data Register bit 7 751.equ PJ7 = 7 ; For compatibility 752 753; DDRJ - PORT J Data Direction Register 754.equ DDJ0 = 0 ; PORT J Data Direction Register bit 0 755.equ DDJ1 = 1 ; PORT J Data Direction Register bit 1 756.equ DDJ2 = 2 ; PORT J Data Direction Register bit 2 757.equ DDJ3 = 3 ; PORT J Data Direction Register bit 3 758.equ DDJ4 = 4 ; PORT J Data Direction Register bit 4 759.equ DDJ5 = 5 ; PORT J Data Direction Register bit 5 760.equ DDJ6 = 6 ; PORT J Data Direction Register bit 6 761.equ DDJ7 = 7 ; PORT J Data Direction Register bit 7 762 763; PINJ - PORT J Input Pins 764.equ PINJ0 = 0 ; PORT J Input Pins bit 0 765.equ PINJ1 = 1 ; PORT J Input Pins bit 1 766.equ PINJ2 = 2 ; PORT J Input Pins bit 2 767.equ PINJ3 = 3 ; PORT J Input Pins bit 3 768.equ PINJ4 = 4 ; PORT J Input Pins bit 4 769.equ PINJ5 = 5 ; PORT J Input Pins bit 5 770.equ PINJ6 = 6 ; PORT J Input Pins bit 6 771.equ PINJ7 = 7 ; PORT J Input Pins bit 7 772 773 774; ***** PORTK ************************ 775; PORTK - PORT K Data Register 776.equ PORTK0 = 0 ; PORT K Data Register bit 0 777.equ PK0 = 0 ; For compatibility 778.equ PORTK1 = 1 ; PORT K Data Register bit 1 779.equ PK1 = 1 ; For compatibility 780.equ PORTK2 = 2 ; PORT K Data Register bit 2 781.equ PK2 = 2 ; For compatibility 782.equ PORTK3 = 3 ; PORT K Data Register bit 3 783.equ PK3 = 3 ; For compatibility 784.equ PORTK4 = 4 ; PORT K Data Register bit 4 785.equ PK4 = 4 ; For compatibility 786.equ PORTK5 = 5 ; PORT K Data Register bit 5 787.equ PK5 = 5 ; For compatibility 788.equ PORTK6 = 6 ; PORT K Data Register bit 6 789.equ PK6 = 6 ; For compatibility 790.equ PORTK7 = 7 ; PORT K Data Register bit 7 791.equ PK7 = 7 ; For compatibility 792 793; DDRK - PORT K Data Direction Register 794.equ DDK0 = 0 ; PORT K Data Direction Register bit 0 795.equ DDK1 = 1 ; PORT K Data Direction Register bit 1 796.equ DDK2 = 2 ; PORT K Data Direction Register bit 2 797.equ DDK3 = 3 ; PORT K Data Direction Register bit 3 798.equ DDK4 = 4 ; PORT K Data Direction Register bit 4 799.equ DDK5 = 5 ; PORT K Data Direction Register bit 5 800.equ DDK6 = 6 ; PORT K Data Direction Register bit 6 801.equ DDK7 = 7 ; PORT K Data Direction Register bit 7 802 803; PINK - PORT K Input Pins 804.equ PINK0 = 0 ; PORT K Input Pins bit 0 805.equ PINK1 = 1 ; PORT K Input Pins bit 1 806.equ PINK2 = 2 ; PORT K Input Pins bit 2 807.equ PINK3 = 3 ; PORT K Input Pins bit 3 808.equ PINK4 = 4 ; PORT K Input Pins bit 4 809.equ PINK5 = 5 ; PORT K Input Pins bit 5 810.equ PINK6 = 6 ; PORT K Input Pins bit 6 811.equ PINK7 = 7 ; PORT K Input Pins bit 7 812 813 814; ***** PORTL ************************ 815; PORTL - PORT L Data Register 816.equ PORTL0 = 0 ; PORT L Data Register bit 0 817.equ PL0 = 0 ; For compatibility 818.equ PORTL1 = 1 ; PORT L Data Register bit 1 819.equ PL1 = 1 ; For compatibility 820.equ PORTL2 = 2 ; PORT L Data Register bit 2 821.equ PL2 = 2 ; For compatibility 822.equ PORTL3 = 3 ; PORT L Data Register bit 3 823.equ PL3 = 3 ; For compatibility 824.equ PORTL4 = 4 ; PORT L Data Register bit 4 825.equ PL4 = 4 ; For compatibility 826.equ PORTL5 = 5 ; PORT L Data Register bit 5 827.equ PL5 = 5 ; For compatibility 828.equ PORTL6 = 6 ; PORT L Data Register bit 6 829.equ PL6 = 6 ; For compatibility 830.equ PORTL7 = 7 ; PORT L Data Register bit 7 831.equ PL7 = 7 ; For compatibility 832 833; DDRL - PORT L Data Direction Register 834.equ DDL0 = 0 ; PORT L Data Direction Register bit 0 835.equ DDL1 = 1 ; PORT L Data Direction Register bit 1 836.equ DDL2 = 2 ; PORT L Data Direction Register bit 2 837.equ DDL3 = 3 ; PORT L Data Direction Register bit 3 838.equ DDL4 = 4 ; PORT L Data Direction Register bit 4 839.equ DDL5 = 5 ; PORT L Data Direction Register bit 5 840.equ DDL6 = 6 ; PORT L Data Direction Register bit 6 841.equ DDL7 = 7 ; PORT L Data Direction Register bit 7 842 843; PINL - PORT L Input Pins 844.equ PINL0 = 0 ; PORT L Input Pins bit 0 845.equ PINL1 = 1 ; PORT L Input Pins bit 1 846.equ PINL2 = 2 ; PORT L Input Pins bit 2 847.equ PINL3 = 3 ; PORT L Input Pins bit 3 848.equ PINL4 = 4 ; PORT L Input Pins bit 4 849.equ PINL5 = 5 ; PORT L Input Pins bit 5 850.equ PINL6 = 6 ; PORT L Input Pins bit 6 851.equ PINL7 = 7 ; PORT L Input Pins bit 7 852 853 854; ***** TIMER_COUNTER_0 ************** 855; TIMSK0 - Timer/Counter0 Interrupt Mask Register 856.equ TOIE0 = 0 ; Timer/Counter0 Overflow Interrupt Enable 857.equ OCIE0A = 1 ; Timer/Counter0 Output Compare Match A Interrupt Enable 858.equ OCIE0B = 2 ; Timer/Counter0 Output Compare Match B Interrupt Enable 859 860; TIFR0 - Timer/Counter0 Interrupt Flag register 861.equ TOV0 = 0 ; Timer/Counter0 Overflow Flag 862.equ OCF0A = 1 ; Timer/Counter0 Output Compare Flag 0A 863.equ OCF0B = 2 ; Timer/Counter0 Output Compare Flag 0B 864 865; TCCR0A - Timer/Counter Control Register A 866.equ WGM00 = 0 ; Waveform Generation Mode 867.equ WGM01 = 1 ; Waveform Generation Mode 868.equ COM0B0 = 4 ; Compare Output Mode, Fast PWm 869.equ COM0B1 = 5 ; Compare Output Mode, Fast PWm 870.equ COM0A0 = 6 ; Compare Output Mode, Phase Correct PWM Mode 871.equ COM0A1 = 7 ; Compare Output Mode, Phase Correct PWM Mode 872 873; TCCR0B - Timer/Counter Control Register B 874.equ CS00 = 0 ; Clock Select 875.equ CS01 = 1 ; Clock Select 876.equ CS02 = 2 ; Clock Select 877.equ WGM02 = 3 ; 878.equ FOC0B = 6 ; Force Output Compare B 879.equ FOC0A = 7 ; Force Output Compare A 880 881; TCNT0 - Timer/Counter0 882.equ TCNT0_0 = 0 ; 883.equ TCNT0_1 = 1 ; 884.equ TCNT0_2 = 2 ; 885.equ TCNT0_3 = 3 ; 886.equ TCNT0_4 = 4 ; 887.equ TCNT0_5 = 5 ; 888.equ TCNT0_6 = 6 ; 889.equ TCNT0_7 = 7 ; 890 891; OCR0A - Timer/Counter0 Output Compare Register 892.equ OCR0A_0 = 0 ; 893.equ OCR0A_1 = 1 ; 894.equ OCR0A_2 = 2 ; 895.equ OCR0A_3 = 3 ; 896.equ OCR0A_4 = 4 ; 897.equ OCR0A_5 = 5 ; 898.equ OCR0A_6 = 6 ; 899.equ OCR0A_7 = 7 ; 900 901; OCR0B - Timer/Counter0 Output Compare Register 902.equ OCR0B_0 = 0 ; 903.equ OCR0B_1 = 1 ; 904.equ OCR0B_2 = 2 ; 905.equ OCR0B_3 = 3 ; 906.equ OCR0B_4 = 4 ; 907.equ OCR0B_5 = 5 ; 908.equ OCR0B_6 = 6 ; 909.equ OCR0B_7 = 7 ; 910 911; GTCCR - General Timer/Counter Control Register 912.equ PSRSYNC = 0 ; Prescaler Reset Timer/Counter1 and Timer/Counter0 913.equ PSR10 = PSRSYNC ; For compatibility 914.equ TSM = 7 ; Timer/Counter Synchronization Mode 915 916 917; ***** TIMER_COUNTER_2 ************** 918; TIMSK2 - Timer/Counter Interrupt Mask register 919.equ TOIE2 = 0 ; Timer/Counter2 Overflow Interrupt Enable 920.equ TOIE2A = TOIE2 ; For compatibility 921.equ OCIE2A = 1 ; Timer/Counter2 Output Compare Match A Interrupt Enable 922.equ OCIE2B = 2 ; Timer/Counter2 Output Compare Match B Interrupt Enable 923 924; TIFR2 - Timer/Counter Interrupt Flag Register 925.equ TOV2 = 0 ; Timer/Counter2 Overflow Flag 926.equ OCF2A = 1 ; Output Compare Flag 2A 927.equ OCF2B = 2 ; Output Compare Flag 2B 928 929; TCCR2A - Timer/Counter2 Control Register A 930.equ WGM20 = 0 ; Waveform Genration Mode 931.equ WGM21 = 1 ; Waveform Genration Mode 932.equ COM2B0 = 4 ; Compare Output Mode bit 0 933.equ COM2B1 = 5 ; Compare Output Mode bit 1 934.equ COM2A0 = 6 ; Compare Output Mode bit 1 935.equ COM2A1 = 7 ; Compare Output Mode bit 1 936 937; TCCR2B - Timer/Counter2 Control Register B 938.equ CS20 = 0 ; Clock Select bit 0 939.equ CS21 = 1 ; Clock Select bit 1 940.equ CS22 = 2 ; Clock Select bit 2 941.equ WGM22 = 3 ; Waveform Generation Mode 942.equ FOC2B = 6 ; Force Output Compare B 943.equ FOC2A = 7 ; Force Output Compare A 944 945; TCNT2 - Timer/Counter2 946.equ TCNT2_0 = 0 ; Timer/Counter 2 bit 0 947.equ TCNT2_1 = 1 ; Timer/Counter 2 bit 1 948.equ TCNT2_2 = 2 ; Timer/Counter 2 bit 2 949.equ TCNT2_3 = 3 ; Timer/Counter 2 bit 3 950.equ TCNT2_4 = 4 ; Timer/Counter 2 bit 4 951.equ TCNT2_5 = 5 ; Timer/Counter 2 bit 5 952.equ TCNT2_6 = 6 ; Timer/Counter 2 bit 6 953.equ TCNT2_7 = 7 ; Timer/Counter 2 bit 7 954 955; OCR2A - Timer/Counter2 Output Compare Register A 956.equ OCR2A_0 = 0 ; Timer/Counter2 Output Compare Register Bit 0 957.equ OCR2A_1 = 1 ; Timer/Counter2 Output Compare Register Bit 1 958.equ OCR2A_2 = 2 ; Timer/Counter2 Output Compare Register Bit 2 959.equ OCR2A_3 = 3 ; Timer/Counter2 Output Compare Register Bit 3 960.equ OCR2A_4 = 4 ; Timer/Counter2 Output Compare Register Bit 4 961.equ OCR2A_5 = 5 ; Timer/Counter2 Output Compare Register Bit 5 962.equ OCR2A_6 = 6 ; Timer/Counter2 Output Compare Register Bit 6 963.equ OCR2A_7 = 7 ; Timer/Counter2 Output Compare Register Bit 7 964 965; OCR2B - Timer/Counter2 Output Compare Register B 966.equ OCR2B_0 = 0 ; Timer/Counter2 Output Compare Register Bit 0 967.equ OCR2B_1 = 1 ; Timer/Counter2 Output Compare Register Bit 1 968.equ OCR2B_2 = 2 ; Timer/Counter2 Output Compare Register Bit 2 969.equ OCR2B_3 = 3 ; Timer/Counter2 Output Compare Register Bit 3 970.equ OCR2B_4 = 4 ; Timer/Counter2 Output Compare Register Bit 4 971.equ OCR2B_5 = 5 ; Timer/Counter2 Output Compare Register Bit 5 972.equ OCR2B_6 = 6 ; Timer/Counter2 Output Compare Register Bit 6 973.equ OCR2B_7 = 7 ; Timer/Counter2 Output Compare Register Bit 7 974 975; ASSR - Asynchronous Status Register 976.equ TCR2BUB = 0 ; Timer/Counter Control Register2 Update Busy 977.equ TCR2AUB = 1 ; Timer/Counter Control Register2 Update Busy 978.equ OCR2BUB = 2 ; Output Compare Register 2 Update Busy 979.equ OCR2AUB = 3 ; Output Compare Register2 Update Busy 980.equ TCN2UB = 4 ; Timer/Counter2 Update Busy 981.equ AS2 = 5 ; Asynchronous Timer/Counter2 982.equ EXCLK = 6 ; Enable External Clock Input 983 984; GTCCR - General Timer Counter Control register 985.equ PSRASY = 1 ; Prescaler Reset Timer/Counter2 986.equ PSR2 = PSRASY ; For compatibility 987;.equ TSM = 7 ; Timer/Counter Synchronization Mode 988 989 990; ***** WATCHDOG ********************* 991; WDTCSR - Watchdog Timer Control Register 992.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0 993.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1 994.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2 995.equ WDE = 3 ; Watch Dog Enable 996.equ WDCE = 4 ; Watchdog Change Enable 997.equ WDP3 = 5 ; Watchdog Timer Prescaler Bit 3 998.equ WDIE = 6 ; Watchdog Timeout Interrupt Enable 999.equ WDIF = 7 ; Watchdog Timeout Interrupt Flag 1000 1001 1002; ***** USART1 *********************** 1003; UDR1 - USART I/O Data Register 1004.equ UDR1_0 = 0 ; USART I/O Data Register bit 0 1005.equ UDR1_1 = 1 ; USART I/O Data Register bit 1 1006.equ UDR1_2 = 2 ; USART I/O Data Register bit 2 1007.equ UDR1_3 = 3 ; USART I/O Data Register bit 3 1008.equ UDR1_4 = 4 ; USART I/O Data Register bit 4 1009.equ UDR1_5 = 5 ; USART I/O Data Register bit 5 1010.equ UDR1_6 = 6 ; USART I/O Data Register bit 6 1011.equ UDR1_7 = 7 ; USART I/O Data Register bit 7 1012 1013; UCSR1A - USART Control and Status Register A 1014.equ MPCM1 = 0 ; Multi-processor Communication Mode 1015.equ U2X1 = 1 ; Double the USART transmission speed 1016.equ UPE1 = 2 ; Parity Error 1017.equ DOR1 = 3 ; Data overRun 1018.equ FE1 = 4 ; Framing Error 1019.equ UDRE1 = 5 ; USART Data Register Empty 1020.equ TXC1 = 6 ; USART Transmitt Complete 1021.equ RXC1 = 7 ; USART Receive Complete 1022 1023; UCSR1B - USART Control and Status Register B 1024.equ TXB81 = 0 ; Transmit Data Bit 8 1025.equ RXB81 = 1 ; Receive Data Bit 8 1026.equ UCSZ12 = 2 ; Character Size 1027.equ TXEN1 = 3 ; Transmitter Enable 1028.equ RXEN1 = 4 ; Receiver Enable 1029.equ UDRIE1 = 5 ; USART Data register Empty Interrupt Enable 1030.equ TXCIE1 = 6 ; TX Complete Interrupt Enable 1031.equ RXCIE1 = 7 ; RX Complete Interrupt Enable 1032 1033; UCSR1C - USART Control and Status Register C 1034.equ UCPOL1 = 0 ; Clock Polarity 1035.equ UCSZ10 = 1 ; Character Size 1036.equ UCPHA1 = UCSZ10 ; For compatibility 1037.equ UCSZ11 = 2 ; Character Size 1038.equ UDORD1 = UCSZ11 ; For compatibility 1039.equ USBS1 = 3 ; Stop Bit Select 1040.equ UPM10 = 4 ; Parity Mode Bit 0 1041.equ UPM11 = 5 ; Parity Mode Bit 1 1042.equ UMSEL10 = 6 ; USART Mode Select 1043.equ UMSEL11 = 7 ; USART Mode Select 1044 1045; UBRR1H - USART Baud Rate Register High Byte 1046.equ UBRR_8 = 0 ; USART Baud Rate Register bit 8 1047.equ UBRR_9 = 1 ; USART Baud Rate Register bit 9 1048.equ UBRR_10 = 2 ; USART Baud Rate Register bit 10 1049.equ UBRR_11 = 3 ; USART Baud Rate Register bit 11 1050 1051; UBRR1L - USART Baud Rate Register Low Byte 1052.equ UBRR_0 = 0 ; USART Baud Rate Register bit 0 1053.equ UBRR_1 = 1 ; USART Baud Rate Register bit 1 1054.equ UBRR_2 = 2 ; USART Baud Rate Register bit 2 1055.equ UBRR_3 = 3 ; USART Baud Rate Register bit 3 1056.equ UBRR_4 = 4 ; USART Baud Rate Register bit 4 1057.equ UBRR_5 = 5 ; USART Baud Rate Register bit 5 1058.equ UBRR_6 = 6 ; USART Baud Rate Register bit 6 1059.equ UBRR_7 = 7 ; USART Baud Rate Register bit 7 1060 1061 1062; ***** EEPROM *********************** 1063; EEARH - EEPROM Address Register Low Byte 1064.equ EEAR8 = 0 ; EEPROM Read/Write Access Bit 8 1065.equ EEAR9 = 1 ; EEPROM Read/Write Access Bit 9 1066.equ EEAR10 = 2 ; EEPROM Read/Write Access Bit 10 1067.equ EEAR11 = 3 ; EEPROM Read/Write Access Bit 11 1068 1069; EEARL - EEPROM Address Register Low Byte 1070.equ EEAR0 = 0 ; EEPROM Read/Write Access Bit 0 1071.equ EEAR1 = 1 ; EEPROM Read/Write Access Bit 1 1072.equ EEAR2 = 2 ; EEPROM Read/Write Access Bit 2 1073.equ EEAR3 = 3 ; EEPROM Read/Write Access Bit 3 1074.equ EEAR4 = 4 ; EEPROM Read/Write Access Bit 4 1075.equ EEAR5 = 5 ; EEPROM Read/Write Access Bit 5 1076.equ EEAR6 = 6 ; EEPROM Read/Write Access Bit 6 1077.equ EEAR7 = 7 ; EEPROM Read/Write Access Bit 7 1078 1079; EEDR - EEPROM Data Register 1080.equ EEDR0 = 0 ; EEPROM Data Register bit 0 1081.equ EEDR1 = 1 ; EEPROM Data Register bit 1 1082.equ EEDR2 = 2 ; EEPROM Data Register bit 2 1083.equ EEDR3 = 3 ; EEPROM Data Register bit 3 1084.equ EEDR4 = 4 ; EEPROM Data Register bit 4 1085.equ EEDR5 = 5 ; EEPROM Data Register bit 5 1086.equ EEDR6 = 6 ; EEPROM Data Register bit 6 1087.equ EEDR7 = 7 ; EEPROM Data Register bit 7 1088 1089; EECR - EEPROM Control Register 1090.equ EERE = 0 ; EEPROM Read Enable 1091.equ EEPE = 1 ; EEPROM Write Enable 1092.equ EEMPE = 2 ; EEPROM Master Write Enable 1093.equ EERIE = 3 ; EEPROM Ready Interrupt Enable 1094.equ EEPM0 = 4 ; EEPROM Programming Mode Bit 0 1095.equ EEPM1 = 5 ; EEPROM Programming Mode Bit 1 1096 1097 1098; ***** TIMER_COUNTER_5 ************** 1099; TIMSK5 - Timer/Counter5 Interrupt Mask Register 1100.equ TOIE5 = 0 ; Timer/Counter5 Overflow Interrupt Enable 1101.equ OCIE5A = 1 ; Timer/Counter5 Output Compare A Match Interrupt Enable 1102.equ OCIE5B = 2 ; Timer/Counter5 Output Compare B Match Interrupt Enable 1103.equ OCIE5C = 3 ; Timer/Counter5 Output Compare C Match Interrupt Enable 1104.equ ICIE5 = 5 ; Timer/Counter5 Input Capture Interrupt Enable 1105 1106; TIFR5 - Timer/Counter5 Interrupt Flag register 1107.equ TOV5 = 0 ; Timer/Counter5 Overflow Flag 1108.equ OCF5A = 1 ; Output Compare Flag 5A 1109.equ OCF5B = 2 ; Output Compare Flag 5B 1110.equ OCF5C = 3 ; Output Compare Flag 5C 1111.equ ICF5 = 5 ; Input Capture Flag 5 1112 1113; TCCR5A - Timer/Counter5 Control Register A 1114.equ WGM50 = 0 ; Waveform Generation Mode 1115.equ WGM51 = 1 ; Waveform Generation Mode 1116.equ COM5C0 = 2 ; Compare Output Mode 5C, bit 0 1117.equ COM5C1 = 3 ; Compare Output Mode 5C, bit 1 1118.equ COM5B0 = 4 ; Compare Output Mode 5B, bit 0 1119.equ COM5B1 = 5 ; Compare Output Mode 5B, bit 1 1120.equ COM5A0 = 6 ; Compare Output Mode 5A, bit 0 1121.equ COM5A1 = 7 ; Compare Output Mode 1A, bit 1 1122 1123; TCCR5B - Timer/Counter5 Control Register B 1124.equ CS50 = 0 ; Prescaler source of Timer/Counter 5 1125.equ CS51 = 1 ; Prescaler source of Timer/Counter 5 1126.equ CS52 = 2 ; Prescaler source of Timer/Counter 5 1127.equ WGM52 = 3 ; Waveform Generation Mode 1128.equ WGM53 = 4 ; Waveform Generation Mode 1129.equ ICES5 = 6 ; Input Capture 5 Edge Select 1130.equ ICNC5 = 7 ; Input Capture 5 Noise Canceler 1131 1132; TCCR5C - Timer/Counter 5 Control Register C 1133.equ FOC5C = 5 ; Force Output Compare 5C 1134.equ FOC5B = 6 ; Force Output Compare 5B 1135.equ FOC5A = 7 ; Force Output Compare 5A 1136 1137; ICR5H - Timer/Counter5 Input Capture Register High Byte 1138.equ ICR5H0 = 0 ; Timer/Counter5 Input Capture Register High Byte bit 0 1139.equ ICR5H1 = 1 ; Timer/Counter5 Input Capture Register High Byte bit 1 1140.equ ICR5H2 = 2 ; Timer/Counter5 Input Capture Register High Byte bit 2 1141.equ ICR5H3 = 3 ; Timer/Counter5 Input Capture Register High Byte bit 3 1142.equ ICR5H4 = 4 ; Timer/Counter5 Input Capture Register High Byte bit 4 1143.equ ICR5H5 = 5 ; Timer/Counter5 Input Capture Register High Byte bit 5 1144.equ ICR5H6 = 6 ; Timer/Counter5 Input Capture Register High Byte bit 6 1145.equ ICR5H7 = 7 ; Timer/Counter5 Input Capture Register High Byte bit 7 1146 1147; ICR5L - Timer/Counter5 Input Capture Register Low Byte 1148.equ ICR5L0 = 0 ; Timer/Counter5 Input Capture Register Low Byte bit 0 1149.equ ICR5L1 = 1 ; Timer/Counter5 Input Capture Register Low Byte bit 1 1150.equ ICR5L2 = 2 ; Timer/Counter5 Input Capture Register Low Byte bit 2 1151.equ ICR5L3 = 3 ; Timer/Counter5 Input Capture Register Low Byte bit 3 1152.equ ICR5L4 = 4 ; Timer/Counter5 Input Capture Register Low Byte bit 4 1153.equ ICR5L5 = 5 ; Timer/Counter5 Input Capture Register Low Byte bit 5 1154.equ ICR5L6 = 6 ; Timer/Counter5 Input Capture Register Low Byte bit 6 1155.equ ICR5L7 = 7 ; Timer/Counter5 Input Capture Register Low Byte bit 7 1156 1157 1158; ***** TIMER_COUNTER_4 ************** 1159; TIMSK4 - Timer/Counter4 Interrupt Mask Register 1160.equ TOIE4 = 0 ; Timer/Counter4 Overflow Interrupt Enable 1161.equ OCIE4A = 1 ; Timer/Counter4 Output Compare A Match Interrupt Enable 1162.equ OCIE4B = 2 ; Timer/Counter4 Output Compare B Match Interrupt Enable 1163.equ OCIE4C = 3 ; Timer/Counter4 Output Compare C Match Interrupt Enable 1164.equ ICIE4 = 5 ; Timer/Counter4 Input Capture Interrupt Enable 1165 1166; TIFR4 - Timer/Counter4 Interrupt Flag register 1167.equ TOV4 = 0 ; Timer/Counter4 Overflow Flag 1168.equ OCF4A = 1 ; Output Compare Flag 4A 1169.equ OCF4B = 2 ; Output Compare Flag 4B 1170.equ OCF4C = 3 ; Output Compare Flag 4C 1171.equ ICF4 = 5 ; Input Capture Flag 4 1172 1173; TCCR4A - Timer/Counter4 Control Register A 1174.equ WGM40 = 0 ; Waveform Generation Mode 1175.equ WGM41 = 1 ; Waveform Generation Mode 1176.equ COM4C0 = 2 ; Compare Output Mode 4C, bit 0 1177.equ COM4C1 = 3 ; Compare Output Mode 4C, bit 1 1178.equ COM4B0 = 4 ; Compare Output Mode 4B, bit 0 1179.equ COM4B1 = 5 ; Compare Output Mode 4B, bit 1 1180.equ COM4A0 = 6 ; Compare Output Mode 4A, bit 0 1181.equ COM4A1 = 7 ; Compare Output Mode 1A, bit 1 1182 1183; TCCR4B - Timer/Counter4 Control Register B 1184.equ CS40 = 0 ; Prescaler source of Timer/Counter 4 1185.equ CS41 = 1 ; Prescaler source of Timer/Counter 4 1186.equ CS42 = 2 ; Prescaler source of Timer/Counter 4 1187.equ WGM42 = 3 ; Waveform Generation Mode 1188.equ WGM43 = 4 ; Waveform Generation Mode 1189.equ ICES4 = 6 ; Input Capture 4 Edge Select 1190.equ ICNC4 = 7 ; Input Capture 4 Noise Canceler 1191 1192; TCCR4C - Timer/Counter 4 Control Register C 1193.equ FOC4C = 5 ; Force Output Compare 4C 1194.equ FOC4B = 6 ; Force Output Compare 4B 1195.equ FOC4A = 7 ; Force Output Compare 4A 1196 1197 1198; ***** TIMER_COUNTER_3 ************** 1199; TIMSK3 - Timer/Counter3 Interrupt Mask Register 1200.equ TOIE3 = 0 ; Timer/Counter3 Overflow Interrupt Enable 1201.equ OCIE3A = 1 ; Timer/Counter3 Output Compare A Match Interrupt Enable 1202.equ OCIE3B = 2 ; Timer/Counter3 Output Compare B Match Interrupt Enable 1203.equ OCIE3C = 3 ; Timer/Counter3 Output Compare C Match Interrupt Enable 1204.equ ICIE3 = 5 ; Timer/Counter3 Input Capture Interrupt Enable 1205 1206; TIFR3 - Timer/Counter3 Interrupt Flag register 1207.equ TOV3 = 0 ; Timer/Counter3 Overflow Flag 1208.equ OCF3A = 1 ; Output Compare Flag 3A 1209.equ OCF3B = 2 ; Output Compare Flag 3B 1210.equ OCF3C = 3 ; Output Compare Flag 3C 1211.equ ICF3 = 5 ; Input Capture Flag 3 1212 1213; TCCR3A - Timer/Counter3 Control Register A 1214.equ WGM30 = 0 ; Waveform Generation Mode 1215.equ WGM31 = 1 ; Waveform Generation Mode 1216.equ COM3C0 = 2 ; Compare Output Mode 3C, bit 0 1217.equ COM3C1 = 3 ; Compare Output Mode 3C, bit 1 1218.equ COM3B0 = 4 ; Compare Output Mode 3B, bit 0 1219.equ COM3B1 = 5 ; Compare Output Mode 3B, bit 1 1220.equ COM3A0 = 6 ; Compare Output Mode 3A, bit 0 1221.equ COM3A1 = 7 ; Compare Output Mode 1A, bit 1 1222 1223; TCCR3B - Timer/Counter3 Control Register B 1224.equ CS30 = 0 ; Prescaler source of Timer/Counter 3 1225.equ CS31 = 1 ; Prescaler source of Timer/Counter 3 1226.equ CS32 = 2 ; Prescaler source of Timer/Counter 3 1227.equ WGM32 = 3 ; Waveform Generation Mode 1228.equ WGM33 = 4 ; Waveform Generation Mode 1229.equ ICES3 = 6 ; Input Capture 3 Edge Select 1230.equ ICNC3 = 7 ; Input Capture 3 Noise Canceler 1231 1232; TCCR3C - Timer/Counter 3 Control Register C 1233.equ FOC3C = 5 ; Force Output Compare 3C 1234.equ FOC3B = 6 ; Force Output Compare 3B 1235.equ FOC3A = 7 ; Force Output Compare 3A 1236 1237 1238; ***** TIMER_COUNTER_1 ************** 1239; TIMSK1 - Timer/Counter1 Interrupt Mask Register 1240.equ TOIE1 = 0 ; Timer/Counter1 Overflow Interrupt Enable 1241.equ OCIE1A = 1 ; Timer/Counter1 Output Compare A Match Interrupt Enable 1242.equ OCIE1B = 2 ; Timer/Counter1 Output Compare B Match Interrupt Enable 1243.equ OCIE1C = 3 ; Timer/Counter1 Output Compare C Match Interrupt Enable 1244.equ ICIE1 = 5 ; Timer/Counter1 Input Capture Interrupt Enable 1245 1246; TIFR1 - Timer/Counter1 Interrupt Flag register 1247.equ TOV1 = 0 ; Timer/Counter1 Overflow Flag 1248.equ OCF1A = 1 ; Output Compare Flag 1A 1249.equ OCF1B = 2 ; Output Compare Flag 1B 1250.equ OCF1C = 3 ; Output Compare Flag 1C 1251.equ ICF1 = 5 ; Input Capture Flag 1 1252 1253; TCCR1A - Timer/Counter1 Control Register A 1254.equ WGM10 = 0 ; Waveform Generation Mode 1255.equ WGM11 = 1 ; Waveform Generation Mode 1256.equ COM1C0 = 2 ; Compare Output Mode 1C, bit 0 1257.equ COM1C1 = 3 ; Compare Output Mode 1C, bit 1 1258.equ COM1B0 = 4 ; Compare Output Mode 1B, bit 0 1259.equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1 1260.equ COM1A0 = 6 ; Compare Output Mode 1A, bit 0 1261.equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1 1262 1263; TCCR1B - Timer/Counter1 Control Register B 1264.equ CS10 = 0 ; Prescaler source of Timer/Counter 1 1265.equ CS11 = 1 ; Prescaler source of Timer/Counter 1 1266.equ CS12 = 2 ; Prescaler source of Timer/Counter 1 1267.equ WGM12 = 3 ; Waveform Generation Mode 1268.equ WGM13 = 4 ; Waveform Generation Mode 1269.equ ICES1 = 6 ; Input Capture 1 Edge Select 1270.equ ICNC1 = 7 ; Input Capture 1 Noise Canceler 1271 1272; TCCR1C - Timer/Counter 1 Control Register C 1273.equ FOC1C = 5 ; Force Output Compare 1C 1274.equ FOC1B = 6 ; Force Output Compare 1B 1275.equ FOC1A = 7 ; Force Output Compare 1A 1276 1277 1278; ***** JTAG ************************* 1279; OCDR - On-Chip Debug Related Register in I/O Memory 1280.equ OCDR0 = 0 ; On-Chip Debug Register Bit 0 1281.equ OCDR1 = 1 ; On-Chip Debug Register Bit 1 1282.equ OCDR2 = 2 ; On-Chip Debug Register Bit 2 1283.equ OCDR3 = 3 ; On-Chip Debug Register Bit 3 1284.equ OCDR4 = 4 ; On-Chip Debug Register Bit 4 1285.equ OCDR5 = 5 ; On-Chip Debug Register Bit 5 1286.equ OCDR6 = 6 ; On-Chip Debug Register Bit 6 1287.equ OCDR7 = 7 ; On-Chip Debug Register Bit 7 1288.equ IDRD = OCDR7 ; For compatibility 1289 1290; MCUCR - MCU Control Register 1291.equ JTD = 7 ; JTAG Interface Disable 1292 1293; MCUSR - MCU Status Register 1294.equ JTRF = 4 ; JTAG Reset Flag 1295 1296 1297; ***** EXTERNAL_INTERRUPT *********** 1298; EICRA - External Interrupt Control Register A 1299.equ ISC00 = 0 ; External Interrupt Sense Control Bit 1300.equ ISC01 = 1 ; External Interrupt Sense Control Bit 1301.equ ISC10 = 2 ; External Interrupt Sense Control Bit 1302.equ ISC11 = 3 ; External Interrupt Sense Control Bit 1303.equ ISC20 = 4 ; External Interrupt Sense Control Bit 1304.equ ISC21 = 5 ; External Interrupt Sense Control Bit 1305.equ ISC30 = 6 ; External Interrupt Sense Control Bit 1306.equ ISC31 = 7 ; External Interrupt Sense Control Bit 1307 1308; EICRB - External Interrupt Control Register B 1309.equ ISC40 = 0 ; External Interrupt 7-4 Sense Control Bit 1310.equ ISC41 = 1 ; External Interrupt 7-4 Sense Control Bit 1311.equ ISC50 = 2 ; External Interrupt 7-4 Sense Control Bit 1312.equ ISC51 = 3 ; External Interrupt 7-4 Sense Control Bit 1313.equ ISC60 = 4 ; External Interrupt 7-4 Sense Control Bit 1314.equ ISC61 = 5 ; External Interrupt 7-4 Sense Control Bit 1315.equ ISC70 = 6 ; External Interrupt 7-4 Sense Control Bit 1316.equ ISC71 = 7 ; External Interrupt 7-4 Sense Control Bit 1317 1318; EIMSK - External Interrupt Mask Register 1319.equ INT0 = 0 ; External Interrupt Request 0 Enable 1320.equ INT1 = 1 ; External Interrupt Request 1 Enable 1321.equ INT2 = 2 ; External Interrupt Request 2 Enable 1322.equ INT3 = 3 ; External Interrupt Request 3 Enable 1323.equ INT4 = 4 ; External Interrupt Request 4 Enable 1324.equ INT5 = 5 ; External Interrupt Request 5 Enable 1325.equ INT6 = 6 ; External Interrupt Request 6 Enable 1326.equ INT7 = 7 ; External Interrupt Request 7 Enable 1327 1328; EIFR - External Interrupt Flag Register 1329.equ INTF0 = 0 ; External Interrupt Flag 0 1330.equ INTF1 = 1 ; External Interrupt Flag 1 1331.equ INTF2 = 2 ; External Interrupt Flag 2 1332.equ INTF3 = 3 ; External Interrupt Flag 3 1333.equ INTF4 = 4 ; External Interrupt Flag 4 1334.equ INTF5 = 5 ; External Interrupt Flag 5 1335.equ INTF6 = 6 ; External Interrupt Flag 6 1336.equ INTF7 = 7 ; External Interrupt Flag 7 1337 1338; PCICR - Pin Change Interrupt Control Register 1339.equ PCIE0 = 0 ; Pin Change Interrupt Enable 0 1340.equ PCIE1 = 1 ; Pin Change Interrupt Enable 1 1341.equ PCIE2 = 2 ; Pin Change Interrupt Enable 2 1342 1343; PCIFR - Pin Change Interrupt Flag Register 1344.equ PCIF0 = 0 ; Pin Change Interrupt Flag 0 1345.equ PCIF1 = 1 ; Pin Change Interrupt Flag 1 1346.equ PCIF2 = 2 ; Pin Change Interrupt Flag 2 1347 1348; PCMSK2 - Pin Change Mask Register 2 1349.equ PCINT16 = 0 ; Pin Change Enable Mask 16 1350.equ PCINT17 = 1 ; Pin Change Enable Mask 17 1351.equ PCINT18 = 2 ; Pin Change Enable Mask 18 1352.equ PCINT19 = 3 ; Pin Change Enable Mask 19 1353.equ PCINT20 = 4 ; Pin Change Enable Mask 20 1354.equ PCINT21 = 5 ; Pin Change Enable Mask 21 1355.equ PCINT22 = 6 ; Pin Change Enable Mask 22 1356.equ PCINT23 = 7 ; Pin Change Enable Mask 23 1357 1358; PCMSK1 - Pin Change Mask Register 1 1359.equ PCINT8 = 0 ; Pin Change Enable Mask 8 1360.equ PCINT9 = 1 ; Pin Change Enable Mask 9 1361.equ PCINT10 = 2 ; Pin Change Enable Mask 10 1362.equ PCINT11 = 3 ; Pin Change Enable Mask 11 1363.equ PCINT12 = 4 ; Pin Change Enable Mask 12 1364.equ PCINT13 = 5 ; Pin Change Enable Mask 13 1365.equ PCINT14 = 6 ; Pin Change Enable Mask 14 1366.equ PCINT15 = 7 ; Pin Change Enable Mask 15 1367 1368; PCMSK0 - Pin Change Mask Register 0 1369.equ PCINT0 = 0 ; Pin Change Enable Mask 0 1370.equ PCINT1 = 1 ; Pin Change Enable Mask 1 1371.equ PCINT2 = 2 ; Pin Change Enable Mask 2 1372.equ PCINT3 = 3 ; Pin Change Enable Mask 3 1373.equ PCINT4 = 4 ; Pin Change Enable Mask 4 1374.equ PCINT5 = 5 ; Pin Change Enable Mask 5 1375.equ PCINT6 = 6 ; Pin Change Enable Mask 6 1376.equ PCINT7 = 7 ; Pin Change Enable Mask 7 1377 1378 1379; ***** CPU ************************** 1380; SREG - Status Register 1381.equ SREG_C = 0 ; Carry Flag 1382.equ SREG_Z = 1 ; Zero Flag 1383.equ SREG_N = 2 ; Negative Flag 1384.equ SREG_V = 3 ; Two's Complement Overflow Flag 1385.equ SREG_S = 4 ; Sign Bit 1386.equ SREG_H = 5 ; Half Carry Flag 1387.equ SREG_T = 6 ; Bit Copy Storage 1388.equ SREG_I = 7 ; Global Interrupt Enable 1389 1390; MCUCR - MCU Control Register 1391.equ IVCE = 0 ; Interrupt Vector Change Enable 1392.equ IVSEL = 1 ; Interrupt Vector Select 1393.equ PUD = 4 ; Pull-up disable 1394;.equ JTD = 7 ; JTAG Interface Disable 1395 1396; MCUSR - MCU Status Register 1397.equ PORF = 0 ; Power-on reset flag 1398.equ EXTRF = 1 ; External Reset Flag 1399.equ BORF = 2 ; Brown-out Reset Flag 1400.equ WDRF = 3 ; Watchdog Reset Flag 1401;.equ JTRF = 4 ; JTAG Reset Flag 1402 1403; XMCRA - External Memory Control Register A 1404.equ SRW00 = 0 ; Wait state select bit lower page 1405.equ SRW01 = 1 ; Wait state select bit lower page 1406.equ SRW10 = 2 ; Wait state select bit upper page 1407.equ SRW11 = 3 ; Wait state select bit upper page 1408.equ SRL0 = 4 ; Wait state page limit 1409.equ SRL1 = 5 ; Wait state page limit 1410.equ SRL2 = 6 ; Wait state page limit 1411.equ SRE = 7 ; External SRAM Enable 1412 1413; XMCRB - External Memory Control Register B 1414.equ XMM0 = 0 ; External Memory High Mask 1415.equ XMM1 = 1 ; External Memory High Mask 1416.equ XMM2 = 2 ; External Memory High Mask 1417.equ XMBK = 7 ; External Memory Bus Keeper Enable 1418 1419; OSCCAL - Oscillator Calibration Value 1420.equ CAL0 = 0 ; Oscillator Calibration Value Bit0 1421.equ CAL1 = 1 ; Oscillator Calibration Value Bit1 1422.equ CAL2 = 2 ; Oscillator Calibration Value Bit2 1423.equ CAL3 = 3 ; Oscillator Calibration Value Bit3 1424.equ CAL4 = 4 ; Oscillator Calibration Value Bit4 1425.equ CAL5 = 5 ; Oscillator Calibration Value Bit5 1426.equ CAL6 = 6 ; Oscillator Calibration Value Bit6 1427.equ CAL7 = 7 ; Oscillator Calibration Value Bit7 1428 1429; CLKPR - 1430.equ CLKPS0 = 0 ; 1431.equ CLKPS1 = 1 ; 1432.equ CLKPS2 = 2 ; 1433.equ CLKPS3 = 3 ; 1434.equ CLKPCE = 7 ; 1435 1436; SMCR - Sleep Mode Control Register 1437.equ SE = 0 ; Sleep Enable 1438.equ SM0 = 1 ; Sleep Mode Select bit 0 1439.equ SM1 = 2 ; Sleep Mode Select bit 1 1440.equ SM2 = 3 ; Sleep Mode Select bit 2 1441 1442; RAMPZ - RAM Page Z Select Register 1443.equ RAMPZ0 = 0 ; RAM Page Z Select Register Bit 0 1444.equ RAMPZ1 = 1 ; RAM Page Z Select Register Bit 1 1445 1446; EIND - Extended Indirect Register 1447.equ EIND0 = 0 ; Bit 0 1448 1449; GPIOR2 - General Purpose IO Register 2 1450.equ GPIOR20 = 0 ; General Purpose IO Register 2 bit 0 1451.equ GPIOR21 = 1 ; General Purpose IO Register 2 bit 1 1452.equ GPIOR22 = 2 ; General Purpose IO Register 2 bit 2 1453.equ GPIOR23 = 3 ; General Purpose IO Register 2 bit 3 1454.equ GPIOR24 = 4 ; General Purpose IO Register 2 bit 4 1455.equ GPIOR25 = 5 ; General Purpose IO Register 2 bit 5 1456.equ GPIOR26 = 6 ; General Purpose IO Register 2 bit 6 1457.equ GPIOR27 = 7 ; General Purpose IO Register 2 bit 7 1458 1459; GPIOR1 - General Purpose IO Register 1 1460.equ GPIOR10 = 0 ; General Purpose IO Register 1 bit 0 1461.equ GPIOR11 = 1 ; General Purpose IO Register 1 bit 1 1462.equ GPIOR12 = 2 ; General Purpose IO Register 1 bit 2 1463.equ GPIOR13 = 3 ; General Purpose IO Register 1 bit 3 1464.equ GPIOR14 = 4 ; General Purpose IO Register 1 bit 4 1465.equ GPIOR15 = 5 ; General Purpose IO Register 1 bit 5 1466.equ GPIOR16 = 6 ; General Purpose IO Register 1 bit 6 1467.equ GPIOR17 = 7 ; General Purpose IO Register 1 bit 7 1468 1469; GPIOR0 - General Purpose IO Register 0 1470.equ GPIOR00 = 0 ; General Purpose IO Register 0 bit 0 1471.equ GPIOR01 = 1 ; General Purpose IO Register 0 bit 1 1472.equ GPIOR02 = 2 ; General Purpose IO Register 0 bit 2 1473.equ GPIOR03 = 3 ; General Purpose IO Register 0 bit 3 1474.equ GPIOR04 = 4 ; General Purpose IO Register 0 bit 4 1475.equ GPIOR05 = 5 ; General Purpose IO Register 0 bit 5 1476.equ GPIOR06 = 6 ; General Purpose IO Register 0 bit 6 1477.equ GPIOR07 = 7 ; General Purpose IO Register 0 bit 7 1478 1479; PRR1 - Power Reduction Register1 1480.equ PRUSART1 = 0 ; Power Reduction USART1 1481.equ PRUSART2 = 1 ; Power Reduction USART2 1482.equ PRUSART3 = 2 ; Power Reduction USART3 1483.equ PRTIM3 = 3 ; Power Reduction Timer/Counter3 1484.equ PRTIM4 = 4 ; Power Reduction Timer/Counter4 1485.equ PRTIM5 = 5 ; Power Reduction Timer/Counter5 1486 1487; PRR0 - Power Reduction Register0 1488.equ PRADC = 0 ; Power Reduction ADC 1489.equ PRUSART0 = 1 ; Power Reduction USART 1490.equ PRSPI = 2 ; Power Reduction Serial Peripheral Interface 1491.equ PRTIM1 = 3 ; Power Reduction Timer/Counter1 1492.equ PRTIM0 = 5 ; Power Reduction Timer/Counter0 1493.equ PRTIM2 = 6 ; Power Reduction Timer/Counter2 1494.equ PRTWI = 7 ; Power Reduction TWI 1495 1496 1497; ***** AD_CONVERTER ***************** 1498; ADMUX - The ADC multiplexer Selection Register 1499.equ MUX0 = 0 ; Analog Channel and Gain Selection Bits 1500.equ MUX1 = 1 ; Analog Channel and Gain Selection Bits 1501.equ MUX2 = 2 ; Analog Channel and Gain Selection Bits 1502.equ MUX3 = 3 ; Analog Channel and Gain Selection Bits 1503.equ MUX4 = 4 ; Analog Channel and Gain Selection Bits 1504.equ ADLAR = 5 ; Left Adjust Result 1505.equ REFS0 = 6 ; Reference Selection Bit 0 1506.equ REFS1 = 7 ; Reference Selection Bit 1 1507 1508; ADCSRA - The ADC Control and Status register A 1509.equ ADPS0 = 0 ; ADC Prescaler Select Bits 1510.equ ADPS1 = 1 ; ADC Prescaler Select Bits 1511.equ ADPS2 = 2 ; ADC Prescaler Select Bits 1512.equ ADIE = 3 ; ADC Interrupt Enable 1513.equ ADIF = 4 ; ADC Interrupt Flag 1514.equ ADATE = 5 ; ADC Auto Trigger Enable 1515.equ ADSC = 6 ; ADC Start Conversion 1516.equ ADEN = 7 ; ADC Enable 1517 1518; ADCSRB - The ADC Control and Status register B 1519.equ ADTS0 = 0 ; ADC Auto Trigger Source bit 0 1520.equ ADTS1 = 1 ; ADC Auto Trigger Source bit 1 1521.equ ADTS2 = 2 ; ADC Auto Trigger Source bit 2 1522.equ MUX5 = 3 ; Analog Channel and Gain Selection Bits 1523;.equ ACME = 6 ; 1524 1525; ADCH - ADC Data Register High Byte 1526.equ ADCH0 = 0 ; ADC Data Register High Byte Bit 0 1527.equ ADCH1 = 1 ; ADC Data Register High Byte Bit 1 1528.equ ADCH2 = 2 ; ADC Data Register High Byte Bit 2 1529.equ ADCH3 = 3 ; ADC Data Register High Byte Bit 3 1530.equ ADCH4 = 4 ; ADC Data Register High Byte Bit 4 1531.equ ADCH5 = 5 ; ADC Data Register High Byte Bit 5 1532.equ ADCH6 = 6 ; ADC Data Register High Byte Bit 6 1533.equ ADCH7 = 7 ; ADC Data Register High Byte Bit 7 1534 1535; ADCL - ADC Data Register Low Byte 1536.equ ADCL0 = 0 ; ADC Data Register Low Byte Bit 0 1537.equ ADCL1 = 1 ; ADC Data Register Low Byte Bit 1 1538.equ ADCL2 = 2 ; ADC Data Register Low Byte Bit 2 1539.equ ADCL3 = 3 ; ADC Data Register Low Byte Bit 3 1540.equ ADCL4 = 4 ; ADC Data Register Low Byte Bit 4 1541.equ ADCL5 = 5 ; ADC Data Register Low Byte Bit 5 1542.equ ADCL6 = 6 ; ADC Data Register Low Byte Bit 6 1543.equ ADCL7 = 7 ; ADC Data Register Low Byte Bit 7 1544 1545; DIDR0 - Digital Input Disable Register 1546.equ ADC0D = 0 ; 1547.equ ADC1D = 1 ; 1548.equ ADC2D = 2 ; 1549.equ ADC3D = 3 ; 1550.equ ADC4D = 4 ; 1551.equ ADC5D = 5 ; 1552.equ ADC6D = 6 ; 1553.equ ADC7D = 7 ; 1554 1555; DIDR2 - Digital Input Disable Register 1556.equ ADC8D = 0 ; 1557.equ ADC9D = 1 ; 1558.equ ADC10D = 2 ; 1559.equ ADC11D = 3 ; 1560.equ ADC12D = 4 ; 1561.equ ADC13D = 5 ; 1562.equ ADC14D = 6 ; 1563.equ ADC15D = 7 ; 1564 1565 1566; ***** BOOT_LOAD ******************** 1567; SPMCSR - Store Program Memory Control Register 1568.equ SPMEN = 0 ; Store Program Memory Enable 1569.equ PGERS = 1 ; Page Erase 1570.equ PGWRT = 2 ; Page Write 1571.equ BLBSET = 3 ; Boot Lock Bit Set 1572.equ RWWSRE = 4 ; Read While Write section read enable 1573.equ SIGRD = 5 ; Signature Row Read 1574.equ RWWSB = 6 ; Read While Write Section Busy 1575.equ SPMIE = 7 ; SPM Interrupt Enable 1576 1577 1578; ***** USART2 *********************** 1579; UDR2 - USART I/O Data Register 1580.equ UDR2_0 = 0 ; USART I/O Data Register bit 0 1581.equ UDR2_1 = 1 ; USART I/O Data Register bit 1 1582.equ UDR2_2 = 2 ; USART I/O Data Register bit 2 1583.equ UDR2_3 = 3 ; USART I/O Data Register bit 3 1584.equ UDR2_4 = 4 ; USART I/O Data Register bit 4 1585.equ UDR2_5 = 5 ; USART I/O Data Register bit 5 1586.equ UDR2_6 = 6 ; USART I/O Data Register bit 6 1587.equ UDR2_7 = 7 ; USART I/O Data Register bit 7 1588 1589; UCSR2A - USART Control and Status Register A 1590.equ MPCM2 = 0 ; Multi-processor Communication Mode 1591.equ U2X2 = 1 ; Double the USART transmission speed 1592.equ UPE2 = 2 ; Parity Error 1593.equ DOR2 = 3 ; Data overRun 1594.equ FE2 = 4 ; Framing Error 1595.equ UDRE2 = 5 ; USART Data Register Empty 1596.equ TXC2 = 6 ; USART Transmitt Complete 1597.equ RXC2 = 7 ; USART Receive Complete 1598 1599; UCSR2B - USART Control and Status Register B 1600.equ TXB82 = 0 ; Transmit Data Bit 8 1601.equ RXB82 = 1 ; Receive Data Bit 8 1602.equ UCSZ22 = 2 ; Character Size 1603.equ TXEN2 = 3 ; Transmitter Enable 1604.equ RXEN2 = 4 ; Receiver Enable 1605.equ UDRIE2 = 5 ; USART Data register Empty Interrupt Enable 1606.equ TXCIE2 = 6 ; TX Complete Interrupt Enable 1607.equ RXCIE2 = 7 ; RX Complete Interrupt Enable 1608 1609; UCSR2C - USART Control and Status Register C 1610.equ UCPOL2 = 0 ; Clock Polarity 1611.equ UCSZ20 = 1 ; Character Size 1612.equ UCSZ21 = 2 ; Character Size 1613.equ USBS2 = 3 ; Stop Bit Select 1614.equ UPM20 = 4 ; Parity Mode Bit 0 1615.equ UPM21 = 5 ; Parity Mode Bit 1 1616.equ UMSEL20 = 6 ; USART Mode Select 1617.equ UMSEL21 = 7 ; USART Mode Select 1618 1619; UBRR2H - USART Baud Rate Register High Byte 1620;.equ UBRR8 = 0 ; USART Baud Rate Register bit 8 1621;.equ UBRR9 = 1 ; USART Baud Rate Register bit 9 1622;.equ UBRR10 = 2 ; USART Baud Rate Register bit 10 1623;.equ UBRR11 = 3 ; USART Baud Rate Register bit 11 1624 1625; UBRR2L - USART Baud Rate Register Low Byte 1626.equ UBRR0 = 0 ; USART Baud Rate Register bit 0 1627.equ UBRR1 = 1 ; USART Baud Rate Register bit 1 1628;.equ UBRR2 = 2 ; USART Baud Rate Register bit 2 1629;.equ UBRR3 = 3 ; USART Baud Rate Register bit 3 1630;.equ UBRR4 = 4 ; USART Baud Rate Register bit 4 1631;.equ UBRR5 = 5 ; USART Baud Rate Register bit 5 1632;.equ UBRR6 = 6 ; USART Baud Rate Register bit 6 1633;.equ UBRR7 = 7 ; USART Baud Rate Register bit 7 1634 1635 1636; ***** USART3 *********************** 1637; UDR3 - USART I/O Data Register 1638.equ UDR3_0 = 0 ; USART I/O Data Register bit 0 1639.equ UDR3_1 = 1 ; USART I/O Data Register bit 1 1640.equ UDR3_2 = 2 ; USART I/O Data Register bit 2 1641.equ UDR3_3 = 3 ; USART I/O Data Register bit 3 1642.equ UDR3_4 = 4 ; USART I/O Data Register bit 4 1643.equ UDR3_5 = 5 ; USART I/O Data Register bit 5 1644.equ UDR3_6 = 6 ; USART I/O Data Register bit 6 1645.equ UDR3_7 = 7 ; USART I/O Data Register bit 7 1646 1647; UCSR3A - USART Control and Status Register A 1648.equ MPCM3 = 0 ; Multi-processor Communication Mode 1649.equ U2X3 = 1 ; Double the USART transmission speed 1650.equ UPE3 = 2 ; Parity Error 1651.equ DOR3 = 3 ; Data overRun 1652.equ FE3 = 4 ; Framing Error 1653.equ UDRE3 = 5 ; USART Data Register Empty 1654.equ TXC3 = 6 ; USART Transmitt Complete 1655.equ RXC3 = 7 ; USART Receive Complete 1656 1657; UCSR3B - USART Control and Status Register B 1658.equ TXB83 = 0 ; Transmit Data Bit 8 1659.equ RXB83 = 1 ; Receive Data Bit 8 1660.equ UCSZ32 = 2 ; Character Size 1661.equ TXEN3 = 3 ; Transmitter Enable 1662.equ RXEN3 = 4 ; Receiver Enable 1663.equ UDRIE3 = 5 ; USART Data register Empty Interrupt Enable 1664.equ TXCIE3 = 6 ; TX Complete Interrupt Enable 1665.equ RXCIE3 = 7 ; RX Complete Interrupt Enable 1666 1667; UCSR3C - USART Control and Status Register C 1668.equ UCPOL3 = 0 ; Clock Polarity 1669.equ UCSZ30 = 1 ; Character Size 1670.equ UCSZ31 = 2 ; Character Size 1671.equ USBS3 = 3 ; Stop Bit Select 1672.equ UPM30 = 4 ; Parity Mode Bit 0 1673.equ UPM31 = 5 ; Parity Mode Bit 1 1674.equ UMSEL30 = 6 ; USART Mode Select 1675.equ UMSEL31 = 7 ; USART Mode Select 1676 1677; UBRR3H - USART Baud Rate Register High Byte 1678;.equ UBRR8 = 0 ; USART Baud Rate Register bit 8 1679;.equ UBRR9 = 1 ; USART Baud Rate Register bit 9 1680;.equ UBRR10 = 2 ; USART Baud Rate Register bit 10 1681;.equ UBRR11 = 3 ; USART Baud Rate Register bit 11 1682 1683; UBRR3L - USART Baud Rate Register Low Byte 1684;.equ UBRR0 = 0 ; USART Baud Rate Register bit 0 1685;.equ UBRR1 = 1 ; USART Baud Rate Register bit 1 1686;.equ UBRR2 = 2 ; USART Baud Rate Register bit 2 1687;.equ UBRR3 = 3 ; USART Baud Rate Register bit 3 1688;.equ UBRR4 = 4 ; USART Baud Rate Register bit 4 1689;.equ UBRR5 = 5 ; USART Baud Rate Register bit 5 1690;.equ UBRR6 = 6 ; USART Baud Rate Register bit 6 1691;.equ UBRR7 = 7 ; USART Baud Rate Register bit 7 1692 1693 1694 1695; ***** LOCKSBITS ******************************************************** 1696.equ LB1 = 0 ; Lock bit 1697.equ LB2 = 1 ; Lock bit 1698.equ BLB01 = 2 ; Boot Lock bit 1699.equ BLB02 = 3 ; Boot Lock bit 1700.equ BLB11 = 4 ; Boot lock bit 1701.equ BLB12 = 5 ; Boot lock bit 1702 1703 1704; ***** FUSES ************************************************************ 1705; LOW fuse bits 1706.equ CKSEL0 = 0 ; Select Clock Source 1707.equ CKSEL1 = 1 ; Select Clock Source 1708.equ CKSEL2 = 2 ; Select Clock Source 1709.equ CKSEL3 = 3 ; Select Clock Source 1710.equ SUT0 = 4 ; Select start-up time 1711.equ SUT1 = 5 ; Select start-up time 1712.equ CKOUT = 6 ; Clock output 1713.equ CKDIV8 = 7 ; Divide clock by 8 1714 1715; HIGH fuse bits 1716.equ BOOTRST = 0 ; Select Reset Vector 1717.equ BOOTSZ0 = 1 ; Select Boot Size 1718.equ BOOTSZ1 = 2 ; Select Boot Size 1719.equ EESAVE = 3 ; EEPROM memory is preserved through chip erase 1720.equ WDTON = 4 ; Watchdog timer always on 1721.equ SPIEN = 5 ; Enable Serial programming and Data Downloading 1722.equ JTAGEN = 6 ; Enable JTAG 1723.equ OCDEN = 7 ; Enable OCD 1724 1725; EXTENDED fuse bits 1726.equ BODLEVEL0 = 0 ; Brown-out Detector trigger level 1727.equ BODLEVEL1 = 1 ; Brown-out Detector trigger level 1728.equ BODLEVEL2 = 2 ; Brown-out Detector trigger level 1729 1730 1731 1732; ***** CPU REGISTER DEFINITIONS ***************************************** 1733.def XH = r27 1734.def XL = r26 1735.def YH = r29 1736.def YL = r28 1737.def ZH = r31 1738.def ZL = r30 1739 1740 1741 1742; ***** DATA MEMORY DECLARATIONS ***************************************** 1743.equ FLASHEND = 0xffff ; Note: Word address 1744.equ IOEND = 0x01ff 1745.equ SRAM_START = 0x0200 1746.equ SRAM_SIZE = 8192 1747.equ RAMEND = 0x21ff 1748.equ XRAMEND = 0xffff 1749.equ E2END = 0x0fff 1750.equ EEPROMEND = 0x0fff 1751.equ EEADRBITS = 12 1752#pragma AVRPART MEMORY PROG_FLASH 131072 1753#pragma AVRPART MEMORY EEPROM 4096 1754#pragma AVRPART MEMORY INT_SRAM SIZE 8192 1755#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x200 1756 1757 1758 1759; ***** BOOTLOADER DECLARATIONS ****************************************** 1760.equ NRWW_START_ADDR = 0xf000 1761.equ NRWW_STOP_ADDR = 0xffff 1762.equ RWW_START_ADDR = 0x0 1763.equ RWW_STOP_ADDR = 0xefff 1764.equ PAGESIZE = 128 1765.equ FIRSTBOOTSTART = 0xfe00 1766.equ SECONDBOOTSTART = 0xfc00 1767.equ THIRDBOOTSTART = 0xf800 1768.equ FOURTHBOOTSTART = 0xf000 1769.equ SMALLBOOTSTART = FIRSTBOOTSTART 1770.equ LARGEBOOTSTART = FOURTHBOOTSTART 1771 1772 1773 1774; ***** INTERRUPT VECTORS ************************************************ 1775.equ INT0addr = 0x0002 ; External Interrupt Request 0 1776.equ INT1addr = 0x0004 ; External Interrupt Request 1 1777.equ INT2addr = 0x0006 ; External Interrupt Request 2 1778.equ INT3addr = 0x0008 ; External Interrupt Request 3 1779.equ INT4addr = 0x000a ; External Interrupt Request 4 1780.equ INT5addr = 0x000c ; External Interrupt Request 5 1781.equ INT6addr = 0x000e ; External Interrupt Request 6 1782.equ INT7addr = 0x0010 ; External Interrupt Request 7 1783.equ PCI0addr = 0x0012 ; Pin Change Interrupt Request 0 1784.equ PCI1addr = 0x0014 ; Pin Change Interrupt Request 1 1785.equ PCI2addr = 0x0016 ; Pin Change Interrupt Request 2 1786.equ WDTaddr = 0x0018 ; Watchdog Time-out Interrupt 1787.equ OC2Aaddr = 0x001a ; Timer/Counter2 Compare Match A 1788.equ OC2Baddr = 0x001c ; Timer/Counter2 Compare Match B 1789.equ OVF2addr = 0x001e ; Timer/Counter2 Overflow 1790.equ ICP1addr = 0x0020 ; Timer/Counter1 Capture Event 1791.equ OC1Aaddr = 0x0022 ; Timer/Counter1 Compare Match A 1792.equ OC1Baddr = 0x0024 ; Timer/Counter1 Compare Match B 1793.equ OC1Caddr = 0x0026 ; Timer/Counter1 Compare Match C 1794.equ OVF1addr = 0x0028 ; Timer/Counter1 Overflow 1795.equ OC0Aaddr = 0x002a ; Timer/Counter0 Compare Match A 1796.equ OC0Baddr = 0x002c ; Timer/Counter0 Compare Match B 1797.equ OVF0addr = 0x002e ; Timer/Counter0 Overflow 1798.equ SPIaddr = 0x0030 ; SPI Serial Transfer Complete 1799.equ URXC0addr = 0x0032 ; USART0, Rx Complete 1800.equ UDRE0addr = 0x0034 ; USART0 Data register Empty 1801.equ UTXC0addr = 0x0036 ; USART0, Tx Complete 1802.equ ACIaddr = 0x0038 ; Analog Comparator 1803.equ ADCCaddr = 0x003a ; ADC Conversion Complete 1804.equ ERDYaddr = 0x003c ; EEPROM Ready 1805.equ ICP3addr = 0x003e ; Timer/Counter3 Capture Event 1806.equ OC3Aaddr = 0x0040 ; Timer/Counter3 Compare Match A 1807.equ OC3Baddr = 0x0042 ; Timer/Counter3 Compare Match B 1808.equ OC3Caddr = 0x0044 ; Timer/Counter3 Compare Match C 1809.equ OVF3addr = 0x0046 ; Timer/Counter3 Overflow 1810.equ URXC1addr = 0x0048 ; USART1, Rx Complete 1811.equ UDRE1addr = 0x004a ; USART1 Data register Empty 1812.equ UTXC1addr = 0x004c ; USART1, Tx Complete 1813.equ TWIaddr = 0x004e ; 2-wire Serial Interface 1814.equ SPMRaddr = 0x0050 ; Store Program Memory Read 1815.equ ICP4addr = 0x0052 ; Timer/Counter4 Capture Event 1816.equ OC4Aaddr = 0x0054 ; Timer/Counter4 Compare Match A 1817.equ OC4Baddr = 0x0056 ; Timer/Counter4 Compare Match B 1818.equ OC4Caddr = 0x0058 ; Timer/Counter4 Compare Match C 1819.equ OVF4addr = 0x005a ; Timer/Counter4 Overflow 1820.equ ICP5addr = 0x005c ; Timer/Counter5 Capture Event 1821.equ OC5Aaddr = 0x005e ; Timer/Counter5 Compare Match A 1822.equ OC5Baddr = 0x0060 ; Timer/Counter5 Compare Match B 1823.equ OC5Caddr = 0x0062 ; Timer/Counter5 Compare Match C 1824.equ OVF5addr = 0x0064 ; Timer/Counter5 Overflow 1825.equ URXC2addr = 0x0066 ; USART2, Rx Complete 1826.equ UDRE2addr = 0x0068 ; USART2 Data register Empty 1827.equ UTXC2addr = 0x006a ; USART2, Tx Complete 1828.equ URXC3addr = 0x006c ; USART3, Rx Complete 1829.equ UDRE3addr = 0x006e ; USART3 Data register Empty 1830.equ UTXC3addr = 0x0070 ; USART3, Tx Complete 1831 1832.equ INT_VECTORS_SIZE = 114 ; size in words 1833 1834#endif /* _M1280DEF_INC_ */ 1835 1836; ***** END OF FILE ****************************************************** 1837