1;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ******************** 2;***** Created: 2005-01-11 10:30 ******* Source: ATmega162.xml *********** 3;************************************************************************* 4;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y 5;* 6;* Number : AVR000 7;* File Name : "m162def.inc" 8;* Title : Register/Bit Definitions for the ATmega162 9;* Date : 2005-01-11 10;* Version : 2.14 11;* Support E-mail : avr@atmel.com 12;* Target MCU : ATmega162 13;* 14;* DESCRIPTION 15;* When including this file in the assembly program file, all I/O register 16;* names and I/O register bit names appearing in the data book can be used. 17;* In addition, the six registers forming the three data pointers X, Y and 18;* Z have been assigned names XL - ZH. Highest RAM address for Internal 19;* SRAM is also defined 20;* 21;* The Register names are represented by their hexadecimal address. 22;* 23;* The Register Bit names are represented by their bit number (0-7). 24;* 25;* Please observe the difference in using the bit names with instructions 26;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" 27;* (skip if bit in register set/cleared). The following example illustrates 28;* this: 29;* 30;* in r16,PORTB ;read PORTB latch 31;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#) 32;* out PORTB,r16 ;output to PORTB 33;* 34;* in r16,TIFR ;read the Timer Interrupt Flag Register 35;* sbrc r16,TOV0 ;test the overflow flag (use bit#) 36;* rjmp TOV0_is_set ;jump if set 37;* ... ;otherwise do something else 38;************************************************************************* 39 40#ifndef _M162DEF_INC_ 41#define _M162DEF_INC_ 42 43 44#pragma partinc 0 45 46; ***** SPECIFY DEVICE *************************************************** 47.device ATmega162 48#pragma AVRPART ADMIN PART_NAME ATmega162 49.equ SIGNATURE_000 = 0x1e 50.equ SIGNATURE_001 = 0x94 51.equ SIGNATURE_002 = 0x04 52 53#pragma AVRPART CORE CORE_VERSION V2E 54 55 56; ***** I/O REGISTER DEFINITIONS ***************************************** 57; NOTE: 58; Definitions marked "MEMORY MAPPED"are extended I/O ports 59; and cannot be used with IN/OUT instructions 60.equ TCCR3A = 0x8b ; MEMORY MAPPED 61.equ TCCR3B = 0x8a ; MEMORY MAPPED 62.equ TCNT3H = 0x89 ; MEMORY MAPPED 63.equ TCNT3L = 0x88 ; MEMORY MAPPED 64.equ OCR3AH = 0x87 ; MEMORY MAPPED 65.equ OCR3AL = 0x86 ; MEMORY MAPPED 66.equ OCR3BH = 0x85 ; MEMORY MAPPED 67.equ OCR3BL = 0x84 ; MEMORY MAPPED 68.equ ICR3H = 0x81 ; MEMORY MAPPED 69.equ ICR3L = 0x80 ; MEMORY MAPPED 70.equ ETIMSK = 0x7d ; MEMORY MAPPED 71.equ ETIFR = 0x7c ; MEMORY MAPPED 72.equ PCMSK1 = 0x6c ; MEMORY MAPPED 73.equ PCMSK0 = 0x6b ; MEMORY MAPPED 74.equ CLKPR = 0x61 ; MEMORY MAPPED 75.equ SREG = 0x3f 76.equ SPH = 0x3e 77.equ SPL = 0x3d 78.equ UBRR1H = 0x3c 79.equ UCSR1C = 0x3c 80.equ GICR = 0x3b 81.equ GIFR = 0x3a 82.equ TIMSK = 0x39 83.equ TIFR = 0x38 84.equ SPMCR = 0x37 85.equ EMCUCR = 0x36 86.equ MCUCR = 0x35 87.equ MCUCSR = 0x34 88.equ TCCR0 = 0x33 89.equ TCNT0 = 0x32 90.equ OCR0 = 0x31 91.equ SFIOR = 0x30 92.equ TCCR1A = 0x2f 93.equ TCCR1B = 0x2e 94.equ TCNT1H = 0x2d 95.equ TCNT1L = 0x2c 96.equ OCR1AH = 0x2b 97.equ OCR1AL = 0x2a 98.equ OCR1BH = 0x29 99.equ OCR1BL = 0x28 100.equ TCCR2 = 0x27 101.equ ASSR = 0x26 102.equ ICR1H = 0x25 103.equ ICR1L = 0x24 104.equ TCNT2 = 0x23 105.equ OCR2 = 0x22 106.equ WDTCR = 0x21 107.equ UBRR0H = 0x20 108.equ UCSR0C = 0x20 109.equ EEARH = 0x1f 110.equ EEARL = 0x1e 111.equ EEDR = 0x1d 112.equ EECR = 0x1c 113.equ PORTA = 0x1b 114.equ DDRA = 0x1a 115.equ PINA = 0x19 116.equ PORTB = 0x18 117.equ DDRB = 0x17 118.equ PINB = 0x16 119.equ PORTC = 0x15 120.equ DDRC = 0x14 121.equ PINC = 0x13 122.equ PORTD = 0x12 123.equ DDRD = 0x11 124.equ PIND = 0x10 125.equ SPDR = 0x0f 126.equ SPSR = 0x0e 127.equ SPCR = 0x0d 128.equ UDR0 = 0x0c 129.equ UCSR0A = 0x0b 130.equ UCSR0B = 0x0a 131.equ UBRR0L = 0x09 132.equ ACSR = 0x08 133.equ PORTE = 0x07 134.equ DDRE = 0x06 135.equ PINE = 0x05 136.equ OSCCAL = 0x04 137.equ OCDR = 0x04 138.equ UDR1 = 0x03 139.equ UCSR1A = 0x02 140.equ UCSR1B = 0x01 141.equ UBRR1L = 0x00 142 143 144; ***** BIT DEFINITIONS ************************************************** 145 146; ***** TIMER_COUNTER_1 ************** 147; TIMSK - Timer/Counter Interrupt Mask Register 148.equ TICIE1 = 3 ; Timer/Counter1 Input Capture Interrupt Enable 149.equ OCIE1B = 5 ; Timer/Counter1 Output CompareB Match Interrupt Enable 150.equ OCIE1A = 6 ; Timer/Counter1 Output CompareA Match Interrupt Enable 151.equ TOIE1 = 7 ; Timer/Counter1 Overflow Interrupt Enable 152 153; TIFR - Timer/Counter Interrupt Flag register 154.equ ICF1 = 3 ; Input Capture Flag 1 155.equ OCF1B = 5 ; Output Compare Flag 1B 156.equ OCF1A = 6 ; Output Compare Flag 1A 157.equ TOV1 = 7 ; Timer/Counter1 Overflow Flag 158 159; TCCR1A - Timer/Counter1 Control Register A 160.equ WGM10 = 0 ; Pulse Width Modulator Select Bit 0 161.equ PWM10 = WGM10 ; For compatibility 162.equ WGM11 = 1 ; Pulse Width Modulator Select Bit 1 163.equ PWM11 = WGM11 ; For compatibility 164.equ FOC1B = 2 ; Force Output Compare for Channel B 165.equ FOC1A = 3 ; Force Output Compare for Channel A 166.equ COM1B0 = 4 ; Compare Output Mode 1B, bit 0 167.equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1 168.equ COM1A0 = 6 ; Compare Ouput Mode 1A, bit 0 169.equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1 170 171; TCCR1B - Timer/Counter1 Control Register B 172.equ CS10 = 0 ; Clock Select1 bit 0 173.equ CS11 = 1 ; Clock Select1 bit 1 174.equ CS12 = 2 ; Clock Select1 bit 2 175.equ WGM12 = 3 ; Pulse Width Modulator Select Bit 2 176.equ CTC10 = WGM12 ; For compatibility 177.equ WGM13 = 4 ; Pulse Width Modulator Select Bit 3 178.equ CTC11 = WGM13 ; For compatibility 179.equ ICES1 = 6 ; Input Capture 1 Edge Select 180.equ ICNC1 = 7 ; Input Capture 1 Noise Canceler 181 182 183; ***** TIMER_COUNTER_2 ************** 184; TCCR2 - Timer/Counter Control Register 185.equ CS20 = 0 ; Clock Select 186.equ CS21 = 1 ; Clock Select 187.equ CS22 = 2 ; Clock Select 188.equ WGM21 = 3 ; Pulse Width Modulator Select Bit 1 189.equ CTC2 = WGM21 ; For compatibility 190.equ COM20 = 4 ; Compare Match Output Mode 191.equ COM21 = 5 ; Compare Match Output Mode 192.equ WGM20 = 6 ; Pulse Width Modulator Select Bit 0 193.equ PWM2 = WGM20 ; For compatibility 194.equ FOC2 = 7 ; Forde Output Compare 195 196; TCNT2 - Timer/Counter Register 197.equ TCNT2_0 = 0 ; Timer/Counter Register Bit 0 198.equ TCNT2_1 = 1 ; Timer/Counter Register Bit 1 199.equ TCNT2_2 = 2 ; Timer/Counter Register Bit 2 200.equ TCNT2_3 = 3 ; Timer/Counter Register Bit 3 201.equ TCNT2_4 = 4 ; Timer/Counter Register Bit 4 202.equ TCNT2_5 = 5 ; Timer/Counter Register Bit 5 203.equ TCNT2_6 = 6 ; Timer/Counter Register Bit 6 204.equ TCNT2_7 = 7 ; Timer/Counter Register Bit 7 205 206; OCR2 - Output Compare Register 207.equ OCR2_0 = 0 ; Output Compare Register Bit 0 208.equ OCR2_1 = 1 ; Output Compare Register Bit 1 209.equ OCR2_2 = 2 ; Output Compare Register Bit 2 210.equ OCR2_3 = 3 ; Output Compare Register Bit 3 211.equ OCR2_4 = 4 ; Output Compare Register Bit 4 212.equ OCR2_5 = 5 ; Output Compare Register Bit 5 213.equ OCR2_6 = 6 ; Output Compare Register Bit 6 214.equ OCR2_7 = 7 ; Output Compare Register Bit 7 215 216; TIMSK - Timer/Counter Interrupt Mask Register 217.equ TOIE2 = 2 ; Timer/Counter2 Overflow Interrupt Enable 218.equ OCIE2 = 4 ; Timer/Counter2 Output Compare Match Interrupt Enable 219 220; TIFR - Timer/Counter Interrupt Flag Register 221.equ TOV2 = 2 ; Timer/Counter2 Overflow Flag 222.equ OCF2 = 4 ; Output Compare Flag 2 223 224; ASSR - Asynchronous Status Register 225.equ TCR2UB = 0 ; Timer/Counter Control Register2 Update Busy 226.equ OCR2UB = 1 ; Output Compare Register2 Update Busy 227.equ TCN2UB = 2 ; Timer/Counter2 Update Busy 228.equ AS2 = 3 ; Asynchronous Timer 2 229 230 231; ***** TIMER_COUNTER_3 ************** 232; ETIMSK - Extended Timer/Counter Interrupt Mask Register 233.equ TOIE3 = 2 ; Timer/Counter3 Overflow Interrupt Enable 234.equ OCIE3B = 3 ; Timer/Counter3 Output CompareB Match Interrupt Enable 235.equ OCIE3A = 4 ; Timer/Counter3 Output CompareA Match Interrupt Enable 236.equ TICIE3 = 5 ; Timer/Counter3 Input Capture Interrupt Enable 237 238; ETIFR - Extended Timer/Counter Interrupt Flag register 239.equ TOV3 = 2 ; Timer/Counter3 Overflow Flag 240.equ OCF3B = 3 ; Output Compare Flag 3B 241.equ OCF3A = 4 ; Output Compare Flag 3A 242.equ ICF3 = 5 ; Input Capture Flag 3 243 244; TCCR3A - Timer/Counter3 Control Register A 245.equ WGM30 = 0 ; Pulse Width Modulator Select Bit 0 246.equ WGM31 = 1 ; Pulse Width Modulator Select Bit 1 247.equ FOC3B = 2 ; Force Output Compare for Channel B 248.equ FOC3A = 3 ; Force Output Compare for Channel A 249.equ COM3B0 = 4 ; Compare Output Mode 3B, bit 0 250.equ COM3B1 = 5 ; Compare Output Mode 3B, bit 1 251.equ COM3A0 = 6 ; Compare Ouput Mode 3A, bit 0 252.equ COM3A1 = 7 ; Compare Output Mode 3A, bit 1 253 254; TCCR3B - Timer/Counter3 Control Register B 255.equ CS30 = 0 ; Clock Select3 bit 0 256.equ CS31 = 1 ; Clock Select3 bit 1 257.equ CS32 = 2 ; Clock Select3 bit 2 258.equ WGM32 = 3 ; Pulse Width Modulator Select Bit 2 259.equ WGM33 = 4 ; Pulse Width Modulator Select Bit 3 260.equ ICES3 = 6 ; Input Capture 3 Edge Select 261.equ ICNC3 = 7 ; Input Capture 3 Noise Canceler 262 263 264; ***** ANALOG_COMPARATOR ************ 265; ACSR - Analog Comparator Control And Status Register 266.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0 267.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1 268.equ ACIC = 2 ; Analog Comparator Input Capture Enable 269.equ ACIE = 3 ; Analog Comparator Interrupt Enable 270.equ ACI = 4 ; Analog Comparator Interrupt Flag 271.equ ACO = 5 ; Analog Compare Output 272.equ ACBG = 6 ; Analog Comparator Bandgap Select 273.equ AINBG = ACBG ; For compatibility 274.equ ACD = 7 ; Analog Comparator Disable 275 276 277; ***** USART0 *********************** 278; UDR0 - USART I/O Data Register 279.equ UDR = UDR0 ; For compatibility 280.equ UDR0_0 = 0 ; USART I/O Data Register bit 0 281.equ UDR0_1 = 1 ; USART I/O Data Register bit 1 282.equ UDR0_2 = 2 ; USART I/O Data Register bit 2 283.equ UDR0_3 = 3 ; USART I/O Data Register bit 3 284.equ UDR0_4 = 4 ; USART I/O Data Register bit 4 285.equ UDR0_5 = 5 ; USART I/O Data Register bit 5 286.equ UDR0_6 = 6 ; USART I/O Data Register bit 6 287.equ UDR0_7 = 7 ; USART I/O Data Register bit 7 288 289; UCSR0A - USART Control and Status Register A 290.equ USR = UCSR0A ; For compatibility 291.equ MPCM0 = 0 ; Multi-processor Communication Mode 292.equ U2X0 = 1 ; Double the USART transmission speed 293.equ U2X = U2X0 ; For compatibility 294.equ UPE0 = 2 ; Parity Error 295.equ DOR0 = 3 ; Data overRun 296.equ DOR = DOR0 ; For compatibility 297.equ FE0 = 4 ; Framing Error 298.equ FE = FE0 ; For compatibility 299.equ UDRE0 = 5 ; USART Data Register Empty 300.equ UDRE = UDRE0 ; For compatibility 301.equ TXC0 = 6 ; USART Transmitt Complete 302.equ TXC = TXC0 ; For compatibility 303.equ RXC0 = 7 ; USART Receive Complete 304.equ RXC = RXC0 ; For compatibility 305 306; UCSR0B - USART Control and Status Register B 307.equ UCR = UCSR0B ; For compatibility 308.equ TXB80 = 0 ; Transmit Data Bit 8 309.equ TXB8 = TXB80 ; For compatibility 310.equ RXB80 = 1 ; Receive Data Bit 8 311.equ RXB8 = RXB80 ; For compatibility 312.equ UCSZ02 = 2 ; Character Size 313.equ UCSZ2 = UCSZ02 ; For compatibility 314.equ TXEN0 = 3 ; Transmitter Enable 315.equ TXEN = TXEN0 ; For compatibility 316.equ RXEN0 = 4 ; Receiver Enable 317.equ RXEN = RXEN0 ; For compatibility 318.equ UDRIE0 = 5 ; USART Data register Empty Interrupt Enable 319.equ UDRIE = UDRIE0 ; For compatibility 320.equ TXCIE0 = 6 ; TX Complete Interrupt Enable 321.equ TXCIE = TXCIE0 ; For compatibility 322.equ RXCIE0 = 7 ; RX Complete Interrupt Enable 323.equ RXCIE = RXCIE0 ; For compatibility 324 325; UCSR0C - USART Control and Status Register C 326.equ UBRRHI = UCSR0C ; For compatibility 327.equ UCPOL0 = 0 ; Clock Polarity 328.equ UCSZ00 = 1 ; Character Size 329.equ UCSZ01 = 2 ; Character Size 330.equ USBS0 = 3 ; Stop Bit Select 331.equ UPM00 = 4 ; Parity Mode Bit 0 332.equ UPM01 = 5 ; Parity Mode Bit 1 333.equ UMSEL0 = 6 ; USART Mode Select 334.equ URSEL = 7 ; Register Select 335 336.equ UBRR0 = UBRR0L ; For compatibility 337.equ UBRR = UBRR0L ; For compatibility 338 339; ***** USART1 *********************** 340; UDR1 - USART I/O Data Register 341.equ UDR1_0 = 0 ; USART1 I/O Data Register bit 0 342.equ UDR1_1 = 1 ; USART1 I/O Data Register bit 1 343.equ UDR1_2 = 2 ; USART1 I/O Data Register bit 2 344.equ UDR1_3 = 3 ; USART1 I/O Data Register bit 3 345.equ UDR1_4 = 4 ; USART1 I/O Data Register bit 4 346.equ UDR1_5 = 5 ; USART1 I/O Data Register bit 5 347.equ UDR1_6 = 6 ; USART1 I/O Data Register bit 6 348.equ UDR1_7 = 7 ; USART1 I/O Data Register bit 7 349 350; UCSR1A - USART Control and Status Register A 351.equ MPCM1 = 0 ; Multi-processor Communication Mode 352.equ U2X1 = 1 ; Double the USART transmission speed 353.equ UPE1 = 2 ; Parity Error 354.equ DOR1 = 3 ; Data overRun 355.equ FE1 = 4 ; Framing Error 356.equ UDRE1 = 5 ; USART Data Register Empty 357.equ TXC1 = 6 ; USART Transmitt Complete 358.equ RXC1 = 7 ; USART Receive Complete 359 360; UCSR1B - USART Control and Status Register B 361.equ TXB81 = 0 ; Transmit Data Bit 8 362.equ RXB81 = 1 ; Receive Data Bit 8 363.equ UCSZ12 = 2 ; Character Size 364.equ CHR91 = UCSZ12 ; For compatibility 365.equ TXEN1 = 3 ; Transmitter Enable 366.equ RXEN1 = 4 ; Receiver Enable 367.equ UDRIE1 = 5 ; USART Data register Empty Interrupt Enable 368.equ TXCIE1 = 6 ; TX Complete Interrupt Enable 369.equ RXCIE1 = 7 ; RX Complete Interrupt Enable 370 371; UCSR1C - USART Control and Status Register C 372.equ UCPOL = 0 ; Clock Polarity 373.equ UCSZ0 = 1 ; Character Size 374.equ UCSZ1 = 2 ; Character Size 375.equ USBS = 3 ; Stop Bit Select 376.equ UPM0 = 4 ; Parity Mode Bit 0 377.equ UPM1 = 5 ; Parity Mode Bit 1 378.equ UMSEL = 6 ; USART Mode Select 379;.equ URSEL = 7 ; Register Select 380 381.equ UBRR1 = UBRR1L ; For compatibility 382 383; ***** SPI ************************** 384; SPDR - SPI Data Register 385.equ SPDR0 = 0 ; SPI Data Register bit 0 386.equ SPDR1 = 1 ; SPI Data Register bit 1 387.equ SPDR2 = 2 ; SPI Data Register bit 2 388.equ SPDR3 = 3 ; SPI Data Register bit 3 389.equ SPDR4 = 4 ; SPI Data Register bit 4 390.equ SPDR5 = 5 ; SPI Data Register bit 5 391.equ SPDR6 = 6 ; SPI Data Register bit 6 392.equ SPDR7 = 7 ; SPI Data Register bit 7 393 394; SPSR - SPI Status Register 395.equ SPI2X = 0 ; Double SPI Speed Bit 396.equ WCOL = 6 ; Write Collision Flag 397.equ SPIF = 7 ; SPI Interrupt Flag 398 399; SPCR - SPI Control Register 400.equ SPR0 = 0 ; SPI Clock Rate Select 0 401.equ SPR1 = 1 ; SPI Clock Rate Select 1 402.equ CPHA = 2 ; Clock Phase 403.equ CPOL = 3 ; Clock polarity 404.equ MSTR = 4 ; Master/Slave Select 405.equ DORD = 5 ; Data Order 406.equ SPE = 6 ; SPI Enable 407.equ SPIE = 7 ; SPI Interrupt Enable 408 409 410; ***** CPU ************************** 411; SREG - Status Register 412.equ SREG_C = 0 ; Carry Flag 413.equ SREG_Z = 1 ; Zero Flag 414.equ SREG_N = 2 ; Negative Flag 415.equ SREG_V = 3 ; Two's Complement Overflow Flag 416.equ SREG_S = 4 ; Sign Bit 417.equ SREG_H = 5 ; Half Carry Flag 418.equ SREG_T = 6 ; Bit Copy Storage 419.equ SREG_I = 7 ; Global Interrupt Enable 420 421; MCUCR - MCU Control Register 422.equ ISC00 = 0 ; Interrupt Sense Control 0 bit 0 423.equ ISC01 = 1 ; Interrupt Sense Control 0 bit 1 424.equ ISC10 = 2 ; Interrupt Sense Control 1 bit 1 425.equ ISC11 = 3 ; Interrupt Sense Control 1 bit 1 426.equ SM1 = 4 ; Sleep Mode Select 427.equ SM = SM1 ; For compatibility 428.equ SE = 5 ; Sleep Enable 429.equ SRW10 = 6 ; External SRAM Wait State Select 430.equ SRW = SRW10 ; For compatibility 431.equ SRE = 7 ; External SRAM Enable 432 433; MCUCSR - MCU Control And Status Register 434.equ MCUSR = MCUCSR ; For compatibility 435.equ PORF = 0 ; Power-on reset flag 436.equ EXTRF = 1 ; External Reset Flag 437.equ BORF = 2 ; Brown-out Reset Flag 438.equ WDRF = 3 ; Watchdog Reset Flag 439.equ JTRF = 4 ; JTAG Reset Flag 440.equ SM2 = 5 ; Sleep Mode Select Bit 2 441.equ JDT = 7 ; JTAG Interface Disable 442 443; EMCUCR - Extended MCU Control Register 444.equ ISC2 = 0 ; Interrupt Sense Control 2 445.equ SRW11 = 1 ; Wait State Select Bit 1 for Upper Sector 446.equ SRW00 = 2 ; Wait State Select Bit 0 for Lower Sector 447.equ SRW01 = 3 ; Wait State Select Bit 1 for Lower Sector 448.equ SRL0 = 4 ; Wait State Sector Limit Bit 0 449.equ SRL1 = 5 ; Wait State Sector Limit Bit 1 450.equ SRL2 = 6 ; Wait State Sector Limit Bit 2 451.equ SM0 = 7 ; Sleep mode Select Bit 0 452 453; OSCCAL - Oscillator Calibration Value 454.equ CAL0 = 0 ; Oscillator Calibration Value Bit0 455.equ CAL1 = 1 ; Oscillator Calibration Value Bit1 456.equ CAL2 = 2 ; Oscillator Calibration Value Bit2 457.equ CAL3 = 3 ; Oscillator Calibration Value Bit3 458.equ CAL4 = 4 ; Oscillator Calibration Value Bit4 459.equ CAL5 = 5 ; Oscillator Calibration Value Bit5 460.equ CAL6 = 6 ; Oscillator Calibration Value Bit6 461 462; CLKPR - Oscillator Calibration Value 463.equ CLKPS0 = 0 ; Clock Prescaler Select Bit 0 464.equ CLKPS1 = 1 ; Clock Prescaler Select Bit 1 465.equ CLKPS2 = 2 ; Clock Prescaler Select Bit 2 466.equ CLKPS3 = 3 ; Clock Prescaler Select Bit 3 467.equ CLKPCE = 7 ; Clock Prescaler Change Enable 468 469; SFIOR - Special Function IO Register 470.equ PSR310 = 0 ; Prescaler Reset Timer/Counter3, Timer/Counter1 and Timer/Counter0 471.equ PSR10 = PSR310 ; For compatibility 472.equ PSR0 = PSR310 ; For compatibility 473.equ PSR1 = PSR310 ; For compatibility 474.equ PSR2 = 1 ; Prescaler Reset Timer/Counter2 475.equ PUD = 2 ; Pull-up Disable 476.equ XMM0 = 3 ; External Memory High Mask Bit 0 477.equ XMM1 = 4 ; External Memory High Mask Bit 1 478.equ XMM2 = 5 ; External Memory High Mask Bit 2 479.equ XMBK = 6 ; External Memory Bus Keeper Enable 480.equ TSM = 7 ; Timer/Counter Synchronization Mode 481 482 483; ***** JTAG ************************* 484; OCDR - On-Chip Debug Related Register in I/O Memory 485.equ OCDR0 = 0 ; On-Chip Debug Register Bit 0 486.equ OCDR1 = 1 ; On-Chip Debug Register Bit 1 487.equ OCDR2 = 2 ; On-Chip Debug Register Bit 2 488.equ OCDR3 = 3 ; On-Chip Debug Register Bit 3 489.equ OCDR4 = 4 ; On-Chip Debug Register Bit 4 490.equ OCDR5 = 5 ; On-Chip Debug Register Bit 5 491.equ OCDR6 = 6 ; On-Chip Debug Register Bit 6 492.equ OCDR7 = 7 ; On-Chip Debug Register Bit 7 493.equ IDRD = OCDR7 ; For compatibility 494 495; MCUCSR - MCU Control And Status Register 496;.equ JTRF = 4 ; JTAG Reset Flag 497.equ JTD = 7 ; JTAG Interface Disable 498 499 500; ***** BOOT_LOAD ******************** 501; SPMCR - Store Program Memory Control Register 502.equ SPMEN = 0 ; Store Program Memory Enable 503.equ PGERS = 1 ; Page Erase 504.equ PGWRT = 2 ; Page Write 505.equ BLBSET = 3 ; Boot Lock Bit Set 506.equ RWWSRE = 4 ; Read While Write secion read enable 507.equ ASRE = RWWSRE ; For compatibility 508.equ RWWSB = 6 ; Read While Write Section Busy 509.equ ASB = RWWSB ; For compatibility 510.equ SPMIE = 7 ; SPM Interrupt Enable 511 512 513; ***** EEPROM *********************** 514; EEDR - EEPROM Data Register 515.equ EEDR0 = 0 ; EEPROM Data Register bit 0 516.equ EEDR1 = 1 ; EEPROM Data Register bit 1 517.equ EEDR2 = 2 ; EEPROM Data Register bit 2 518.equ EEDR3 = 3 ; EEPROM Data Register bit 3 519.equ EEDR4 = 4 ; EEPROM Data Register bit 4 520.equ EEDR5 = 5 ; EEPROM Data Register bit 5 521.equ EEDR6 = 6 ; EEPROM Data Register bit 6 522.equ EEDR7 = 7 ; EEPROM Data Register bit 7 523 524; EECR - EEPROM Control Register 525.equ EERE = 0 ; EEPROM Read Enable 526.equ EEWE = 1 ; EEPROM Write Enable 527.equ EEMWE = 2 ; EEPROM Master Write Enable 528.equ EEWEE = EEMWE ; For compatibility 529.equ EERIE = 3 ; EEPROM Ready Interrupt Enable 530 531 532; ***** PORTA ************************ 533; PORTA - Port A Data Register 534.equ PORTA0 = 0 ; Port A Data Register bit 0 535.equ PA0 = 0 ; For compatibility 536.equ PORTA1 = 1 ; Port A Data Register bit 1 537.equ PA1 = 1 ; For compatibility 538.equ PORTA2 = 2 ; Port A Data Register bit 2 539.equ PA2 = 2 ; For compatibility 540.equ PORTA3 = 3 ; Port A Data Register bit 3 541.equ PA3 = 3 ; For compatibility 542.equ PORTA4 = 4 ; Port A Data Register bit 4 543.equ PA4 = 4 ; For compatibility 544.equ PORTA5 = 5 ; Port A Data Register bit 5 545.equ PA5 = 5 ; For compatibility 546.equ PORTA6 = 6 ; Port A Data Register bit 6 547.equ PA6 = 6 ; For compatibility 548.equ PORTA7 = 7 ; Port A Data Register bit 7 549.equ PA7 = 7 ; For compatibility 550 551; DDRA - Port A Data Direction Register 552.equ DDA0 = 0 ; Data Direction Register, Port A, bit 0 553.equ DDA1 = 1 ; Data Direction Register, Port A, bit 1 554.equ DDA2 = 2 ; Data Direction Register, Port A, bit 2 555.equ DDA3 = 3 ; Data Direction Register, Port A, bit 3 556.equ DDA4 = 4 ; Data Direction Register, Port A, bit 4 557.equ DDA5 = 5 ; Data Direction Register, Port A, bit 5 558.equ DDA6 = 6 ; Data Direction Register, Port A, bit 6 559.equ DDA7 = 7 ; Data Direction Register, Port A, bit 7 560 561; PINA - Port A Input Pins 562.equ PINA0 = 0 ; Input Pins, Port A bit 0 563.equ PINA1 = 1 ; Input Pins, Port A bit 1 564.equ PINA2 = 2 ; Input Pins, Port A bit 2 565.equ PINA3 = 3 ; Input Pins, Port A bit 3 566.equ PINA4 = 4 ; Input Pins, Port A bit 4 567.equ PINA5 = 5 ; Input Pins, Port A bit 5 568.equ PINA6 = 6 ; Input Pins, Port A bit 6 569.equ PINA7 = 7 ; Input Pins, Port A bit 7 570 571 572; ***** PORTB ************************ 573; PORTB - Port B Data Register 574.equ PORTB0 = 0 ; Port B Data Register bit 0 575.equ PB0 = 0 ; For compatibility 576.equ PORTB1 = 1 ; Port B Data Register bit 1 577.equ PB1 = 1 ; For compatibility 578.equ PORTB2 = 2 ; Port B Data Register bit 2 579.equ PB2 = 2 ; For compatibility 580.equ PORTB3 = 3 ; Port B Data Register bit 3 581.equ PB3 = 3 ; For compatibility 582.equ PORTB4 = 4 ; Port B Data Register bit 4 583.equ PB4 = 4 ; For compatibility 584.equ PORTB5 = 5 ; Port B Data Register bit 5 585.equ PB5 = 5 ; For compatibility 586.equ PORTB6 = 6 ; Port B Data Register bit 6 587.equ PB6 = 6 ; For compatibility 588.equ PORTB7 = 7 ; Port B Data Register bit 7 589.equ PB7 = 7 ; For compatibility 590 591; DDRB - Port B Data Direction Register 592.equ DDB0 = 0 ; Port B Data Direction Register bit 0 593.equ DDB1 = 1 ; Port B Data Direction Register bit 1 594.equ DDB2 = 2 ; Port B Data Direction Register bit 2 595.equ DDB3 = 3 ; Port B Data Direction Register bit 3 596.equ DDB4 = 4 ; Port B Data Direction Register bit 4 597.equ DDB5 = 5 ; Port B Data Direction Register bit 5 598.equ DDB6 = 6 ; Port B Data Direction Register bit 6 599.equ DDB7 = 7 ; Port B Data Direction Register bit 7 600 601; PINB - Port B Input Pins 602.equ PINB0 = 0 ; Port B Input Pins bit 0 603.equ PINB1 = 1 ; Port B Input Pins bit 1 604.equ PINB2 = 2 ; Port B Input Pins bit 2 605.equ PINB3 = 3 ; Port B Input Pins bit 3 606.equ PINB4 = 4 ; Port B Input Pins bit 4 607.equ PINB5 = 5 ; Port B Input Pins bit 5 608.equ PINB6 = 6 ; Port B Input Pins bit 6 609.equ PINB7 = 7 ; Port B Input Pins bit 7 610 611 612; ***** PORTC ************************ 613; PORTC - Port C Data Register 614.equ PORTC0 = 0 ; Port C Data Register bit 0 615.equ PC0 = 0 ; For compatibility 616.equ PORTC1 = 1 ; Port C Data Register bit 1 617.equ PC1 = 1 ; For compatibility 618.equ PORTC2 = 2 ; Port C Data Register bit 2 619.equ PC2 = 2 ; For compatibility 620.equ PORTC3 = 3 ; Port C Data Register bit 3 621.equ PC3 = 3 ; For compatibility 622.equ PORTC4 = 4 ; Port C Data Register bit 4 623.equ PC4 = 4 ; For compatibility 624.equ PORTC5 = 5 ; Port C Data Register bit 5 625.equ PC5 = 5 ; For compatibility 626.equ PORTC6 = 6 ; Port C Data Register bit 6 627.equ PC6 = 6 ; For compatibility 628.equ PORTC7 = 7 ; Port C Data Register bit 7 629.equ PC7 = 7 ; For compatibility 630 631; DDRC - Port C Data Direction Register 632.equ DDC0 = 0 ; Port C Data Direction Register bit 0 633.equ DDC1 = 1 ; Port C Data Direction Register bit 1 634.equ DDC2 = 2 ; Port C Data Direction Register bit 2 635.equ DDC3 = 3 ; Port C Data Direction Register bit 3 636.equ DDC4 = 4 ; Port C Data Direction Register bit 4 637.equ DDC5 = 5 ; Port C Data Direction Register bit 5 638.equ DDC6 = 6 ; Port C Data Direction Register bit 6 639.equ DDC7 = 7 ; Port C Data Direction Register bit 7 640 641; PINC - Port C Input Pins 642.equ PINC0 = 0 ; Port C Input Pins bit 0 643.equ PINC1 = 1 ; Port C Input Pins bit 1 644.equ PINC2 = 2 ; Port C Input Pins bit 2 645.equ PINC3 = 3 ; Port C Input Pins bit 3 646.equ PINC4 = 4 ; Port C Input Pins bit 4 647.equ PINC5 = 5 ; Port C Input Pins bit 5 648.equ PINC6 = 6 ; Port C Input Pins bit 6 649.equ PINC7 = 7 ; Port C Input Pins bit 7 650 651 652; ***** PORTD ************************ 653; PORTD - Port D Data Register 654.equ PORTD0 = 0 ; Port D Data Register bit 0 655.equ PD0 = 0 ; For compatibility 656.equ PORTD1 = 1 ; Port D Data Register bit 1 657.equ PD1 = 1 ; For compatibility 658.equ PORTD2 = 2 ; Port D Data Register bit 2 659.equ PD2 = 2 ; For compatibility 660.equ PORTD3 = 3 ; Port D Data Register bit 3 661.equ PD3 = 3 ; For compatibility 662.equ PORTD4 = 4 ; Port D Data Register bit 4 663.equ PD4 = 4 ; For compatibility 664.equ PORTD5 = 5 ; Port D Data Register bit 5 665.equ PD5 = 5 ; For compatibility 666.equ PORTD6 = 6 ; Port D Data Register bit 6 667.equ PD6 = 6 ; For compatibility 668.equ PORTD7 = 7 ; Port D Data Register bit 7 669.equ PD7 = 7 ; For compatibility 670 671; DDRD - Port D Data Direction Register 672.equ DDD0 = 0 ; Port D Data Direction Register bit 0 673.equ DDD1 = 1 ; Port D Data Direction Register bit 1 674.equ DDD2 = 2 ; Port D Data Direction Register bit 2 675.equ DDD3 = 3 ; Port D Data Direction Register bit 3 676.equ DDD4 = 4 ; Port D Data Direction Register bit 4 677.equ DDD5 = 5 ; Port D Data Direction Register bit 5 678.equ DDD6 = 6 ; Port D Data Direction Register bit 6 679.equ DDD7 = 7 ; Port D Data Direction Register bit 7 680 681; PIND - Port D Input Pins 682.equ PIND0 = 0 ; Port D Input Pins bit 0 683.equ PIND1 = 1 ; Port D Input Pins bit 1 684.equ PIND2 = 2 ; Port D Input Pins bit 2 685.equ PIND3 = 3 ; Port D Input Pins bit 3 686.equ PIND4 = 4 ; Port D Input Pins bit 4 687.equ PIND5 = 5 ; Port D Input Pins bit 5 688.equ PIND6 = 6 ; Port D Input Pins bit 6 689.equ PIND7 = 7 ; Port D Input Pins bit 7 690 691 692; ***** TIMER_COUNTER_0 ************** 693; TCCR0 - Timer/Counter 0 Control Register 694.equ CS00 = 0 ; Clock Select 1 695.equ CS01 = 1 ; Clock Select 1 696.equ CS02 = 2 ; Clock Select 2 697.equ WGM01 = 3 ; Waveform Generation Mode 1 698.equ CTC0 = WGM01 ; For compatibility 699.equ COM00 = 4 ; Compare match Output Mode 0 700.equ COM01 = 5 ; Compare Match Output Mode 1 701.equ WGM00 = 6 ; Waveform Generation Mode 0 702.equ PWM0 = WGM00 ; For compatibility 703.equ FOC0 = 7 ; Force Output Compare 704 705; TCNT0 - Timer/Counter 0 Register 706.equ TCNT0_0 = 0 ; 707.equ TCNT0_1 = 1 ; 708.equ TCNT0_2 = 2 ; 709.equ TCNT0_3 = 3 ; 710.equ TCNT0_4 = 4 ; 711.equ TCNT0_5 = 5 ; 712.equ TCNT0_6 = 6 ; 713.equ TCNT0_7 = 7 ; 714 715; OCR0 - Timer/Counter 0 Output Compare Register 716.equ OCR0_0 = 0 ; 717.equ OCR0_1 = 1 ; 718.equ OCR0_2 = 2 ; 719.equ OCR0_3 = 3 ; 720.equ OCR0_4 = 4 ; 721.equ OCR0_5 = 5 ; 722.equ OCR0_6 = 6 ; 723.equ OCR0_7 = 7 ; 724 725; TIMSK - Timer/Counter Interrupt Mask Register 726.equ OCIE0 = 0 ; Timer/Counter0 Output Compare Match Interrupt register 727.equ TOIE0 = 1 ; Timer/Counter0 Overflow Interrupt Enable 728 729; TIFR - Timer/Counter Interrupt Flag register 730.equ OCF0 = 0 ; Output Compare Flag 0 731.equ TOV0 = 1 ; Timer/Counter0 Overflow Flag 732 733 734; ***** WATCHDOG ********************* 735; WDTCR - Watchdog Timer Control Register 736.equ WDTCSR = WDTCR ; For compatibility 737.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0 738.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1 739.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2 740.equ WDE = 3 ; Watch Dog Enable 741.equ WDCE = 4 ; Watchdog Change Enable 742.equ WDTOE = WDCE ; For compatibility 743 744 745; ***** PORTE ************************ 746; PORTE - Data Register, Port E 747.equ PORTE0 = 0 ; 748.equ PE0 = 0 ; For compatibility 749.equ PORTE1 = 1 ; 750.equ PE1 = 1 ; For compatibility 751.equ PORTE2 = 2 ; 752.equ PE2 = 2 ; For compatibility 753 754; DDRE 755.equ DDE0 = 0 ; 756.equ DDE1 = 1 ; 757.equ DDE2 = 2 ; 758 759; PINE - Input Pins, Port E 760.equ PINE0 = 0 ; 761.equ PINE1 = 1 ; 762.equ PINE2 = 2 ; 763.equ PINE3 = 3 ; 764 765 766; ***** EXTERNAL_INTERRUPT *********** 767; MCUCR - MCU Control Register 768;.equ ISC00 = 0 ; Interrupt Sense Control 0 Bit 0 769;.equ ISC01 = 1 ; Interrupt Sense Control 0 Bit 1 770;.equ ISC10 = 2 ; Interrupt Sense Control 1 Bit 0 771;.equ ISC11 = 3 ; Interrupt Sense Control 1 Bit 1 772 773; EMCUCR - Extended MCU Control Register 774;.equ ISC2 = 0 ; Interrupt Sense Control 2 775 776; GICR - General Interrupt Control Register 777.equ EIMSK = GICR ; For compatibility 778.equ GIMSK = GICR ; For compatibility 779.equ IVCE = 0 ; Interrupt Vector Change Enable 780.equ IVSEL = 1 ; Interrupt Vector Select 781.equ PCIE0 = 3 ; Pin Change Interrupt Enable 0 782.equ PCIE1 = 4 ; Pin Change Interrupt Enable 1 783.equ INT2 = 5 ; External Interrupt Request 2 Enable 784.equ INT0 = 6 ; External Interrupt Request 0 Enable 785.equ INT1 = 7 ; External Interrupt Request 1 Enable 786 787; GIFR - General Interrupt Flag Register 788.equ PCIF0 = 3 ; Pin Change Interrupt Flag 0 789.equ PCIF1 = 4 ; Pin Change Interrupt Flag 1 790.equ INTF2 = 5 ; External Interrupt Flag 2 791.equ INTF0 = 6 ; External Interrupt Flag 0 792.equ INTF1 = 7 ; External Interrupt Flag 1 793 794; PCMSK1 - Pin Change Mask Register 1 795.equ PCINT8 = 0 ; Pin Change Enable Mask 8 796.equ PCINT9 = 1 ; Pin Change Enable Mask 9 797.equ PCINT10 = 2 ; Pin Change Enable Mask 10 798.equ PCINT11 = 3 ; Pin Change Enable Mask 11 799.equ PCINT12 = 4 ; Pin Change Enable Mask 12 800.equ PCINT13 = 5 ; Pin Change Enable Mask 13 801.equ PCINT14 = 6 ; Pin Change Enable Mask 14 802.equ PCINT15 = 7 ; Pin Change Enable Mask 15 803 804; PCMSK0 - Pin Change Enable Mask 805.equ PCINT0 = 0 ; Pin Change Enable Mask 0 806.equ PCINT1 = 1 ; Pin Change Enable Mask 1 807.equ PCINT2 = 2 ; Pin Change Enable Mask 2 808.equ PCINT3 = 3 ; Pin Change Enable Mask 3 809.equ PCINT4 = 4 ; Pin Change Enable Mask 4 810.equ PCINT5 = 5 ; Pin Change Enable Mask 5 811.equ PCINT6 = 6 ; Pin Change Enable Mask 6 812.equ PCINT7 = 7 ; Pin Change Enable Mask 7 813 814 815 816; ***** LOCKSBITS ******************************************************** 817.equ LB1 = 0 ; Lock bit 818.equ LB2 = 1 ; Lock bit 819.equ BLB01 = 2 ; Boot Lock bit 820.equ BLB02 = 3 ; Boot Lock bit 821.equ BLB11 = 4 ; Boot lock bit 822.equ BLB12 = 5 ; Boot lock bit 823 824 825; ***** FUSES ************************************************************ 826; LOW fuse bits 827.equ CKSEL0 = 0 ; Select Clock Source 828.equ CKSEL1 = 1 ; Select Clock Source 829.equ CKSEL2 = 2 ; Select Clock Source 830.equ CKSEL3 = 3 ; Select Clock Source 831.equ SUT0 = 4 ; Select start-up time 832.equ SUT1 = 5 ; Select start-up time 833.equ CKOUT = 6 ; Oscillator options 834.equ CLKDIV8 = 7 ; Divide clock by 8 835 836; HIGH fuse bits 837.equ BOOTRST = 0 ; Select Reset Vector 838.equ BOOTSZ0 = 1 ; Select Boot Size 839.equ BOOTSZ1 = 2 ; Select Boot Size 840.equ EESAVE = 3 ; EEPROM memory is preserved through chip erase 841.equ WDTON = 4 ; Watchdog timer always on 842.equ SPIEN = 5 ; Enable Serial programming and Data Downloading 843.equ JTAGEN = 6 ; Enable JTAG 844.equ OCDEN = 7 ; Enable OCD 845 846; EXTENDED fuse bits 847.equ BODLEVEL0 = 1 ; Brown out detector trigger level 848.equ BODLEVEL1 = 2 ; Brown out detector trigger level 849.equ BODLEVEL2 = 3 ; Brown out detector trigger level 850.equ M161C = 4 ; ATMega 161 compatibility mode 851 852 853 854; ***** CPU REGISTER DEFINITIONS ***************************************** 855.def XH = r27 856.def XL = r26 857.def YH = r29 858.def YL = r28 859.def ZH = r31 860.def ZL = r30 861 862 863 864; ***** DATA MEMORY DECLARATIONS ***************************************** 865.equ FLASHEND = 0x1fff ; Note: Word address 866.equ IOEND = 0x00ff 867.equ SRAM_START = 0x0100 868.equ SRAM_SIZE = 1024 869.equ RAMEND = 0x04ff 870.equ XRAMEND = 0xffff 871.equ E2END = 0x01ff 872.equ EEPROMEND = 0x01ff 873.equ EEADRBITS = 9 874#pragma AVRPART MEMORY PROG_FLASH 16384 875#pragma AVRPART MEMORY EEPROM 512 876#pragma AVRPART MEMORY INT_SRAM SIZE 1024 877#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x100 878 879 880 881; ***** BOOTLOADER DECLARATIONS ****************************************** 882.equ NRWW_START_ADDR = 0x1c00 883.equ NRWW_STOP_ADDR = 0x1fff 884.equ RWW_START_ADDR = 0x0 885.equ RWW_STOP_ADDR = 0x1bff 886.equ PAGESIZE = 64 887.equ FIRSTBOOTSTART = 0x1f80 888.equ SECONDBOOTSTART = 0x1f00 889.equ THIRDBOOTSTART = 0x1e00 890.equ FOURTHBOOTSTART = 0x1c00 891.equ SMALLBOOTSTART = FIRSTBOOTSTART 892.equ LARGEBOOTSTART = FOURTHBOOTSTART 893 894 895 896; ***** INTERRUPT VECTORS ************************************************ 897.equ INT0addr = 0x0002 ; External Interrupt Request 0 898.equ INT1addr = 0x0004 ; External Interrupt Request 1 899.equ INT2addr = 0x0006 ; External Interrupt Request 2 900.equ PCI0addr = 0x0008 ; Pin Change Interrupt Request 0 901.equ PCI1addr = 0x000a ; Pin Change Interrupt Request 1 902.equ ICP3addr = 0x000c ; Timer/Counter3 Capture Event 903.equ OC3Aaddr = 0x000e ; Timer/Counter3 Compare Match A 904.equ OC3Baddr = 0x0010 ; Timer/Counter3 Compare Match B 905.equ OVF3addr = 0x0012 ; Timer/Counter3 Overflow 906.equ OC2addr = 0x0014 ; Timer/Counter2 Compare Match 907.equ OVF2addr = 0x0016 ; Timer/Counter2 Overflow 908.equ ICP1addr = 0x0018 ; Timer/Counter1 Capture Event 909.equ OC1Aaddr = 0x001a ; Timer/Counter1 Compare Match A 910.equ OC1Baddr = 0x001c ; Timer/Counter Compare Match B 911.equ OVF1addr = 0x001e ; Timer/Counter1 Overflow 912.equ OC0addr = 0x0020 ; Timer/Counter0 Compare Match 913.equ OVF0addr = 0x0022 ; Timer/Counter0 Overflow 914.equ SPIaddr = 0x0024 ; SPI Serial Transfer Complete 915.equ URXC0addr = 0x0026 ; USART0, Rx Complete 916.equ URXC1addr = 0x0028 ; USART1, Rx Complete 917.equ UDRE0addr = 0x002a ; USART0 Data register Empty 918.equ UDRE1addr = 0x002c ; USART1, Data register Empty 919.equ UTXC0addr = 0x002e ; USART0, Tx Complete 920.equ UTXC1addr = 0x0030 ; USART1, Tx Complete 921.equ ERDYaddr = 0x0032 ; EEPROM Ready 922.equ ACIaddr = 0x0034 ; Analog Comparator 923.equ SPMRaddr = 0x0036 ; Store Program Memory Read 924 925.equ INT_VECTORS_SIZE = 56 ; size in words 926 927#endif /* _M162DEF_INC_ */ 928 929; ***** END OF FILE ****************************************************** 930