1;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ******************** 2;***** Created: 2005-01-11 10:31 ******* Source: ATmega2561.xml ********** 3;************************************************************************* 4;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y 5;* 6;* Number : AVR000 7;* File Name : "m2561def.inc" 8;* Title : Register/Bit Definitions for the ATmega2561 9;* Date : 2005-01-11 10;* Version : 2.14 11;* Support E-mail : avr@atmel.com 12;* Target MCU : ATmega2561 13;* 14;* DESCRIPTION 15;* When including this file in the assembly program file, all I/O register 16;* names and I/O register bit names appearing in the data book can be used. 17;* In addition, the six registers forming the three data pointers X, Y and 18;* Z have been assigned names XL - ZH. Highest RAM address for Internal 19;* SRAM is also defined 20;* 21;* The Register names are represented by their hexadecimal address. 22;* 23;* The Register Bit names are represented by their bit number (0-7). 24;* 25;* Please observe the difference in using the bit names with instructions 26;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" 27;* (skip if bit in register set/cleared). The following example illustrates 28;* this: 29;* 30;* in r16,PORTB ;read PORTB latch 31;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#) 32;* out PORTB,r16 ;output to PORTB 33;* 34;* in r16,TIFR ;read the Timer Interrupt Flag Register 35;* sbrc r16,TOV0 ;test the overflow flag (use bit#) 36;* rjmp TOV0_is_set ;jump if set 37;* ... ;otherwise do something else 38;************************************************************************* 39 40#ifndef _M2561DEF_INC_ 41#define _M2561DEF_INC_ 42 43 44#pragma partinc 0 45 46; ***** SPECIFY DEVICE *************************************************** 47.device ATmega2561 48#pragma AVRPART ADMIN PART_NAME ATmega2561 49.equ SIGNATURE_000 = 0x1e 50.equ SIGNATURE_001 = 0x98 51.equ SIGNATURE_002 = 0x02 52 53#pragma AVRPART CORE CORE_VERSION V3 54 55 56; ***** I/O REGISTER DEFINITIONS ***************************************** 57; NOTE: 58; Definitions marked "MEMORY MAPPED"are extended I/O ports 59; and cannot be used with IN/OUT instructions 60.equ UDR3 = 0x136 ; MEMORY MAPPED 61.equ UBRR3H = 0x135 ; MEMORY MAPPED 62.equ UBRR3L = 0x134 ; MEMORY MAPPED 63.equ UCSR3C = 0x132 ; MEMORY MAPPED 64.equ UCSR3B = 0x131 ; MEMORY MAPPED 65.equ UCSR3A = 0x130 ; MEMORY MAPPED 66.equ OCR5CH = 0x12d ; MEMORY MAPPED 67.equ OCR5CL = 0x12c ; MEMORY MAPPED 68.equ OCR5BH = 0x12b ; MEMORY MAPPED 69.equ OCR5BL = 0x12a ; MEMORY MAPPED 70.equ OCR5AH = 0x129 ; MEMORY MAPPED 71.equ OCR5AL = 0x128 ; MEMORY MAPPED 72.equ ICR5H = 0x127 ; MEMORY MAPPED 73.equ ICR5L = 0x126 ; MEMORY MAPPED 74.equ TCNT5H = 0x125 ; MEMORY MAPPED 75.equ TCNT5L = 0x124 ; MEMORY MAPPED 76.equ TCCR5C = 0x122 ; MEMORY MAPPED 77.equ TCCR5B = 0x121 ; MEMORY MAPPED 78.equ TCCR5A = 0x120 ; MEMORY MAPPED 79.equ PORTL = 0x10b ; MEMORY MAPPED 80.equ DDRL = 0x10a ; MEMORY MAPPED 81.equ PINL = 0x109 ; MEMORY MAPPED 82.equ PORTK = 0x108 ; MEMORY MAPPED 83.equ DDRK = 0x107 ; MEMORY MAPPED 84.equ PINK = 0x106 ; MEMORY MAPPED 85.equ PORTJ = 0x105 ; MEMORY MAPPED 86.equ DDRJ = 0x104 ; MEMORY MAPPED 87.equ PINJ = 0x103 ; MEMORY MAPPED 88.equ PORTH = 0x102 ; MEMORY MAPPED 89.equ DDRH = 0x101 ; MEMORY MAPPED 90.equ PINH = 0x100 ; MEMORY MAPPED 91.equ UDR2 = 0xd6 ; MEMORY MAPPED 92.equ UBRR2H = 0xd5 ; MEMORY MAPPED 93.equ UBRR2L = 0xd4 ; MEMORY MAPPED 94.equ UCSR2C = 0xd2 ; MEMORY MAPPED 95.equ UCSR2B = 0xd1 ; MEMORY MAPPED 96.equ UCSR2A = 0xd0 ; MEMORY MAPPED 97.equ UDR1 = 0xce ; MEMORY MAPPED 98.equ UBRR1H = 0xcd ; MEMORY MAPPED 99.equ UBRR1L = 0xcc ; MEMORY MAPPED 100.equ UCSR1C = 0xca ; MEMORY MAPPED 101.equ UCSR1B = 0xc9 ; MEMORY MAPPED 102.equ UCSR1A = 0xc8 ; MEMORY MAPPED 103.equ UDR0 = 0xc6 ; MEMORY MAPPED 104.equ UBRR0H = 0xc5 ; MEMORY MAPPED 105.equ UBRR0L = 0xc4 ; MEMORY MAPPED 106.equ UCSR0C = 0xc2 ; MEMORY MAPPED 107.equ UCSR0B = 0xc1 ; MEMORY MAPPED 108.equ UCSR0A = 0xc0 ; MEMORY MAPPED 109.equ TWAMR = 0xbd ; MEMORY MAPPED 110.equ TWCR = 0xbc ; MEMORY MAPPED 111.equ TWDR = 0xbb ; MEMORY MAPPED 112.equ TWAR = 0xba ; MEMORY MAPPED 113.equ TWSR = 0xb9 ; MEMORY MAPPED 114.equ TWBR = 0xb8 ; MEMORY MAPPED 115.equ ASSR = 0xb6 ; MEMORY MAPPED 116.equ OCR2B = 0xb4 ; MEMORY MAPPED 117.equ OCR2A = 0xb3 ; MEMORY MAPPED 118.equ TCNT2 = 0xb2 ; MEMORY MAPPED 119.equ TCCR2B = 0xb1 ; MEMORY MAPPED 120.equ TCCR2A = 0xb0 ; MEMORY MAPPED 121.equ OCR4CH = 0xad ; MEMORY MAPPED 122.equ OCR4CL = 0xac ; MEMORY MAPPED 123.equ OCR4BH = 0xab ; MEMORY MAPPED 124.equ OCR4BL = 0xaa ; MEMORY MAPPED 125.equ OCR4AH = 0xa9 ; MEMORY MAPPED 126.equ OCR4AL = 0xa8 ; MEMORY MAPPED 127.equ ICR4H = 0xa7 ; MEMORY MAPPED 128.equ ICR4L = 0xa6 ; MEMORY MAPPED 129.equ TCNT4H = 0xa5 ; MEMORY MAPPED 130.equ TCNT4L = 0xa4 ; MEMORY MAPPED 131.equ TCCR4C = 0xa2 ; MEMORY MAPPED 132.equ TCCR4B = 0xa1 ; MEMORY MAPPED 133.equ TCCR4A = 0xa0 ; MEMORY MAPPED 134.equ OCR3CH = 0x9d ; MEMORY MAPPED 135.equ OCR3CL = 0x9c ; MEMORY MAPPED 136.equ OCR3BH = 0x9b ; MEMORY MAPPED 137.equ OCR3BL = 0x9a ; MEMORY MAPPED 138.equ OCR3AH = 0x99 ; MEMORY MAPPED 139.equ OCR3AL = 0x98 ; MEMORY MAPPED 140.equ ICR3H = 0x97 ; MEMORY MAPPED 141.equ ICR3L = 0x96 ; MEMORY MAPPED 142.equ TCNT3H = 0x95 ; MEMORY MAPPED 143.equ TCNT3L = 0x94 ; MEMORY MAPPED 144.equ TCCR3C = 0x92 ; MEMORY MAPPED 145.equ TCCR3B = 0x91 ; MEMORY MAPPED 146.equ TCCR3A = 0x90 ; MEMORY MAPPED 147.equ OCR1CH = 0x8d ; MEMORY MAPPED 148.equ OCR1CL = 0x8c ; MEMORY MAPPED 149.equ OCR1BH = 0x8b ; MEMORY MAPPED 150.equ OCR1BL = 0x8a ; MEMORY MAPPED 151.equ OCR1AH = 0x89 ; MEMORY MAPPED 152.equ OCR1AL = 0x88 ; MEMORY MAPPED 153.equ ICR1H = 0x87 ; MEMORY MAPPED 154.equ ICR1L = 0x86 ; MEMORY MAPPED 155.equ TCNT1H = 0x85 ; MEMORY MAPPED 156.equ TCNT1L = 0x84 ; MEMORY MAPPED 157.equ TCCR1C = 0x82 ; MEMORY MAPPED 158.equ TCCR1B = 0x81 ; MEMORY MAPPED 159.equ TCCR1A = 0x80 ; MEMORY MAPPED 160.equ DIDR1 = 0x7f ; MEMORY MAPPED 161.equ DIDR0 = 0x7e ; MEMORY MAPPED 162.equ DIDR2 = 0x7d ; MEMORY MAPPED 163.equ ADMUX = 0x7c ; MEMORY MAPPED 164.equ ADCSRB = 0x7b ; MEMORY MAPPED 165.equ ADCSRA = 0x7a ; MEMORY MAPPED 166.equ ADCH = 0x79 ; MEMORY MAPPED 167.equ ADCL = 0x78 ; MEMORY MAPPED 168.equ XMCRB = 0x75 ; MEMORY MAPPED 169.equ XMCRA = 0x74 ; MEMORY MAPPED 170.equ TIMSK5 = 0x73 ; MEMORY MAPPED 171.equ TIMSK4 = 0x72 ; MEMORY MAPPED 172.equ TIMSK3 = 0x71 ; MEMORY MAPPED 173.equ TIMSK2 = 0x70 ; MEMORY MAPPED 174.equ TIMSK1 = 0x6f ; MEMORY MAPPED 175.equ TIMSK0 = 0x6e ; MEMORY MAPPED 176.equ PCMSK2 = 0x6d ; MEMORY MAPPED 177.equ PCMSK1 = 0x6c ; MEMORY MAPPED 178.equ PCMSK0 = 0x6b ; MEMORY MAPPED 179.equ EICRB = 0x6a ; MEMORY MAPPED 180.equ EICRA = 0x69 ; MEMORY MAPPED 181.equ PCICR = 0x68 ; MEMORY MAPPED 182.equ OSCCAL = 0x66 ; MEMORY MAPPED 183.equ PRR1 = 0x65 ; MEMORY MAPPED 184.equ PRR0 = 0x64 ; MEMORY MAPPED 185.equ CLKPR = 0x61 ; MEMORY MAPPED 186.equ WDTCSR = 0x60 ; MEMORY MAPPED 187.equ SREG = 0x3f 188.equ SPH = 0x3e 189.equ SPL = 0x3d 190.equ EIND = 0x3c 191.equ RAMPZ = 0x3b 192.equ SPMCSR = 0x37 193.equ MCUCR = 0x35 194.equ MCUSR = 0x34 195.equ SMCR = 0x33 196.equ OCDR = 0x31 197.equ ACSR = 0x30 198.equ SPDR = 0x2e 199.equ SPSR = 0x2d 200.equ SPCR = 0x2c 201.equ GPIOR2 = 0x2b 202.equ GPIOR1 = 0x2a 203.equ OCR0B = 0x28 204.equ OCR0A = 0x27 205.equ TCNT0 = 0x26 206.equ TCCR0B = 0x25 207.equ TCCR0A = 0x24 208.equ GTCCR = 0x23 209.equ EEARH = 0x22 210.equ EEARL = 0x21 211.equ EEDR = 0x20 212.equ EECR = 0x1f 213.equ GPIOR0 = 0x1e 214.equ EIMSK = 0x1d 215.equ EIFR = 0x1c 216.equ PCIFR = 0x1b 217.equ TIFR5 = 0x1a 218.equ TIFR4 = 0x19 219.equ TIFR3 = 0x18 220.equ TIFR2 = 0x17 221.equ TIFR1 = 0x16 222.equ TIFR0 = 0x15 223.equ PORTG = 0x14 224.equ DDRG = 0x13 225.equ PING = 0x12 226.equ PORTF = 0x11 227.equ DDRF = 0x10 228.equ PINF = 0x0f 229.equ PORTE = 0x0e 230.equ DDRE = 0x0d 231.equ PINE = 0x0c 232.equ PORTD = 0x0b 233.equ DDRD = 0x0a 234.equ PIND = 0x09 235.equ PORTC = 0x08 236.equ DDRC = 0x07 237.equ PINC = 0x06 238.equ PORTB = 0x05 239.equ DDRB = 0x04 240.equ PINB = 0x03 241.equ PORTA = 0x02 242.equ DDRA = 0x01 243.equ PINA = 0x00 244 245 246; ***** BIT DEFINITIONS ************************************************** 247 248; ***** ANALOG_COMPARATOR ************ 249; ADCSRB - ADC Control and Status Register B 250.equ ACME = 6 ; Analog Comparator Multiplexer Enable 251 252; ACSR - Analog Comparator Control And Status Register 253.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0 254.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1 255.equ ACIC = 2 ; Analog Comparator Input Capture Enable 256.equ ACIE = 3 ; Analog Comparator Interrupt Enable 257.equ ACI = 4 ; Analog Comparator Interrupt Flag 258.equ ACO = 5 ; Analog Compare Output 259.equ ACBG = 6 ; Analog Comparator Bandgap Select 260.equ ACD = 7 ; Analog Comparator Disable 261 262; DIDR1 - Digital Input Disable Register 1 263.equ AIN0D = 0 ; AIN0 Digital Input Disable 264.equ AIN1D = 1 ; AIN1 Digital Input Disable 265 266 267; ***** USART0 *********************** 268; UDR0 - USART I/O Data Register 269.equ UDR0_0 = 0 ; USART I/O Data Register bit 0 270.equ UDR0_1 = 1 ; USART I/O Data Register bit 1 271.equ UDR0_2 = 2 ; USART I/O Data Register bit 2 272.equ UDR0_3 = 3 ; USART I/O Data Register bit 3 273.equ UDR0_4 = 4 ; USART I/O Data Register bit 4 274.equ UDR0_5 = 5 ; USART I/O Data Register bit 5 275.equ UDR0_6 = 6 ; USART I/O Data Register bit 6 276.equ UDR0_7 = 7 ; USART I/O Data Register bit 7 277 278; UCSR0A - USART Control and Status Register A 279.equ MPCM0 = 0 ; Multi-processor Communication Mode 280.equ U2X0 = 1 ; Double the USART transmission speed 281.equ UPE0 = 2 ; Parity Error 282.equ DOR0 = 3 ; Data overRun 283.equ FE0 = 4 ; Framing Error 284.equ UDRE0 = 5 ; USART Data Register Empty 285.equ TXC0 = 6 ; USART Transmitt Complete 286.equ RXC0 = 7 ; USART Receive Complete 287 288; UCSR0B - USART Control and Status Register B 289.equ TXB80 = 0 ; Transmit Data Bit 8 290.equ RXB80 = 1 ; Receive Data Bit 8 291.equ UCSZ02 = 2 ; Character Size 292.equ TXEN0 = 3 ; Transmitter Enable 293.equ RXEN0 = 4 ; Receiver Enable 294.equ UDRIE0 = 5 ; USART Data register Empty Interrupt Enable 295.equ TXCIE0 = 6 ; TX Complete Interrupt Enable 296.equ RXCIE0 = 7 ; RX Complete Interrupt Enable 297 298; UCSR0C - USART Control and Status Register C 299.equ UCPOL0 = 0 ; Clock Polarity 300.equ UCSZ00 = 1 ; Character Size 301.equ UCPHA0 = UCSZ00 ; For compatibility 302.equ UCSZ01 = 2 ; Character Size 303.equ UDORD0 = UCSZ01 ; For compatibility 304.equ USBS0 = 3 ; Stop Bit Select 305.equ UPM00 = 4 ; Parity Mode Bit 0 306.equ UPM01 = 5 ; Parity Mode Bit 1 307.equ UMSEL00 = 6 ; USART Mode Select 308.equ UMSEL0 = UMSEL00 ; For compatibility 309.equ UMSEL01 = 7 ; USART Mode Select 310.equ UMSEL1 = UMSEL01 ; For compatibility 311 312 313; ***** TWI ************************** 314; TWAMR - TWI (Slave) Address Mask Register 315.equ TWAM0 = 1 ; 316.equ TWAMR0 = TWAM0 ; For compatibility 317.equ TWAM1 = 2 ; 318.equ TWAMR1 = TWAM1 ; For compatibility 319.equ TWAM2 = 3 ; 320.equ TWAMR2 = TWAM2 ; For compatibility 321.equ TWAM3 = 4 ; 322.equ TWAMR3 = TWAM3 ; For compatibility 323.equ TWAM4 = 5 ; 324.equ TWAMR4 = TWAM4 ; For compatibility 325.equ TWAM5 = 6 ; 326.equ TWAMR5 = TWAM5 ; For compatibility 327.equ TWAM6 = 7 ; 328.equ TWAMR6 = TWAM6 ; For compatibility 329 330; TWBR - TWI Bit Rate register 331.equ TWBR0 = 0 ; 332.equ TWBR1 = 1 ; 333.equ TWBR2 = 2 ; 334.equ TWBR3 = 3 ; 335.equ TWBR4 = 4 ; 336.equ TWBR5 = 5 ; 337.equ TWBR6 = 6 ; 338.equ TWBR7 = 7 ; 339 340; TWCR - TWI Control Register 341.equ TWIE = 0 ; TWI Interrupt Enable 342.equ TWEN = 2 ; TWI Enable Bit 343.equ TWWC = 3 ; TWI Write Collition Flag 344.equ TWSTO = 4 ; TWI Stop Condition Bit 345.equ TWSTA = 5 ; TWI Start Condition Bit 346.equ TWEA = 6 ; TWI Enable Acknowledge Bit 347.equ TWINT = 7 ; TWI Interrupt Flag 348 349; TWSR - TWI Status Register 350.equ TWPS0 = 0 ; TWI Prescaler 351.equ TWPS1 = 1 ; TWI Prescaler 352.equ TWS3 = 3 ; TWI Status 353.equ TWS4 = 4 ; TWI Status 354.equ TWS5 = 5 ; TWI Status 355.equ TWS6 = 6 ; TWI Status 356.equ TWS7 = 7 ; TWI Status 357 358; TWDR - TWI Data register 359.equ TWD0 = 0 ; TWI Data Register Bit 0 360.equ TWD1 = 1 ; TWI Data Register Bit 1 361.equ TWD2 = 2 ; TWI Data Register Bit 2 362.equ TWD3 = 3 ; TWI Data Register Bit 3 363.equ TWD4 = 4 ; TWI Data Register Bit 4 364.equ TWD5 = 5 ; TWI Data Register Bit 5 365.equ TWD6 = 6 ; TWI Data Register Bit 6 366.equ TWD7 = 7 ; TWI Data Register Bit 7 367 368; TWAR - TWI (Slave) Address register 369.equ TWGCE = 0 ; TWI General Call Recognition Enable Bit 370.equ TWA0 = 1 ; TWI (Slave) Address register Bit 0 371.equ TWA1 = 2 ; TWI (Slave) Address register Bit 1 372.equ TWA2 = 3 ; TWI (Slave) Address register Bit 2 373.equ TWA3 = 4 ; TWI (Slave) Address register Bit 3 374.equ TWA4 = 5 ; TWI (Slave) Address register Bit 4 375.equ TWA5 = 6 ; TWI (Slave) Address register Bit 5 376.equ TWA6 = 7 ; TWI (Slave) Address register Bit 6 377 378 379; ***** SPI ************************** 380; SPDR - SPI Data Register 381.equ SPDR0 = 0 ; SPI Data Register bit 0 382.equ SPDR1 = 1 ; SPI Data Register bit 1 383.equ SPDR2 = 2 ; SPI Data Register bit 2 384.equ SPDR3 = 3 ; SPI Data Register bit 3 385.equ SPDR4 = 4 ; SPI Data Register bit 4 386.equ SPDR5 = 5 ; SPI Data Register bit 5 387.equ SPDR6 = 6 ; SPI Data Register bit 6 388.equ SPDR7 = 7 ; SPI Data Register bit 7 389 390; SPSR - SPI Status Register 391.equ SPI2X = 0 ; Double SPI Speed Bit 392.equ WCOL = 6 ; Write Collision Flag 393.equ SPIF = 7 ; SPI Interrupt Flag 394 395; SPCR - SPI Control Register 396.equ SPR0 = 0 ; SPI Clock Rate Select 0 397.equ SPR1 = 1 ; SPI Clock Rate Select 1 398.equ CPHA = 2 ; Clock Phase 399.equ CPOL = 3 ; Clock polarity 400.equ MSTR = 4 ; Master/Slave Select 401.equ DORD = 5 ; Data Order 402.equ SPE = 6 ; SPI Enable 403.equ SPIE = 7 ; SPI Interrupt Enable 404 405 406; ***** PORTA ************************ 407; PORTA - Port A Data Register 408.equ PORTA0 = 0 ; Port A Data Register bit 0 409.equ PA0 = 0 ; For compatibility 410.equ PORTA1 = 1 ; Port A Data Register bit 1 411.equ PA1 = 1 ; For compatibility 412.equ PORTA2 = 2 ; Port A Data Register bit 2 413.equ PA2 = 2 ; For compatibility 414.equ PORTA3 = 3 ; Port A Data Register bit 3 415.equ PA3 = 3 ; For compatibility 416.equ PORTA4 = 4 ; Port A Data Register bit 4 417.equ PA4 = 4 ; For compatibility 418.equ PORTA5 = 5 ; Port A Data Register bit 5 419.equ PA5 = 5 ; For compatibility 420.equ PORTA6 = 6 ; Port A Data Register bit 6 421.equ PA6 = 6 ; For compatibility 422.equ PORTA7 = 7 ; Port A Data Register bit 7 423.equ PA7 = 7 ; For compatibility 424 425; DDRA - Port A Data Direction Register 426.equ DDA0 = 0 ; Data Direction Register, Port A, bit 0 427.equ DDA1 = 1 ; Data Direction Register, Port A, bit 1 428.equ DDA2 = 2 ; Data Direction Register, Port A, bit 2 429.equ DDA3 = 3 ; Data Direction Register, Port A, bit 3 430.equ DDA4 = 4 ; Data Direction Register, Port A, bit 4 431.equ DDA5 = 5 ; Data Direction Register, Port A, bit 5 432.equ DDA6 = 6 ; Data Direction Register, Port A, bit 6 433.equ DDA7 = 7 ; Data Direction Register, Port A, bit 7 434 435; PINA - Port A Input Pins 436.equ PINA0 = 0 ; Input Pins, Port A bit 0 437.equ PINA1 = 1 ; Input Pins, Port A bit 1 438.equ PINA2 = 2 ; Input Pins, Port A bit 2 439.equ PINA3 = 3 ; Input Pins, Port A bit 3 440.equ PINA4 = 4 ; Input Pins, Port A bit 4 441.equ PINA5 = 5 ; Input Pins, Port A bit 5 442.equ PINA6 = 6 ; Input Pins, Port A bit 6 443.equ PINA7 = 7 ; Input Pins, Port A bit 7 444 445 446; ***** PORTB ************************ 447; PORTB - Port B Data Register 448.equ PORTB0 = 0 ; Port B Data Register bit 0 449.equ PB0 = 0 ; For compatibility 450.equ PORTB1 = 1 ; Port B Data Register bit 1 451.equ PB1 = 1 ; For compatibility 452.equ PORTB2 = 2 ; Port B Data Register bit 2 453.equ PB2 = 2 ; For compatibility 454.equ PORTB3 = 3 ; Port B Data Register bit 3 455.equ PB3 = 3 ; For compatibility 456.equ PORTB4 = 4 ; Port B Data Register bit 4 457.equ PB4 = 4 ; For compatibility 458.equ PORTB5 = 5 ; Port B Data Register bit 5 459.equ PB5 = 5 ; For compatibility 460.equ PORTB6 = 6 ; Port B Data Register bit 6 461.equ PB6 = 6 ; For compatibility 462.equ PORTB7 = 7 ; Port B Data Register bit 7 463.equ PB7 = 7 ; For compatibility 464 465; DDRB - Port B Data Direction Register 466.equ DDB0 = 0 ; Port B Data Direction Register bit 0 467.equ DDB1 = 1 ; Port B Data Direction Register bit 1 468.equ DDB2 = 2 ; Port B Data Direction Register bit 2 469.equ DDB3 = 3 ; Port B Data Direction Register bit 3 470.equ DDB4 = 4 ; Port B Data Direction Register bit 4 471.equ DDB5 = 5 ; Port B Data Direction Register bit 5 472.equ DDB6 = 6 ; Port B Data Direction Register bit 6 473.equ DDB7 = 7 ; Port B Data Direction Register bit 7 474 475; PINB - Port B Input Pins 476.equ PINB0 = 0 ; Port B Input Pins bit 0 477.equ PINB1 = 1 ; Port B Input Pins bit 1 478.equ PINB2 = 2 ; Port B Input Pins bit 2 479.equ PINB3 = 3 ; Port B Input Pins bit 3 480.equ PINB4 = 4 ; Port B Input Pins bit 4 481.equ PINB5 = 5 ; Port B Input Pins bit 5 482.equ PINB6 = 6 ; Port B Input Pins bit 6 483.equ PINB7 = 7 ; Port B Input Pins bit 7 484 485 486; ***** PORTC ************************ 487; PORTC - Port C Data Register 488.equ PORTC0 = 0 ; Port C Data Register bit 0 489.equ PC0 = 0 ; For compatibility 490.equ PORTC1 = 1 ; Port C Data Register bit 1 491.equ PC1 = 1 ; For compatibility 492.equ PORTC2 = 2 ; Port C Data Register bit 2 493.equ PC2 = 2 ; For compatibility 494.equ PORTC3 = 3 ; Port C Data Register bit 3 495.equ PC3 = 3 ; For compatibility 496.equ PORTC4 = 4 ; Port C Data Register bit 4 497.equ PC4 = 4 ; For compatibility 498.equ PORTC5 = 5 ; Port C Data Register bit 5 499.equ PC5 = 5 ; For compatibility 500.equ PORTC6 = 6 ; Port C Data Register bit 6 501.equ PC6 = 6 ; For compatibility 502.equ PORTC7 = 7 ; Port C Data Register bit 7 503.equ PC7 = 7 ; For compatibility 504 505; DDRC - Port C Data Direction Register 506.equ DDC0 = 0 ; Port C Data Direction Register bit 0 507.equ DDC1 = 1 ; Port C Data Direction Register bit 1 508.equ DDC2 = 2 ; Port C Data Direction Register bit 2 509.equ DDC3 = 3 ; Port C Data Direction Register bit 3 510.equ DDC4 = 4 ; Port C Data Direction Register bit 4 511.equ DDC5 = 5 ; Port C Data Direction Register bit 5 512.equ DDC6 = 6 ; Port C Data Direction Register bit 6 513.equ DDC7 = 7 ; Port C Data Direction Register bit 7 514 515; PINC - Port C Input Pins 516.equ PINC0 = 0 ; Port C Input Pins bit 0 517.equ PINC1 = 1 ; Port C Input Pins bit 1 518.equ PINC2 = 2 ; Port C Input Pins bit 2 519.equ PINC3 = 3 ; Port C Input Pins bit 3 520.equ PINC4 = 4 ; Port C Input Pins bit 4 521.equ PINC5 = 5 ; Port C Input Pins bit 5 522.equ PINC6 = 6 ; Port C Input Pins bit 6 523.equ PINC7 = 7 ; Port C Input Pins bit 7 524 525 526; ***** PORTD ************************ 527; PORTD - Port D Data Register 528.equ PORTD0 = 0 ; Port D Data Register bit 0 529.equ PD0 = 0 ; For compatibility 530.equ PORTD1 = 1 ; Port D Data Register bit 1 531.equ PD1 = 1 ; For compatibility 532.equ PORTD2 = 2 ; Port D Data Register bit 2 533.equ PD2 = 2 ; For compatibility 534.equ PORTD3 = 3 ; Port D Data Register bit 3 535.equ PD3 = 3 ; For compatibility 536.equ PORTD4 = 4 ; Port D Data Register bit 4 537.equ PD4 = 4 ; For compatibility 538.equ PORTD5 = 5 ; Port D Data Register bit 5 539.equ PD5 = 5 ; For compatibility 540.equ PORTD6 = 6 ; Port D Data Register bit 6 541.equ PD6 = 6 ; For compatibility 542.equ PORTD7 = 7 ; Port D Data Register bit 7 543.equ PD7 = 7 ; For compatibility 544 545; DDRD - Port D Data Direction Register 546.equ DDD0 = 0 ; Port D Data Direction Register bit 0 547.equ DDD1 = 1 ; Port D Data Direction Register bit 1 548.equ DDD2 = 2 ; Port D Data Direction Register bit 2 549.equ DDD3 = 3 ; Port D Data Direction Register bit 3 550.equ DDD4 = 4 ; Port D Data Direction Register bit 4 551.equ DDD5 = 5 ; Port D Data Direction Register bit 5 552.equ DDD6 = 6 ; Port D Data Direction Register bit 6 553.equ DDD7 = 7 ; Port D Data Direction Register bit 7 554 555; PIND - Port D Input Pins 556.equ PIND0 = 0 ; Port D Input Pins bit 0 557.equ PIND1 = 1 ; Port D Input Pins bit 1 558.equ PIND2 = 2 ; Port D Input Pins bit 2 559.equ PIND3 = 3 ; Port D Input Pins bit 3 560.equ PIND4 = 4 ; Port D Input Pins bit 4 561.equ PIND5 = 5 ; Port D Input Pins bit 5 562.equ PIND6 = 6 ; Port D Input Pins bit 6 563.equ PIND7 = 7 ; Port D Input Pins bit 7 564 565 566; ***** PORTE ************************ 567; PORTE - Data Register, Port E 568.equ PORTE0 = 0 ; 569.equ PE0 = 0 ; For compatibility 570.equ PORTE1 = 1 ; 571.equ PE1 = 1 ; For compatibility 572.equ PORTE2 = 2 ; 573.equ PE2 = 2 ; For compatibility 574.equ PORTE3 = 3 ; 575.equ PE3 = 3 ; For compatibility 576.equ PORTE4 = 4 ; 577.equ PE4 = 4 ; For compatibility 578.equ PORTE5 = 5 ; 579.equ PE5 = 5 ; For compatibility 580.equ PORTE6 = 6 ; 581.equ PE6 = 6 ; For compatibility 582.equ PORTE7 = 7 ; 583.equ PE7 = 7 ; For compatibility 584 585; DDRE - Data Direction Register, Port E 586.equ DDE0 = 0 ; 587.equ DDE1 = 1 ; 588.equ DDE2 = 2 ; 589.equ DDE3 = 3 ; 590.equ DDE4 = 4 ; 591.equ DDE5 = 5 ; 592.equ DDE6 = 6 ; 593.equ DDE7 = 7 ; 594 595; PINE - Input Pins, Port E 596.equ PINE0 = 0 ; 597.equ PINE1 = 1 ; 598.equ PINE2 = 2 ; 599.equ PINE3 = 3 ; 600.equ PINE4 = 4 ; 601.equ PINE5 = 5 ; 602.equ PINE6 = 6 ; 603.equ PINE7 = 7 ; 604 605 606; ***** PORTF ************************ 607; PORTF - Data Register, Port F 608.equ PORTF0 = 0 ; 609.equ PF0 = 0 ; For compatibility 610.equ PORTF1 = 1 ; 611.equ PF1 = 1 ; For compatibility 612.equ PORTF2 = 2 ; 613.equ PF2 = 2 ; For compatibility 614.equ PORTF3 = 3 ; 615.equ PF3 = 3 ; For compatibility 616.equ PORTF4 = 4 ; 617.equ PF4 = 4 ; For compatibility 618.equ PORTF5 = 5 ; 619.equ PF5 = 5 ; For compatibility 620.equ PORTF6 = 6 ; 621.equ PF6 = 6 ; For compatibility 622.equ PORTF7 = 7 ; 623.equ PF7 = 7 ; For compatibility 624 625; DDRF - Data Direction Register, Port F 626.equ DDF0 = 0 ; 627.equ DDF1 = 1 ; 628.equ DDF2 = 2 ; 629.equ DDF3 = 3 ; 630.equ DDF4 = 4 ; 631.equ DDF5 = 5 ; 632.equ DDF6 = 6 ; 633.equ DDF7 = 7 ; 634 635; PINF - Input Pins, Port F 636.equ PINF0 = 0 ; 637.equ PINF1 = 1 ; 638.equ PINF2 = 2 ; 639.equ PINF3 = 3 ; 640.equ PINF4 = 4 ; 641.equ PINF5 = 5 ; 642.equ PINF6 = 6 ; 643.equ PINF7 = 7 ; 644 645 646; ***** PORTG ************************ 647; PORTG - Data Register, Port G 648.equ PORTG0 = 0 ; 649.equ PG0 = 0 ; For compatibility 650.equ PORTG1 = 1 ; 651.equ PG1 = 1 ; For compatibility 652.equ PORTG2 = 2 ; 653.equ PG2 = 2 ; For compatibility 654.equ PORTG3 = 3 ; 655.equ PG3 = 3 ; For compatibility 656.equ PORTG4 = 4 ; 657.equ PG4 = 4 ; For compatibility 658.equ PORTG5 = 5 ; 659.equ PG5 = 5 ; For compatibility 660 661; DDRG 662.equ DDG0 = 0 ; 663.equ DDG1 = 1 ; 664.equ DDG2 = 2 ; 665.equ DDG3 = 3 ; 666.equ DDG4 = 4 ; 667.equ DDG5 = 5 ; 668 669; PING - Input Pins, Port G 670.equ PING0 = 0 ; 671.equ PING1 = 1 ; 672.equ PING2 = 2 ; 673.equ PING3 = 3 ; 674.equ PING4 = 4 ; 675.equ PING5 = 5 ; 676 677 678; ***** TIMER_COUNTER_0 ************** 679; TIMSK0 - Timer/Counter0 Interrupt Mask Register 680.equ TOIE0 = 0 ; Timer/Counter0 Overflow Interrupt Enable 681.equ OCIE0A = 1 ; Timer/Counter0 Output Compare Match A Interrupt Enable 682.equ OCIE0B = 2 ; Timer/Counter0 Output Compare Match B Interrupt Enable 683 684; TIFR0 - Timer/Counter0 Interrupt Flag register 685.equ TOV0 = 0 ; Timer/Counter0 Overflow Flag 686.equ OCF0A = 1 ; Timer/Counter0 Output Compare Flag 0A 687.equ OCF0B = 2 ; Timer/Counter0 Output Compare Flag 0B 688 689; TCCR0A - Timer/Counter Control Register A 690.equ WGM00 = 0 ; Waveform Generation Mode 691.equ WGM01 = 1 ; Waveform Generation Mode 692.equ COM0B0 = 4 ; Compare Output Mode, Fast PWm 693.equ COM0B1 = 5 ; Compare Output Mode, Fast PWm 694.equ COM0A0 = 6 ; Compare Output Mode, Phase Correct PWM Mode 695.equ COM0A1 = 7 ; Compare Output Mode, Phase Correct PWM Mode 696 697; TCCR0B - Timer/Counter Control Register B 698.equ CS00 = 0 ; Clock Select 699.equ CS01 = 1 ; Clock Select 700.equ CS02 = 2 ; Clock Select 701.equ WGM02 = 3 ; 702.equ FOC0B = 6 ; Force Output Compare B 703.equ FOC0A = 7 ; Force Output Compare A 704 705; TCNT0 - Timer/Counter0 706.equ TCNT0_0 = 0 ; 707.equ TCNT0_1 = 1 ; 708.equ TCNT0_2 = 2 ; 709.equ TCNT0_3 = 3 ; 710.equ TCNT0_4 = 4 ; 711.equ TCNT0_5 = 5 ; 712.equ TCNT0_6 = 6 ; 713.equ TCNT0_7 = 7 ; 714 715; OCR0A - Timer/Counter0 Output Compare Register 716.equ OCROA_0 = 0 ; 717.equ OCROA_1 = 1 ; 718.equ OCROA_2 = 2 ; 719.equ OCROA_3 = 3 ; 720.equ OCROA_4 = 4 ; 721.equ OCROA_5 = 5 ; 722.equ OCROA_6 = 6 ; 723.equ OCROA_7 = 7 ; 724 725; OCR0B - Timer/Counter0 Output Compare Register 726.equ OCR0B_0 = 0 ; 727.equ OCR0B_1 = 1 ; 728.equ OCR0B_2 = 2 ; 729.equ OCR0B_3 = 3 ; 730.equ OCR0B_4 = 4 ; 731.equ OCR0B_5 = 5 ; 732.equ OCR0B_6 = 6 ; 733.equ OCR0B_7 = 7 ; 734 735; GTCCR - General Timer/Counter Control Register 736.equ PSRSYNC = 0 ; Prescaler Reset Timer/Counter1 and Timer/Counter0 737.equ PSR10 = PSRSYNC ; For compatibility 738.equ TSM = 7 ; Timer/Counter Synchronization Mode 739 740 741; ***** TIMER_COUNTER_2 ************** 742; TIMSK2 - Timer/Counter Interrupt Mask register 743.equ TOIE2 = 0 ; Timer/Counter2 Overflow Interrupt Enable 744.equ TOIE2A = TOIE2 ; For compatibility 745.equ OCIE2A = 1 ; Timer/Counter2 Output Compare Match A Interrupt Enable 746.equ OCIE2B = 2 ; Timer/Counter2 Output Compare Match B Interrupt Enable 747 748; TIFR2 - Timer/Counter Interrupt Flag Register 749.equ TOV2 = 0 ; Timer/Counter2 Overflow Flag 750.equ OCF2A = 1 ; Output Compare Flag 2A 751.equ OCF2B = 2 ; Output Compare Flag 2B 752 753; TCCR2A - Timer/Counter2 Control Register A 754.equ WGM20 = 0 ; Waveform Genration Mode 755.equ WGM21 = 1 ; Waveform Genration Mode 756.equ COM2B0 = 4 ; Compare Output Mode bit 0 757.equ COM2B1 = 5 ; Compare Output Mode bit 1 758.equ COM2A0 = 6 ; Compare Output Mode bit 1 759.equ COM2A1 = 7 ; Compare Output Mode bit 1 760 761; TCCR2B - Timer/Counter2 Control Register B 762.equ CS20 = 0 ; Clock Select bit 0 763.equ CS21 = 1 ; Clock Select bit 1 764.equ CS22 = 2 ; Clock Select bit 2 765.equ WGM22 = 3 ; Waveform Generation Mode 766.equ FOC2B = 6 ; Force Output Compare B 767.equ FOC2A = 7 ; Force Output Compare A 768 769; TCNT2 - Timer/Counter2 770.equ TCNT2_0 = 0 ; Timer/Counter 2 bit 0 771.equ TCNT2_1 = 1 ; Timer/Counter 2 bit 1 772.equ TCNT2_2 = 2 ; Timer/Counter 2 bit 2 773.equ TCNT2_3 = 3 ; Timer/Counter 2 bit 3 774.equ TCNT2_4 = 4 ; Timer/Counter 2 bit 4 775.equ TCNT2_5 = 5 ; Timer/Counter 2 bit 5 776.equ TCNT2_6 = 6 ; Timer/Counter 2 bit 6 777.equ TCNT2_7 = 7 ; Timer/Counter 2 bit 7 778 779; OCR2A - Timer/Counter2 Output Compare Register A 780.equ OCR2_0 = 0 ; Timer/Counter2 Output Compare Register Bit 0 781.equ OCR2_1 = 1 ; Timer/Counter2 Output Compare Register Bit 1 782.equ OCR2_2 = 2 ; Timer/Counter2 Output Compare Register Bit 2 783.equ OCR2_3 = 3 ; Timer/Counter2 Output Compare Register Bit 3 784.equ OCR2_4 = 4 ; Timer/Counter2 Output Compare Register Bit 4 785.equ OCR2_5 = 5 ; Timer/Counter2 Output Compare Register Bit 5 786.equ OCR2_6 = 6 ; Timer/Counter2 Output Compare Register Bit 6 787.equ OCR2_7 = 7 ; Timer/Counter2 Output Compare Register Bit 7 788 789; OCR2B - Timer/Counter2 Output Compare Register B 790;.equ OCR2_0 = 0 ; Timer/Counter2 Output Compare Register Bit 0 791;.equ OCR2_1 = 1 ; Timer/Counter2 Output Compare Register Bit 1 792;.equ OCR2_2 = 2 ; Timer/Counter2 Output Compare Register Bit 2 793;.equ OCR2_3 = 3 ; Timer/Counter2 Output Compare Register Bit 3 794;.equ OCR2_4 = 4 ; Timer/Counter2 Output Compare Register Bit 4 795;.equ OCR2_5 = 5 ; Timer/Counter2 Output Compare Register Bit 5 796;.equ OCR2_6 = 6 ; Timer/Counter2 Output Compare Register Bit 6 797;.equ OCR2_7 = 7 ; Timer/Counter2 Output Compare Register Bit 7 798 799; ASSR - Asynchronous Status Register 800.equ TCR2BUB = 0 ; Timer/Counter Control Register2 Update Busy 801.equ TCR2AUB = 1 ; Timer/Counter Control Register2 Update Busy 802.equ OCR2BUB = 2 ; Output Compare Register 2 Update Busy 803.equ OCR2AUB = 3 ; Output Compare Register2 Update Busy 804.equ TCN2UB = 4 ; Timer/Counter2 Update Busy 805.equ AS2 = 5 ; Asynchronous Timer/Counter2 806.equ EXCLK = 6 ; Enable External Clock Input 807 808; GTCCR - General Timer Counter Control register 809.equ PSRASY = 1 ; Prescaler Reset Timer/Counter2 810.equ PSR2 = PSRASY ; For compatibility 811;.equ TSM = 7 ; Timer/Counter Synchronization Mode 812 813 814; ***** WATCHDOG ********************* 815; WDTCSR - Watchdog Timer Control Register 816.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0 817.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1 818.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2 819.equ WDE = 3 ; Watch Dog Enable 820.equ WDCE = 4 ; Watchdog Change Enable 821.equ WDP3 = 5 ; Watchdog Timer Prescaler Bit 3 822.equ WDIE = 6 ; Watchdog Timeout Interrupt Enable 823.equ WDIF = 7 ; Watchdog Timeout Interrupt Flag 824 825 826; ***** USART1 *********************** 827; UDR1 - USART I/O Data Register 828.equ UDR1_0 = 0 ; USART I/O Data Register bit 0 829.equ UDR1_1 = 1 ; USART I/O Data Register bit 1 830.equ UDR1_2 = 2 ; USART I/O Data Register bit 2 831.equ UDR1_3 = 3 ; USART I/O Data Register bit 3 832.equ UDR1_4 = 4 ; USART I/O Data Register bit 4 833.equ UDR1_5 = 5 ; USART I/O Data Register bit 5 834.equ UDR1_6 = 6 ; USART I/O Data Register bit 6 835.equ UDR1_7 = 7 ; USART I/O Data Register bit 7 836 837; UCSR1A - USART Control and Status Register A 838.equ MPCM1 = 0 ; Multi-processor Communication Mode 839.equ U2X1 = 1 ; Double the USART transmission speed 840.equ UPE1 = 2 ; Parity Error 841.equ DOR1 = 3 ; Data overRun 842.equ FE1 = 4 ; Framing Error 843.equ UDRE1 = 5 ; USART Data Register Empty 844.equ TXC1 = 6 ; USART Transmitt Complete 845.equ RXC1 = 7 ; USART Receive Complete 846 847; UCSR1B - USART Control and Status Register B 848.equ TXB81 = 0 ; Transmit Data Bit 8 849.equ RXB81 = 1 ; Receive Data Bit 8 850.equ UCSZ12 = 2 ; Character Size 851.equ TXEN1 = 3 ; Transmitter Enable 852.equ RXEN1 = 4 ; Receiver Enable 853.equ UDRIE1 = 5 ; USART Data register Empty Interrupt Enable 854.equ TXCIE1 = 6 ; TX Complete Interrupt Enable 855.equ RXCIE1 = 7 ; RX Complete Interrupt Enable 856 857; UCSR1C - USART Control and Status Register C 858.equ UCPOL1 = 0 ; Clock Polarity 859.equ UCSZ10_UCPHA1 = 1 ; Character Size 860.equ UCSZ11_UDORD1 = 2 ; Character Size 861.equ USBS1 = 3 ; Stop Bit Select 862.equ UPM10 = 4 ; Parity Mode Bit 0 863.equ UPM11 = 5 ; Parity Mode Bit 1 864.equ UMSEL10 = 6 ; USART Mode Select 865.equ UMSEL11 = 7 ; USART Mode Select 866 867 868; ***** EEPROM *********************** 869; EEARH - EEPROM Address Register Low Byte 870.equ EEAR8 = 0 ; EEPROM Read/Write Access Bit 8 871.equ EEAR9 = 1 ; EEPROM Read/Write Access Bit 9 872.equ EEAR10 = 2 ; EEPROM Read/Write Access Bit 10 873.equ EEAR11 = 3 ; EEPROM Read/Write Access Bit 11 874 875; EEARL - EEPROM Address Register Low Byte 876.equ EEAR0 = 0 ; EEPROM Read/Write Access Bit 0 877.equ EEAR1 = 1 ; EEPROM Read/Write Access Bit 1 878.equ EEAR2 = 2 ; EEPROM Read/Write Access Bit 2 879.equ EEAR3 = 3 ; EEPROM Read/Write Access Bit 3 880.equ EEAR4 = 4 ; EEPROM Read/Write Access Bit 4 881.equ EEAR5 = 5 ; EEPROM Read/Write Access Bit 5 882.equ EEAR6 = 6 ; EEPROM Read/Write Access Bit 6 883.equ EEAR7 = 7 ; EEPROM Read/Write Access Bit 7 884 885; EEDR - EEPROM Data Register 886.equ EEDR0 = 0 ; EEPROM Data Register bit 0 887.equ EEDR1 = 1 ; EEPROM Data Register bit 1 888.equ EEDR2 = 2 ; EEPROM Data Register bit 2 889.equ EEDR3 = 3 ; EEPROM Data Register bit 3 890.equ EEDR4 = 4 ; EEPROM Data Register bit 4 891.equ EEDR5 = 5 ; EEPROM Data Register bit 5 892.equ EEDR6 = 6 ; EEPROM Data Register bit 6 893.equ EEDR7 = 7 ; EEPROM Data Register bit 7 894 895; EECR - EEPROM Control Register 896.equ EERE = 0 ; EEPROM Read Enable 897.equ EEPE = 1 ; EEPROM Write Enable 898.equ EEMPE = 2 ; EEPROM Master Write Enable 899.equ EERIE = 3 ; EEPROM Ready Interrupt Enable 900.equ EEPM0 = 4 ; EEPROM Programming Mode Bit 0 901.equ EEPM1 = 5 ; EEPROM Programming Mode Bit 1 902 903 904; ***** TIMER_COUNTER_5 ************** 905; TIMSK5 - Timer/Counter5 Interrupt Mask Register 906.equ TOIE5 = 0 ; Timer/Counter5 Overflow Interrupt Enable 907.equ OCIE5A = 1 ; Timer/Counter5 Output Compare A Match Interrupt Enable 908.equ OCIE5B = 2 ; Timer/Counter5 Output Compare B Match Interrupt Enable 909.equ OCIE5C = 3 ; Timer/Counter5 Output Compare C Match Interrupt Enable 910.equ ICIE5 = 5 ; Timer/Counter5 Input Capture Interrupt Enable 911 912; TIFR5 - Timer/Counter5 Interrupt Flag register 913.equ TOV5 = 0 ; Timer/Counter5 Overflow Flag 914.equ OCF5A = 1 ; Output Compare Flag 5A 915.equ OCF5B = 2 ; Output Compare Flag 5B 916.equ OCF5C = 3 ; Output Compare Flag 5C 917.equ ICF5 = 5 ; Input Capture Flag 5 918 919; TCCR5A - Timer/Counter5 Control Register A 920.equ WGM50 = 0 ; Waveform Generation Mode 921.equ WGM51 = 1 ; Waveform Generation Mode 922.equ COM5C0 = 2 ; Compare Output Mode 5C, bit 0 923.equ COM5C1 = 3 ; Compare Output Mode 5C, bit 1 924.equ COM5B0 = 4 ; Compare Output Mode 5B, bit 0 925.equ COM5B1 = 5 ; Compare Output Mode 5B, bit 1 926.equ COM5A0 = 6 ; Compare Output Mode 5A, bit 0 927.equ COM5A1 = 7 ; Compare Output Mode 1A, bit 1 928 929; TCCR5B - Timer/Counter5 Control Register B 930.equ CS50 = 0 ; Prescaler source of Timer/Counter 5 931.equ CS51 = 1 ; Prescaler source of Timer/Counter 5 932.equ CS52 = 2 ; Prescaler source of Timer/Counter 5 933.equ WGM52 = 3 ; Waveform Generation Mode 934.equ WGM53 = 4 ; Waveform Generation Mode 935.equ ICES5 = 6 ; Input Capture 5 Edge Select 936.equ ICNC5 = 7 ; Input Capture 5 Noise Canceler 937 938; TCCR5C - Timer/Counter 5 Control Register C 939.equ FOC5C = 5 ; Force Output Compare 5C 940.equ FOC5B = 6 ; Force Output Compare 5B 941.equ FOC5A = 7 ; Force Output Compare 5A 942 943; ICR5L - Timer/Counter5 Input Capture Register Low Byte 944.equ ICR5L0 = 0 ; Timer/Counter5 Input Capture Register Low Byte bit 0 945.equ ICR5L1 = 1 ; Timer/Counter5 Input Capture Register Low Byte bit 1 946.equ ICR5L2 = 2 ; Timer/Counter5 Input Capture Register Low Byte bit 2 947.equ ICR5L3 = 3 ; Timer/Counter5 Input Capture Register Low Byte bit 3 948.equ ICR5L4 = 4 ; Timer/Counter5 Input Capture Register Low Byte bit 4 949.equ ICR5L5 = 5 ; Timer/Counter5 Input Capture Register Low Byte bit 5 950.equ ICR5L6 = 6 ; Timer/Counter5 Input Capture Register Low Byte bit 6 951.equ ICR5L7 = 7 ; Timer/Counter5 Input Capture Register Low Byte bit 7 952 953 954; ***** TIMER_COUNTER_4 ************** 955; TIMSK4 - Timer/Counter4 Interrupt Mask Register 956.equ TOIE4 = 0 ; Timer/Counter4 Overflow Interrupt Enable 957.equ OCIE4A = 1 ; Timer/Counter4 Output Compare A Match Interrupt Enable 958.equ OCIE4B = 2 ; Timer/Counter4 Output Compare B Match Interrupt Enable 959.equ OCIE4C = 3 ; Timer/Counter4 Output Compare C Match Interrupt Enable 960.equ ICIE4 = 5 ; Timer/Counter4 Input Capture Interrupt Enable 961 962; TIFR4 - Timer/Counter4 Interrupt Flag register 963.equ TOV4 = 0 ; Timer/Counter4 Overflow Flag 964.equ OCF4A = 1 ; Output Compare Flag 4A 965.equ OCF4B = 2 ; Output Compare Flag 4B 966.equ OCF4C = 3 ; Output Compare Flag 4C 967.equ ICF4 = 5 ; Input Capture Flag 4 968 969; TCCR4A - Timer/Counter4 Control Register A 970.equ WGM40 = 0 ; Waveform Generation Mode 971.equ WGM41 = 1 ; Waveform Generation Mode 972.equ COM4C0 = 2 ; Compare Output Mode 4C, bit 0 973.equ COM4C1 = 3 ; Compare Output Mode 4C, bit 1 974.equ COM4B0 = 4 ; Compare Output Mode 4B, bit 0 975.equ COM4B1 = 5 ; Compare Output Mode 4B, bit 1 976.equ COM4A0 = 6 ; Compare Output Mode 4A, bit 0 977.equ COM4A1 = 7 ; Compare Output Mode 1A, bit 1 978 979; TCCR4B - Timer/Counter4 Control Register B 980.equ CS40 = 0 ; Prescaler source of Timer/Counter 4 981.equ CS41 = 1 ; Prescaler source of Timer/Counter 4 982.equ CS42 = 2 ; Prescaler source of Timer/Counter 4 983.equ WGM42 = 3 ; Waveform Generation Mode 984.equ WGM43 = 4 ; Waveform Generation Mode 985.equ ICES4 = 6 ; Input Capture 4 Edge Select 986.equ ICNC4 = 7 ; Input Capture 4 Noise Canceler 987 988; TCCR4C - Timer/Counter 4 Control Register C 989.equ FOC4C = 5 ; Force Output Compare 4C 990.equ FOC4B = 6 ; Force Output Compare 4B 991.equ FOC4A = 7 ; Force Output Compare 4A 992 993 994; ***** TIMER_COUNTER_3 ************** 995; TIMSK3 - Timer/Counter3 Interrupt Mask Register 996.equ TOIE3 = 0 ; Timer/Counter3 Overflow Interrupt Enable 997.equ OCIE3A = 1 ; Timer/Counter3 Output Compare A Match Interrupt Enable 998.equ OCIE3B = 2 ; Timer/Counter3 Output Compare B Match Interrupt Enable 999.equ OCIE3C = 3 ; Timer/Counter3 Output Compare C Match Interrupt Enable 1000.equ ICIE3 = 5 ; Timer/Counter3 Input Capture Interrupt Enable 1001 1002; TIFR3 - Timer/Counter3 Interrupt Flag register 1003.equ TOV3 = 0 ; Timer/Counter3 Overflow Flag 1004.equ OCF3A = 1 ; Output Compare Flag 3A 1005.equ OCF3B = 2 ; Output Compare Flag 3B 1006.equ OCF3C = 3 ; Output Compare Flag 3C 1007.equ ICF3 = 5 ; Input Capture Flag 3 1008 1009; TCCR3A - Timer/Counter3 Control Register A 1010.equ WGM30 = 0 ; Waveform Generation Mode 1011.equ WGM31 = 1 ; Waveform Generation Mode 1012.equ COM3C0 = 2 ; Compare Output Mode 3C, bit 0 1013.equ COM3C1 = 3 ; Compare Output Mode 3C, bit 1 1014.equ COM3B0 = 4 ; Compare Output Mode 3B, bit 0 1015.equ COM3B1 = 5 ; Compare Output Mode 3B, bit 1 1016.equ COM3A0 = 6 ; Compare Output Mode 3A, bit 0 1017.equ COM3A1 = 7 ; Compare Output Mode 1A, bit 1 1018 1019; TCCR3B - Timer/Counter3 Control Register B 1020.equ CS30 = 0 ; Prescaler source of Timer/Counter 3 1021.equ CS31 = 1 ; Prescaler source of Timer/Counter 3 1022.equ CS32 = 2 ; Prescaler source of Timer/Counter 3 1023.equ WGM32 = 3 ; Waveform Generation Mode 1024.equ WGM33 = 4 ; Waveform Generation Mode 1025.equ ICES3 = 6 ; Input Capture 3 Edge Select 1026.equ ICNC3 = 7 ; Input Capture 3 Noise Canceler 1027 1028; TCCR3C - Timer/Counter 3 Control Register C 1029.equ FOC3C = 5 ; Force Output Compare 3C 1030.equ FOC3B = 6 ; Force Output Compare 3B 1031.equ FOC3A = 7 ; Force Output Compare 3A 1032 1033 1034; ***** TIMER_COUNTER_1 ************** 1035; TIMSK1 - Timer/Counter1 Interrupt Mask Register 1036.equ TOIE1 = 0 ; Timer/Counter1 Overflow Interrupt Enable 1037.equ OCIE1A = 1 ; Timer/Counter1 Output Compare A Match Interrupt Enable 1038.equ OCIE1B = 2 ; Timer/Counter1 Output Compare B Match Interrupt Enable 1039.equ OCIE1C = 3 ; Timer/Counter1 Output Compare C Match Interrupt Enable 1040.equ ICIE1 = 5 ; Timer/Counter1 Input Capture Interrupt Enable 1041 1042; TIFR1 - Timer/Counter1 Interrupt Flag register 1043.equ TOV1 = 0 ; Timer/Counter1 Overflow Flag 1044.equ OCF1A = 1 ; Output Compare Flag 1A 1045.equ OCF1B = 2 ; Output Compare Flag 1B 1046.equ OCF1C = 3 ; Output Compare Flag 1C 1047.equ ICF1 = 5 ; Input Capture Flag 1 1048 1049; TCCR1A - Timer/Counter1 Control Register A 1050.equ WGM10 = 0 ; Waveform Generation Mode 1051.equ WGM11 = 1 ; Waveform Generation Mode 1052.equ COM1C0 = 2 ; Compare Output Mode 1C, bit 0 1053.equ COM1C1 = 3 ; Compare Output Mode 1C, bit 1 1054.equ COM1B0 = 4 ; Compare Output Mode 1B, bit 0 1055.equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1 1056.equ COM1A0 = 6 ; Compare Output Mode 1A, bit 0 1057.equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1 1058 1059; TCCR1B - Timer/Counter1 Control Register B 1060.equ CS10 = 0 ; Prescaler source of Timer/Counter 1 1061.equ CS11 = 1 ; Prescaler source of Timer/Counter 1 1062.equ CS12 = 2 ; Prescaler source of Timer/Counter 1 1063.equ WGM12 = 3 ; Waveform Generation Mode 1064.equ WGM13 = 4 ; Waveform Generation Mode 1065.equ ICES1 = 6 ; Input Capture 1 Edge Select 1066.equ ICNC1 = 7 ; Input Capture 1 Noise Canceler 1067 1068; TCCR1C - Timer/Counter 1 Control Register C 1069.equ FOC1C = 5 ; Force Output Compare 1C 1070.equ FOC1B = 6 ; Force Output Compare 1B 1071.equ FOC1A = 7 ; Force Output Compare 1A 1072 1073 1074; ***** JTAG ************************* 1075; OCDR - On-Chip Debug Related Register in I/O Memory 1076.equ OCDR0 = 0 ; On-Chip Debug Register Bit 0 1077.equ OCDR1 = 1 ; On-Chip Debug Register Bit 1 1078.equ OCDR2 = 2 ; On-Chip Debug Register Bit 2 1079.equ OCDR3 = 3 ; On-Chip Debug Register Bit 3 1080.equ OCDR4 = 4 ; On-Chip Debug Register Bit 4 1081.equ OCDR5 = 5 ; On-Chip Debug Register Bit 5 1082.equ OCDR6 = 6 ; On-Chip Debug Register Bit 6 1083.equ OCDR7 = 7 ; On-Chip Debug Register Bit 7 1084.equ IDRD = OCDR7 ; For compatibility 1085 1086; MCUCR - MCU Control Register 1087.equ JTD = 7 ; JTAG Interface Disable 1088 1089; MCUSR - MCU Status Register 1090.equ JTRF = 4 ; JTAG Reset Flag 1091 1092 1093; ***** EXTERNAL_INTERRUPT *********** 1094; EICRA - External Interrupt Control Register A 1095.equ ISC00 = 0 ; External Interrupt Sense Control Bit 1096.equ ISC01 = 1 ; External Interrupt Sense Control Bit 1097.equ ISC10 = 2 ; External Interrupt Sense Control Bit 1098.equ ISC11 = 3 ; External Interrupt Sense Control Bit 1099.equ ISC20 = 4 ; External Interrupt Sense Control Bit 1100.equ ISC21 = 5 ; External Interrupt Sense Control Bit 1101.equ ISC30 = 6 ; External Interrupt Sense Control Bit 1102.equ ISC31 = 7 ; External Interrupt Sense Control Bit 1103 1104; EICRB - External Interrupt Control Register B 1105.equ ISC40 = 0 ; External Interrupt 7-4 Sense Control Bit 1106.equ ISC41 = 1 ; External Interrupt 7-4 Sense Control Bit 1107.equ ISC50 = 2 ; External Interrupt 7-4 Sense Control Bit 1108.equ ISC51 = 3 ; External Interrupt 7-4 Sense Control Bit 1109.equ ISC60 = 4 ; External Interrupt 7-4 Sense Control Bit 1110.equ ISC61 = 5 ; External Interrupt 7-4 Sense Control Bit 1111.equ ISC70 = 6 ; External Interrupt 7-4 Sense Control Bit 1112.equ ISC71 = 7 ; External Interrupt 7-4 Sense Control Bit 1113 1114; EIMSK - External Interrupt Mask Register 1115.equ INT0 = 0 ; External Interrupt Request 0 Enable 1116.equ INT1 = 1 ; External Interrupt Request 1 Enable 1117.equ INT2 = 2 ; External Interrupt Request 2 Enable 1118.equ INT3 = 3 ; External Interrupt Request 3 Enable 1119.equ INT4 = 4 ; External Interrupt Request 4 Enable 1120.equ INT5 = 5 ; External Interrupt Request 5 Enable 1121.equ INT6 = 6 ; External Interrupt Request 6 Enable 1122.equ INT7 = 7 ; External Interrupt Request 7 Enable 1123 1124; EIFR - External Interrupt Flag Register 1125.equ INTF0 = 0 ; External Interrupt Flag 0 1126.equ INTF1 = 1 ; External Interrupt Flag 1 1127.equ INTF2 = 2 ; External Interrupt Flag 2 1128.equ INTF3 = 3 ; External Interrupt Flag 3 1129.equ INTF4 = 4 ; External Interrupt Flag 4 1130.equ INTF5 = 5 ; External Interrupt Flag 5 1131.equ INTF6 = 6 ; External Interrupt Flag 6 1132.equ INTF7 = 7 ; External Interrupt Flag 7 1133 1134; PCICR - Pin Change Interrupt Control Register 1135.equ PCIE0 = 0 ; Pin Change Interrupt Enable 0 1136.equ PCIE1 = 1 ; Pin Change Interrupt Enable 1 1137.equ PCIE2 = 2 ; Pin Change Interrupt Enable 2 1138 1139; PCIFR - Pin Change Interrupt Flag Register 1140.equ PCIF0 = 0 ; Pin Change Interrupt Flag 0 1141.equ PCIF1 = 1 ; Pin Change Interrupt Flag 1 1142.equ PCIF2 = 2 ; Pin Change Interrupt Flag 2 1143 1144; PCMSK2 - Pin Change Mask Register 2 1145.equ PCINT16 = 0 ; Pin Change Enable Mask 16 1146.equ PCINT17 = 1 ; Pin Change Enable Mask 17 1147.equ PCINT18 = 2 ; Pin Change Enable Mask 18 1148.equ PCINT19 = 3 ; Pin Change Enable Mask 19 1149.equ PCINT20 = 4 ; Pin Change Enable Mask 20 1150.equ PCINT21 = 5 ; Pin Change Enable Mask 21 1151.equ PCINT22 = 6 ; Pin Change Enable Mask 22 1152.equ PCINT23 = 7 ; Pin Change Enable Mask 23 1153 1154; PCMSK1 - Pin Change Mask Register 1 1155.equ PCINT8 = 0 ; Pin Change Enable Mask 8 1156.equ PCINT9 = 1 ; Pin Change Enable Mask 9 1157.equ PCINT10 = 2 ; Pin Change Enable Mask 10 1158.equ PCINT11 = 3 ; Pin Change Enable Mask 11 1159.equ PCINT12 = 4 ; Pin Change Enable Mask 12 1160.equ PCINT13 = 5 ; Pin Change Enable Mask 13 1161.equ PCINT14 = 6 ; Pin Change Enable Mask 14 1162.equ PCINT15 = 7 ; Pin Change Enable Mask 15 1163 1164; PCMSK0 - Pin Change Mask Register 0 1165.equ PCINT0 = 0 ; Pin Change Enable Mask 0 1166.equ PCINT1 = 1 ; Pin Change Enable Mask 1 1167.equ PCINT2 = 2 ; Pin Change Enable Mask 2 1168.equ PCINT3 = 3 ; Pin Change Enable Mask 3 1169.equ PCINT4 = 4 ; Pin Change Enable Mask 4 1170.equ PCINT5 = 5 ; Pin Change Enable Mask 5 1171.equ PCINT6 = 6 ; Pin Change Enable Mask 6 1172.equ PCINT7 = 7 ; Pin Change Enable Mask 7 1173 1174 1175; ***** CPU ************************** 1176; SREG - Status Register 1177.equ SREG_C = 0 ; Carry Flag 1178.equ SREG_Z = 1 ; Zero Flag 1179.equ SREG_N = 2 ; Negative Flag 1180.equ SREG_V = 3 ; Two's Complement Overflow Flag 1181.equ SREG_S = 4 1182.equ SREG_H = 5 ; Half Carry Flag 1183.equ SREG_T = 6 ; Bit Copy Storage 1184.equ SREG_I = 7 ; Global Interrupt Enable 1185 1186; MCUCR - MCU Control Register 1187.equ IVCE = 0 ; Interrupt Vector Change Enable 1188.equ IVSEL = 1 ; Interrupt Vector Select 1189.equ PUD = 4 ; Pull-up disable 1190;.equ JTD = 7 ; JTAG Interface Disable 1191 1192; MCUSR - MCU Status Register 1193.equ PORF = 0 ; Power-on reset flag 1194.equ EXTRF = 1 ; External Reset Flag 1195.equ BORF = 2 ; Brown-out Reset Flag 1196.equ WDRF = 3 ; Watchdog Reset Flag 1197;.equ JTRF = 4 ; JTAG Reset Flag 1198 1199; XMCRA - External Memory Control Register A 1200.equ SRW00 = 0 ; Wait state select bit lower page 1201.equ SRW01 = 1 ; Wait state select bit lower page 1202.equ SRW10 = 2 ; Wait state select bit upper page 1203.equ SRW11 = 3 ; Wait state select bit upper page 1204.equ SRL0 = 4 ; Wait state page limit 1205.equ SRL1 = 5 ; Wait state page limit 1206.equ SRL2 = 6 ; Wait state page limit 1207.equ SRE = 7 ; External SRAM Enable 1208 1209; XMCRB - External Memory Control Register B 1210.equ XMM0 = 0 ; External Memory High Mask 1211.equ XMM1 = 1 ; External Memory High Mask 1212.equ XMM2 = 2 ; External Memory High Mask 1213.equ XMBK = 7 ; External Memory Bus Keeper Enable 1214 1215; OSCCAL - Oscillator Calibration Value 1216.equ CAL0 = 0 ; Oscillator Calibration Value Bit0 1217.equ CAL1 = 1 ; Oscillator Calibration Value Bit1 1218.equ CAL2 = 2 ; Oscillator Calibration Value Bit2 1219.equ CAL3 = 3 ; Oscillator Calibration Value Bit3 1220.equ CAL4 = 4 ; Oscillator Calibration Value Bit4 1221.equ CAL5 = 5 ; Oscillator Calibration Value Bit5 1222.equ CAL6 = 6 ; Oscillator Calibration Value Bit6 1223.equ CAL7 = 7 ; Oscillator Calibration Value Bit7 1224 1225; CLKPR - 1226.equ CLKPS0 = 0 ; 1227.equ CLKPS1 = 1 ; 1228.equ CLKPS2 = 2 ; 1229.equ CLKPS3 = 3 ; 1230.equ CPKPCE = 7 ; 1231 1232; SMCR - Sleep Mode Control Register 1233.equ SE = 0 ; Sleep Enable 1234.equ SM0 = 1 ; Sleep Mode Select bit 0 1235.equ SM1 = 2 ; Sleep Mode Select bit 1 1236.equ SM2 = 3 ; Sleep Mode Select bit 2 1237 1238; RAMPZ - RAM Page Z Select Register 1239.equ RAMPZ0 = 0 ; RAM Page Z Select Register Bit 0 1240.equ RAMPZ1 = 1 ; RAM Page Z Select Register Bit 1 1241 1242; EIND - Extended Indirect Register 1243.equ EIND0 = 0 ; Bit 0 1244 1245; GPIOR2 - General Purpose IO Register 2 1246.equ GPIOR20 = 0 ; General Purpose IO Register 2 bit 0 1247.equ GPIOR21 = 1 ; General Purpose IO Register 2 bit 1 1248.equ GPIOR22 = 2 ; General Purpose IO Register 2 bit 2 1249.equ GPIOR23 = 3 ; General Purpose IO Register 2 bit 3 1250.equ GPIOR24 = 4 ; General Purpose IO Register 2 bit 4 1251.equ GPIOR25 = 5 ; General Purpose IO Register 2 bit 5 1252.equ GPIOR26 = 6 ; General Purpose IO Register 2 bit 6 1253.equ GPIOR27 = 7 ; General Purpose IO Register 2 bit 7 1254 1255; GPIOR1 - General Purpose IO Register 1 1256.equ GPIOR10 = 0 ; General Purpose IO Register 1 bit 0 1257.equ GPIOR11 = 1 ; General Purpose IO Register 1 bit 1 1258.equ GPIOR12 = 2 ; General Purpose IO Register 1 bit 2 1259.equ GPIOR13 = 3 ; General Purpose IO Register 1 bit 3 1260.equ GPIOR14 = 4 ; General Purpose IO Register 1 bit 4 1261.equ GPIOR15 = 5 ; General Purpose IO Register 1 bit 5 1262.equ GPIOR16 = 6 ; General Purpose IO Register 1 bit 6 1263.equ GPIOR17 = 7 ; General Purpose IO Register 1 bit 7 1264 1265; GPIOR0 - General Purpose IO Register 0 1266.equ GPIOR00 = 0 ; General Purpose IO Register 0 bit 0 1267.equ GPIOR01 = 1 ; General Purpose IO Register 0 bit 1 1268.equ GPIOR02 = 2 ; General Purpose IO Register 0 bit 2 1269.equ GPIOR03 = 3 ; General Purpose IO Register 0 bit 3 1270.equ GPIOR04 = 4 ; General Purpose IO Register 0 bit 4 1271.equ GPIOR05 = 5 ; General Purpose IO Register 0 bit 5 1272.equ GPIOR06 = 6 ; General Purpose IO Register 0 bit 6 1273.equ GPIOR07 = 7 ; General Purpose IO Register 0 bit 7 1274 1275; PRR1 - Power Reduction Register1 1276.equ PRUSART1 = 0 ; Power Reduction USART1 1277.equ PRUSART2 = 1 ; Power Reduction USART2 1278.equ PRUSART3 = 2 ; Power Reduction USART3 1279.equ PRTIM3 = 3 ; Power Reduction Timer/Counter3 1280.equ PRTIM4 = 4 ; Power Reduction Timer/Counter4 1281.equ PRTIM5 = 5 ; Power Reduction Timer/Counter5 1282 1283; PRR0 - Power Reduction Register0 1284.equ PRADC = 0 ; Power Reduction ADC 1285.equ PRUSART0 = 1 ; Power Reduction USART 1286.equ PRSPI = 2 ; Power Reduction Serial Peripheral Interface 1287.equ PRTIM1 = 3 ; Power Reduction Timer/Counter1 1288.equ PRTIM0 = 5 ; Power Reduction Timer/Counter0 1289.equ PRTIM2 = 6 ; Power Reduction Timer/Counter2 1290.equ PRTWI = 7 ; Power Reduction TWI 1291 1292 1293; ***** AD_CONVERTER ***************** 1294; ADMUX - The ADC multiplexer Selection Register 1295.equ MUX0 = 0 ; Analog Channel and Gain Selection Bits 1296.equ MUX1 = 1 ; Analog Channel and Gain Selection Bits 1297.equ MUX2 = 2 ; Analog Channel and Gain Selection Bits 1298.equ MUX3 = 3 ; Analog Channel and Gain Selection Bits 1299.equ MUX4 = 4 ; Analog Channel and Gain Selection Bits 1300.equ ADLAR = 5 ; Left Adjust Result 1301.equ REFS0 = 6 ; Reference Selection Bit 0 1302.equ REFS1 = 7 ; Reference Selection Bit 1 1303 1304; ADCSRA - The ADC Control and Status register A 1305.equ ADPS0 = 0 ; ADC Prescaler Select Bits 1306.equ ADPS1 = 1 ; ADC Prescaler Select Bits 1307.equ ADPS2 = 2 ; ADC Prescaler Select Bits 1308.equ ADIE = 3 ; ADC Interrupt Enable 1309.equ ADIF = 4 ; ADC Interrupt Flag 1310.equ ADATE = 5 ; ADC Auto Trigger Enable 1311.equ ADSC = 6 ; ADC Start Conversion 1312.equ ADEN = 7 ; ADC Enable 1313 1314; ADCSRB - The ADC Control and Status register B 1315.equ ADTS0 = 0 ; ADC Auto Trigger Source bit 0 1316.equ ADTS1 = 1 ; ADC Auto Trigger Source bit 1 1317.equ ADTS2 = 2 ; ADC Auto Trigger Source bit 2 1318.equ MUX5 = 3 ; Analog Channel and Gain Selection Bits 1319;.equ ACME = 6 ; 1320 1321; ADCH - ADC Data Register High Byte 1322.equ ADCH0 = 0 ; ADC Data Register High Byte Bit 0 1323.equ ADCH1 = 1 ; ADC Data Register High Byte Bit 1 1324.equ ADCH2 = 2 ; ADC Data Register High Byte Bit 2 1325.equ ADCH3 = 3 ; ADC Data Register High Byte Bit 3 1326.equ ADCH4 = 4 ; ADC Data Register High Byte Bit 4 1327.equ ADCH5 = 5 ; ADC Data Register High Byte Bit 5 1328.equ ADCH6 = 6 ; ADC Data Register High Byte Bit 6 1329.equ ADCH7 = 7 ; ADC Data Register High Byte Bit 7 1330 1331; ADCL - ADC Data Register Low Byte 1332.equ ADCL0 = 0 ; ADC Data Register Low Byte Bit 0 1333.equ ADCL1 = 1 ; ADC Data Register Low Byte Bit 1 1334.equ ADCL2 = 2 ; ADC Data Register Low Byte Bit 2 1335.equ ADCL3 = 3 ; ADC Data Register Low Byte Bit 3 1336.equ ADCL4 = 4 ; ADC Data Register Low Byte Bit 4 1337.equ ADCL5 = 5 ; ADC Data Register Low Byte Bit 5 1338.equ ADCL6 = 6 ; ADC Data Register Low Byte Bit 6 1339.equ ADCL7 = 7 ; ADC Data Register Low Byte Bit 7 1340 1341; DIDR0 - Digital Input Disable Register 1342.equ ADC0D = 0 ; 1343.equ ADC1D = 1 ; 1344.equ ADC2D = 2 ; 1345.equ ADC3D = 3 ; 1346.equ ADC4D = 4 ; 1347.equ ADC5D = 5 ; 1348.equ ADC6D = 6 ; 1349.equ ADC7D = 7 ; 1350 1351; DIDR2 - Digital Input Disable Register 1352.equ ADC8D = 0 ; 1353.equ ADC9D = 1 ; 1354.equ ADC10D = 2 ; 1355.equ ADC11D = 3 ; 1356.equ ADC12D = 4 ; 1357.equ ADC13D = 5 ; 1358.equ ADC14D = 6 ; 1359.equ ADC15D = 7 ; 1360 1361 1362; ***** BOOT_LOAD ******************** 1363; SPMCSR - Store Program Memory Control Register 1364.equ SPMEN = 0 ; Store Program Memory Enable 1365.equ PGERS = 1 ; Page Erase 1366.equ PGWRT = 2 ; Page Write 1367.equ BLBSET = 3 ; Boot Lock Bit Set 1368.equ RWWSRE = 4 ; Read While Write section read enable 1369.equ SIGRD = 5 ; Signature Row Read 1370.equ RWWSB = 6 ; Read While Write Section Busy 1371.equ SPMIE = 7 ; SPM Interrupt Enable 1372 1373 1374 1375; ***** LOCKSBITS ******************************************************** 1376.equ LB1 = 0 ; Lock bit 1377.equ LB2 = 1 ; Lock bit 1378.equ BLB01 = 2 ; Boot Lock bit 1379.equ BLB02 = 3 ; Boot Lock bit 1380.equ BLB11 = 4 ; Boot lock bit 1381.equ BLB12 = 5 ; Boot lock bit 1382 1383 1384; ***** FUSES ************************************************************ 1385; LOW fuse bits 1386.equ CKSEL0 = 0 ; Select Clock Source 1387.equ CKSEL1 = 1 ; Select Clock Source 1388.equ CKSEL2 = 2 ; Select Clock Source 1389.equ CKSEL3 = 3 ; Select Clock Source 1390.equ SUT0 = 4 ; Select start-up time 1391.equ SUT1 = 5 ; Select start-up time 1392.equ CKOUT = 6 ; Oscillator options 1393.equ CLKDIV8 = 7 ; Divide clock by 8 1394 1395; HIGH fuse bits 1396.equ BOOTRST = 0 ; Select Reset Vector 1397.equ BOOTSZ0 = 1 ; Select Boot Size 1398.equ BOOTSZ1 = 2 ; Select Boot Size 1399.equ EESAVE = 3 ; EEPROM memory is preserved through chip erase 1400.equ WDTON = 4 ; Watchdog timer always on 1401.equ SPIEN = 5 ; Enable Serial programming and Data Downloading 1402.equ JTAGEN = 6 ; Enable JTAG 1403.equ OCDEN = 7 ; Enable OCD 1404 1405; EXTENDED fuse bits 1406.equ BODLEVEL0 = 0 ; Brown-out Detector trigger level 1407.equ BODLEVEL1 = 1 ; Brown-out Detector trigger level 1408.equ BODLEVEL2 = 2 ; Brown-out Detector trigger level 1409 1410 1411 1412; ***** CPU REGISTER DEFINITIONS ***************************************** 1413.def XH = r27 1414.def XL = r26 1415.def YH = r29 1416.def YL = r28 1417.def ZH = r31 1418.def ZL = r30 1419 1420 1421 1422; ***** DATA MEMORY DECLARATIONS ***************************************** 1423.equ FLASHEND = 0x1ffff ; Note: Word address 1424.equ IOEND = 0x01ff 1425.equ SRAM_START = 0x0200 1426.equ SRAM_SIZE = 8192 1427.equ RAMEND = 0x21ff 1428.equ XRAMEND = 0xffff 1429.equ E2END = 0x0fff 1430.equ EEPROMEND = 0x0fff 1431.equ EEADRBITS = 12 1432#pragma AVRPART MEMORY PROG_FLASH 262144 1433#pragma AVRPART MEMORY EEPROM 4096 1434#pragma AVRPART MEMORY INT_SRAM SIZE 8192 1435#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x200 1436 1437 1438 1439; ***** BOOTLOADER DECLARATIONS ****************************************** 1440.equ NRWW_START_ADDR = 0x1f000 1441.equ NRWW_STOP_ADDR = 0x1ffff 1442.equ RWW_START_ADDR = 0x0 1443.equ RWW_STOP_ADDR = 0x1efff 1444.equ PAGESIZE = 128 1445.equ FIRSTBOOTSTART = 0x1fe00 1446.equ SECONDBOOTSTART = 0x1fc00 1447.equ THIRDBOOTSTART = 0x1f800 1448.equ FOURTHBOOTSTART = 0x1f000 1449.equ SMALLBOOTSTART = FIRSTBOOTSTART 1450.equ LARGEBOOTSTART = FOURTHBOOTSTART 1451 1452 1453 1454; ***** INTERRUPT VECTORS ************************************************ 1455.equ INT0addr = 0x0002 ; External Interrupt Request 0 1456.equ INT1addr = 0x0004 ; External Interrupt Request 1 1457.equ INT2addr = 0x0006 ; External Interrupt Request 2 1458.equ INT3addr = 0x0008 ; External Interrupt Request 3 1459.equ INT4addr = 0x000a ; External Interrupt Request 4 1460.equ INT5addr = 0x000c ; External Interrupt Request 5 1461.equ INT6addr = 0x000e ; External Interrupt Request 6 1462.equ INT7addr = 0x0010 ; External Interrupt Request 7 1463.equ PCI0addr = 0x0012 ; Pin Change Interrupt Request 0 1464.equ PCI1addr = 0x0014 ; Pin Change Interrupt Request 1 1465.equ PCI2addr = 0x0016 ; Pin Change Interrupt Request 2 1466.equ WDTaddr = 0x0018 ; Watchdog Time-out Interrupt 1467.equ OC2Aaddr = 0x001a ; Timer/Counter2 Compare Match A 1468.equ OC2Baddr = 0x001c ; Timer/Counter2 Compare Match B 1469.equ OVF2addr = 0x001e ; Timer/Counter2 Overflow 1470.equ ICP1addr = 0x0020 ; Timer/Counter1 Capture Event 1471.equ OC1Aaddr = 0x0022 ; Timer/Counter1 Compare Match A 1472.equ OC1Baddr = 0x0024 ; Timer/Counter1 Compare Match B 1473.equ OC1Caddr = 0x0026 ; Timer/Counter1 Compare Match C 1474.equ OVF1addr = 0x0028 ; Timer/Counter1 Overflow 1475.equ OC0Aaddr = 0x002a ; Timer/Counter0 Compare Match A 1476.equ OC0Baddr = 0x002c ; Timer/Counter0 Compare Match B 1477.equ OVF0addr = 0x002e ; Timer/Counter0 Overflow 1478.equ SPIaddr = 0x0030 ; SPI Serial Transfer Complete 1479.equ URXC0addr = 0x0032 ; USART0, Rx Complete 1480.equ UDRE0addr = 0x0034 ; USART0 Data register Empty 1481.equ UTXC0addr = 0x0036 ; USART0, Tx Complete 1482.equ ACIaddr = 0x0038 ; Analog Comparator 1483.equ ADCCaddr = 0x003a ; ADC Conversion Complete 1484.equ ERDYaddr = 0x003c ; EEPROM Ready 1485.equ ICP3addr = 0x003e ; Timer/Counter3 Capture Event 1486.equ OC3Aaddr = 0x0040 ; Timer/Counter3 Compare Match A 1487.equ OC3Baddr = 0x0042 ; Timer/Counter3 Compare Match B 1488.equ OC3Caddr = 0x0044 ; Timer/Counter3 Compare Match C 1489.equ OVF3addr = 0x0046 ; Timer/Counter3 Overflow 1490.equ URXC1addr = 0x0048 ; USART1, Rx Complete 1491.equ UDRE1addr = 0x004a ; USART1 Data register Empty 1492.equ UTXC1addr = 0x004c ; USART1, Tx Complete 1493.equ TWIaddr = 0x004e ; 2-wire Serial Interface 1494.equ SPMRaddr = 0x0050 ; Store Program Memory Read 1495.equ ICP4addr = 0x0052 ; Timer/Counter4 Capture Event 1496.equ OC4Aaddr = 0x0054 ; Timer/Counter4 Compare Match A 1497.equ OC4Baddr = 0x0056 ; Timer/Counter4 Compare Match B 1498.equ OC4Caddr = 0x0058 ; Timer/Counter4 Compare Match C 1499.equ OVF4addr = 0x005a ; Timer/Counter4 Overflow 1500.equ ICP5addr = 0x005c ; Timer/Counter5 Capture Event 1501.equ OC5Aaddr = 0x005e ; Timer/Counter5 Compare Match A 1502.equ OC5Baddr = 0x0060 ; Timer/Counter5 Compare Match B 1503.equ OC5Caddr = 0x0062 ; Timer/Counter5 Compare Match C 1504.equ OVF5addr = 0x0064 ; Timer/Counter5 Overflow 1505.equ URXC2addr = 0x0066 ; USART2, Rx Complete 1506.equ UDRE2addr = 0x0068 ; USART2 Data register Empty 1507.equ UTXC2addr = 0x006a ; USART2, Tx Complete 1508.equ URXC3addr = 0x006c ; USART3, Rx Complete 1509.equ UDRE3addr = 0x006e ; USART3 Data register Empty 1510.equ UTXC3addr = 0x0070 ; USART3, Tx Complete 1511 1512.equ INT_VECTORS_SIZE = 114 ; size in words 1513 1514#endif /* _M2561DEF_INC_ */ 1515 1516; ***** END OF FILE ****************************************************** 1517