1;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ******************** 2;***** Created: 2011-02-09 12:03 ******* Source: ATmega328P.xml ********** 3;************************************************************************* 4;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y 5;* 6;* Number : AVR000 7;* File Name : "m328Pdef.inc" 8;* Title : Register/Bit Definitions for the ATmega328P 9;* Date : 2011-02-09 10;* Version : 2.35 11;* Support E-mail : avr@atmel.com 12;* Target MCU : ATmega328P 13;* 14;* DESCRIPTION 15;* When including this file in the assembly program file, all I/O register 16;* names and I/O register bit names appearing in the data book can be used. 17;* In addition, the six registers forming the three data pointers X, Y and 18;* Z have been assigned names XL - ZH. Highest RAM address for Internal 19;* SRAM is also defined 20;* 21;* The Register names are represented by their hexadecimal address. 22;* 23;* The Register Bit names are represented by their bit number (0-7). 24;* 25;* Please observe the difference in using the bit names with instructions 26;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" 27;* (skip if bit in register set/cleared). The following example illustrates 28;* this: 29;* 30;* in r16,PORTB ;read PORTB latch 31;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#) 32;* out PORTB,r16 ;output to PORTB 33;* 34;* in r16,TIFR ;read the Timer Interrupt Flag Register 35;* sbrc r16,TOV0 ;test the overflow flag (use bit#) 36;* rjmp TOV0_is_set ;jump if set 37;* ... ;otherwise do something else 38;************************************************************************* 39 40#ifndef _M328PDEF_INC_ 41#define _M328PDEF_INC_ 42 43 44#pragma partinc 0 45 46; ***** SPECIFY DEVICE *************************************************** 47.device ATmega328P 48#pragma AVRPART ADMIN PART_NAME ATmega328P 49.equ SIGNATURE_000 = 0x1e 50.equ SIGNATURE_001 = 0x95 51.equ SIGNATURE_002 = 0x0f 52 53#pragma AVRPART CORE CORE_VERSION V2E 54 55 56; ***** I/O REGISTER DEFINITIONS ***************************************** 57; NOTE: 58; Definitions marked "MEMORY MAPPED"are extended I/O ports 59; and cannot be used with IN/OUT instructions 60.equ UDR0 = 0xc6 ; MEMORY MAPPED 61.equ UBRR0L = 0xc4 ; MEMORY MAPPED 62.equ UBRR0H = 0xc5 ; MEMORY MAPPED 63.equ UCSR0C = 0xc2 ; MEMORY MAPPED 64.equ UCSR0B = 0xc1 ; MEMORY MAPPED 65.equ UCSR0A = 0xc0 ; MEMORY MAPPED 66.equ TWAMR = 0xbd ; MEMORY MAPPED 67.equ TWCR = 0xbc ; MEMORY MAPPED 68.equ TWDR = 0xbb ; MEMORY MAPPED 69.equ TWAR = 0xba ; MEMORY MAPPED 70.equ TWSR = 0xb9 ; MEMORY MAPPED 71.equ TWBR = 0xb8 ; MEMORY MAPPED 72.equ ASSR = 0xb6 ; MEMORY MAPPED 73.equ OCR2B = 0xb4 ; MEMORY MAPPED 74.equ OCR2A = 0xb3 ; MEMORY MAPPED 75.equ TCNT2 = 0xb2 ; MEMORY MAPPED 76.equ TCCR2B = 0xb1 ; MEMORY MAPPED 77.equ TCCR2A = 0xb0 ; MEMORY MAPPED 78.equ OCR1BL = 0x8a ; MEMORY MAPPED 79.equ OCR1BH = 0x8b ; MEMORY MAPPED 80.equ OCR1AL = 0x88 ; MEMORY MAPPED 81.equ OCR1AH = 0x89 ; MEMORY MAPPED 82.equ ICR1L = 0x86 ; MEMORY MAPPED 83.equ ICR1H = 0x87 ; MEMORY MAPPED 84.equ TCNT1L = 0x84 ; MEMORY MAPPED 85.equ TCNT1H = 0x85 ; MEMORY MAPPED 86.equ TCCR1C = 0x82 ; MEMORY MAPPED 87.equ TCCR1B = 0x81 ; MEMORY MAPPED 88.equ TCCR1A = 0x80 ; MEMORY MAPPED 89.equ DIDR1 = 0x7f ; MEMORY MAPPED 90.equ DIDR0 = 0x7e ; MEMORY MAPPED 91.equ ADMUX = 0x7c ; MEMORY MAPPED 92.equ ADCSRB = 0x7b ; MEMORY MAPPED 93.equ ADCSRA = 0x7a ; MEMORY MAPPED 94.equ ADCH = 0x79 ; MEMORY MAPPED 95.equ ADCL = 0x78 ; MEMORY MAPPED 96.equ TIMSK2 = 0x70 ; MEMORY MAPPED 97.equ TIMSK1 = 0x6f ; MEMORY MAPPED 98.equ TIMSK0 = 0x6e ; MEMORY MAPPED 99.equ PCMSK1 = 0x6c ; MEMORY MAPPED 100.equ PCMSK2 = 0x6d ; MEMORY MAPPED 101.equ PCMSK0 = 0x6b ; MEMORY MAPPED 102.equ EICRA = 0x69 ; MEMORY MAPPED 103.equ PCICR = 0x68 ; MEMORY MAPPED 104.equ OSCCAL = 0x66 ; MEMORY MAPPED 105.equ PRR = 0x64 ; MEMORY MAPPED 106.equ CLKPR = 0x61 ; MEMORY MAPPED 107.equ WDTCSR = 0x60 ; MEMORY MAPPED 108.equ SREG = 0x3f 109.equ SPL = 0x3d 110.equ SPH = 0x3e 111.equ SPMCSR = 0x37 112.equ MCUCR = 0x35 113.equ MCUSR = 0x34 114.equ SMCR = 0x33 115.equ ACSR = 0x30 116.equ SPDR = 0x2e 117.equ SPSR = 0x2d 118.equ SPCR = 0x2c 119.equ GPIOR2 = 0x2b 120.equ GPIOR1 = 0x2a 121.equ OCR0B = 0x28 122.equ OCR0A = 0x27 123.equ TCNT0 = 0x26 124.equ TCCR0B = 0x25 125.equ TCCR0A = 0x24 126.equ GTCCR = 0x23 127.equ EEARH = 0x22 128.equ EEARL = 0x21 129.equ EEDR = 0x20 130.equ EECR = 0x1f 131.equ GPIOR0 = 0x1e 132.equ EIMSK = 0x1d 133.equ EIFR = 0x1c 134.equ PCIFR = 0x1b 135.equ TIFR2 = 0x17 136.equ TIFR1 = 0x16 137.equ TIFR0 = 0x15 138.equ PORTD = 0x0b 139.equ DDRD = 0x0a 140.equ PIND = 0x09 141.equ PORTC = 0x08 142.equ DDRC = 0x07 143.equ PINC = 0x06 144.equ PORTB = 0x05 145.equ DDRB = 0x04 146.equ PINB = 0x03 147 148 149; ***** BIT DEFINITIONS ************************************************** 150 151; ***** USART0 *********************** 152; UDR0 - USART I/O Data Register 153.equ UDR0_0 = 0 ; USART I/O Data Register bit 0 154.equ UDR0_1 = 1 ; USART I/O Data Register bit 1 155.equ UDR0_2 = 2 ; USART I/O Data Register bit 2 156.equ UDR0_3 = 3 ; USART I/O Data Register bit 3 157.equ UDR0_4 = 4 ; USART I/O Data Register bit 4 158.equ UDR0_5 = 5 ; USART I/O Data Register bit 5 159.equ UDR0_6 = 6 ; USART I/O Data Register bit 6 160.equ UDR0_7 = 7 ; USART I/O Data Register bit 7 161 162; UCSR0A - USART Control and Status Register A 163.equ MPCM0 = 0 ; Multi-processor Communication Mode 164.equ U2X0 = 1 ; Double the USART transmission speed 165.equ UPE0 = 2 ; Parity Error 166.equ DOR0 = 3 ; Data overRun 167.equ FE0 = 4 ; Framing Error 168.equ UDRE0 = 5 ; USART Data Register Empty 169.equ TXC0 = 6 ; USART Transmitt Complete 170.equ RXC0 = 7 ; USART Receive Complete 171 172; UCSR0B - USART Control and Status Register B 173.equ TXB80 = 0 ; Transmit Data Bit 8 174.equ RXB80 = 1 ; Receive Data Bit 8 175.equ UCSZ02 = 2 ; Character Size 176.equ TXEN0 = 3 ; Transmitter Enable 177.equ RXEN0 = 4 ; Receiver Enable 178.equ UDRIE0 = 5 ; USART Data register Empty Interrupt Enable 179.equ TXCIE0 = 6 ; TX Complete Interrupt Enable 180.equ RXCIE0 = 7 ; RX Complete Interrupt Enable 181 182; UCSR0C - USART Control and Status Register C 183.equ UCPOL0 = 0 ; Clock Polarity 184.equ UCSZ00 = 1 ; Character Size 185.equ UCPHA0 = UCSZ00 ; For compatibility 186.equ UCSZ01 = 2 ; Character Size 187.equ UDORD0 = UCSZ01 ; For compatibility 188.equ USBS0 = 3 ; Stop Bit Select 189.equ UPM00 = 4 ; Parity Mode Bit 0 190.equ UPM01 = 5 ; Parity Mode Bit 1 191.equ UMSEL00 = 6 ; USART Mode Select 192.equ UMSEL0 = UMSEL00 ; For compatibility 193.equ UMSEL01 = 7 ; USART Mode Select 194.equ UMSEL1 = UMSEL01 ; For compatibility 195 196; UBRR0H - USART Baud Rate Register High Byte 197.equ UBRR8 = 0 ; USART Baud Rate Register bit 8 198.equ UBRR9 = 1 ; USART Baud Rate Register bit 9 199.equ UBRR10 = 2 ; USART Baud Rate Register bit 10 200.equ UBRR11 = 3 ; USART Baud Rate Register bit 11 201 202; UBRR0L - USART Baud Rate Register Low Byte 203.equ _UBRR0 = 0 ; USART Baud Rate Register bit 0 204.equ _UBRR1 = 1 ; USART Baud Rate Register bit 1 205.equ UBRR2 = 2 ; USART Baud Rate Register bit 2 206.equ UBRR3 = 3 ; USART Baud Rate Register bit 3 207.equ UBRR4 = 4 ; USART Baud Rate Register bit 4 208.equ UBRR5 = 5 ; USART Baud Rate Register bit 5 209.equ UBRR6 = 6 ; USART Baud Rate Register bit 6 210.equ UBRR7 = 7 ; USART Baud Rate Register bit 7 211 212 213; ***** TWI ************************** 214; TWAMR - TWI (Slave) Address Mask Register 215.equ TWAM0 = 1 ; 216.equ TWAMR0 = TWAM0 ; For compatibility 217.equ TWAM1 = 2 ; 218.equ TWAMR1 = TWAM1 ; For compatibility 219.equ TWAM2 = 3 ; 220.equ TWAMR2 = TWAM2 ; For compatibility 221.equ TWAM3 = 4 ; 222.equ TWAMR3 = TWAM3 ; For compatibility 223.equ TWAM4 = 5 ; 224.equ TWAMR4 = TWAM4 ; For compatibility 225.equ TWAM5 = 6 ; 226.equ TWAMR5 = TWAM5 ; For compatibility 227.equ TWAM6 = 7 ; 228.equ TWAMR6 = TWAM6 ; For compatibility 229 230; TWBR - TWI Bit Rate register 231.equ TWBR0 = 0 ; 232.equ TWBR1 = 1 ; 233.equ TWBR2 = 2 ; 234.equ TWBR3 = 3 ; 235.equ TWBR4 = 4 ; 236.equ TWBR5 = 5 ; 237.equ TWBR6 = 6 ; 238.equ TWBR7 = 7 ; 239 240; TWCR - TWI Control Register 241.equ TWIE = 0 ; TWI Interrupt Enable 242.equ TWEN = 2 ; TWI Enable Bit 243.equ TWWC = 3 ; TWI Write Collition Flag 244.equ TWSTO = 4 ; TWI Stop Condition Bit 245.equ TWSTA = 5 ; TWI Start Condition Bit 246.equ TWEA = 6 ; TWI Enable Acknowledge Bit 247.equ TWINT = 7 ; TWI Interrupt Flag 248 249; TWSR - TWI Status Register 250.equ TWPS0 = 0 ; TWI Prescaler 251.equ TWPS1 = 1 ; TWI Prescaler 252.equ TWS3 = 3 ; TWI Status 253.equ TWS4 = 4 ; TWI Status 254.equ TWS5 = 5 ; TWI Status 255.equ TWS6 = 6 ; TWI Status 256.equ TWS7 = 7 ; TWI Status 257 258; TWDR - TWI Data register 259.equ TWD0 = 0 ; TWI Data Register Bit 0 260.equ TWD1 = 1 ; TWI Data Register Bit 1 261.equ TWD2 = 2 ; TWI Data Register Bit 2 262.equ TWD3 = 3 ; TWI Data Register Bit 3 263.equ TWD4 = 4 ; TWI Data Register Bit 4 264.equ TWD5 = 5 ; TWI Data Register Bit 5 265.equ TWD6 = 6 ; TWI Data Register Bit 6 266.equ TWD7 = 7 ; TWI Data Register Bit 7 267 268; TWAR - TWI (Slave) Address register 269.equ TWGCE = 0 ; TWI General Call Recognition Enable Bit 270.equ TWA0 = 1 ; TWI (Slave) Address register Bit 0 271.equ TWA1 = 2 ; TWI (Slave) Address register Bit 1 272.equ TWA2 = 3 ; TWI (Slave) Address register Bit 2 273.equ TWA3 = 4 ; TWI (Slave) Address register Bit 3 274.equ TWA4 = 5 ; TWI (Slave) Address register Bit 4 275.equ TWA5 = 6 ; TWI (Slave) Address register Bit 5 276.equ TWA6 = 7 ; TWI (Slave) Address register Bit 6 277 278 279; ***** TIMER_COUNTER_1 ************** 280; TIMSK1 - Timer/Counter Interrupt Mask Register 281.equ TOIE1 = 0 ; Timer/Counter1 Overflow Interrupt Enable 282.equ OCIE1A = 1 ; Timer/Counter1 Output CompareA Match Interrupt Enable 283.equ OCIE1B = 2 ; Timer/Counter1 Output CompareB Match Interrupt Enable 284.equ ICIE1 = 5 ; Timer/Counter1 Input Capture Interrupt Enable 285 286; TIFR1 - Timer/Counter Interrupt Flag register 287.equ TOV1 = 0 ; Timer/Counter1 Overflow Flag 288.equ OCF1A = 1 ; Output Compare Flag 1A 289.equ OCF1B = 2 ; Output Compare Flag 1B 290.equ ICF1 = 5 ; Input Capture Flag 1 291 292; TCCR1A - Timer/Counter1 Control Register A 293.equ WGM10 = 0 ; Waveform Generation Mode 294.equ WGM11 = 1 ; Waveform Generation Mode 295.equ COM1B0 = 4 ; Compare Output Mode 1B, bit 0 296.equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1 297.equ COM1A0 = 6 ; Comparet Ouput Mode 1A, bit 0 298.equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1 299 300; TCCR1B - Timer/Counter1 Control Register B 301.equ CS10 = 0 ; Prescaler source of Timer/Counter 1 302.equ CS11 = 1 ; Prescaler source of Timer/Counter 1 303.equ CS12 = 2 ; Prescaler source of Timer/Counter 1 304.equ WGM12 = 3 ; Waveform Generation Mode 305.equ WGM13 = 4 ; Waveform Generation Mode 306.equ ICES1 = 6 ; Input Capture 1 Edge Select 307.equ ICNC1 = 7 ; Input Capture 1 Noise Canceler 308 309; TCCR1C - Timer/Counter1 Control Register C 310.equ FOC1B = 6 ; 311.equ FOC1A = 7 ; 312 313; GTCCR - General Timer/Counter Control Register 314.equ PSRSYNC = 0 ; Prescaler Reset Timer/Counter1 and Timer/Counter0 315.equ TSM = 7 ; Timer/Counter Synchronization Mode 316 317 318; ***** TIMER_COUNTER_2 ************** 319; TIMSK2 - Timer/Counter Interrupt Mask register 320.equ TOIE2 = 0 ; Timer/Counter2 Overflow Interrupt Enable 321.equ TOIE2A = TOIE2 ; For compatibility 322.equ OCIE2A = 1 ; Timer/Counter2 Output Compare Match A Interrupt Enable 323.equ OCIE2B = 2 ; Timer/Counter2 Output Compare Match B Interrupt Enable 324 325; TIFR2 - Timer/Counter Interrupt Flag Register 326.equ TOV2 = 0 ; Timer/Counter2 Overflow Flag 327.equ OCF2A = 1 ; Output Compare Flag 2A 328.equ OCF2B = 2 ; Output Compare Flag 2B 329 330; TCCR2A - Timer/Counter2 Control Register A 331.equ WGM20 = 0 ; Waveform Genration Mode 332.equ WGM21 = 1 ; Waveform Genration Mode 333.equ COM2B0 = 4 ; Compare Output Mode bit 0 334.equ COM2B1 = 5 ; Compare Output Mode bit 1 335.equ COM2A0 = 6 ; Compare Output Mode bit 1 336.equ COM2A1 = 7 ; Compare Output Mode bit 1 337 338; TCCR2B - Timer/Counter2 Control Register B 339.equ CS20 = 0 ; Clock Select bit 0 340.equ CS21 = 1 ; Clock Select bit 1 341.equ CS22 = 2 ; Clock Select bit 2 342.equ WGM22 = 3 ; Waveform Generation Mode 343.equ FOC2B = 6 ; Force Output Compare B 344.equ FOC2A = 7 ; Force Output Compare A 345 346; TCNT2 - Timer/Counter2 347.equ TCNT2_0 = 0 ; Timer/Counter 2 bit 0 348.equ TCNT2_1 = 1 ; Timer/Counter 2 bit 1 349.equ TCNT2_2 = 2 ; Timer/Counter 2 bit 2 350.equ TCNT2_3 = 3 ; Timer/Counter 2 bit 3 351.equ TCNT2_4 = 4 ; Timer/Counter 2 bit 4 352.equ TCNT2_5 = 5 ; Timer/Counter 2 bit 5 353.equ TCNT2_6 = 6 ; Timer/Counter 2 bit 6 354.equ TCNT2_7 = 7 ; Timer/Counter 2 bit 7 355 356; OCR2A - Timer/Counter2 Output Compare Register A 357.equ OCR2A_0 = 0 ; Timer/Counter2 Output Compare Register Bit 0 358.equ OCR2A_1 = 1 ; Timer/Counter2 Output Compare Register Bit 1 359.equ OCR2A_2 = 2 ; Timer/Counter2 Output Compare Register Bit 2 360.equ OCR2A_3 = 3 ; Timer/Counter2 Output Compare Register Bit 3 361.equ OCR2A_4 = 4 ; Timer/Counter2 Output Compare Register Bit 4 362.equ OCR2A_5 = 5 ; Timer/Counter2 Output Compare Register Bit 5 363.equ OCR2A_6 = 6 ; Timer/Counter2 Output Compare Register Bit 6 364.equ OCR2A_7 = 7 ; Timer/Counter2 Output Compare Register Bit 7 365 366; OCR2B - Timer/Counter2 Output Compare Register B 367.equ OCR2B_0 = 0 ; Timer/Counter2 Output Compare Register Bit 0 368.equ OCR2B_1 = 1 ; Timer/Counter2 Output Compare Register Bit 1 369.equ OCR2B_2 = 2 ; Timer/Counter2 Output Compare Register Bit 2 370.equ OCR2B_3 = 3 ; Timer/Counter2 Output Compare Register Bit 3 371.equ OCR2B_4 = 4 ; Timer/Counter2 Output Compare Register Bit 4 372.equ OCR2B_5 = 5 ; Timer/Counter2 Output Compare Register Bit 5 373.equ OCR2B_6 = 6 ; Timer/Counter2 Output Compare Register Bit 6 374.equ OCR2B_7 = 7 ; Timer/Counter2 Output Compare Register Bit 7 375 376; ASSR - Asynchronous Status Register 377.equ TCR2BUB = 0 ; Timer/Counter Control Register2 Update Busy 378.equ TCR2AUB = 1 ; Timer/Counter Control Register2 Update Busy 379.equ OCR2BUB = 2 ; Output Compare Register 2 Update Busy 380.equ OCR2AUB = 3 ; Output Compare Register2 Update Busy 381.equ TCN2UB = 4 ; Timer/Counter2 Update Busy 382.equ AS2 = 5 ; Asynchronous Timer/Counter2 383.equ EXCLK = 6 ; Enable External Clock Input 384 385; GTCCR - General Timer Counter Control register 386.equ PSRASY = 1 ; Prescaler Reset Timer/Counter2 387.equ PSR2 = PSRASY ; For compatibility 388;.equ TSM = 7 ; Timer/Counter Synchronization Mode 389 390 391; ***** AD_CONVERTER ***************** 392; ADMUX - The ADC multiplexer Selection Register 393.equ MUX0 = 0 ; Analog Channel and Gain Selection Bits 394.equ MUX1 = 1 ; Analog Channel and Gain Selection Bits 395.equ MUX2 = 2 ; Analog Channel and Gain Selection Bits 396.equ MUX3 = 3 ; Analog Channel and Gain Selection Bits 397.equ ADLAR = 5 ; Left Adjust Result 398.equ REFS0 = 6 ; Reference Selection Bit 0 399.equ REFS1 = 7 ; Reference Selection Bit 1 400 401; ADCSRA - The ADC Control and Status register A 402.equ ADPS0 = 0 ; ADC Prescaler Select Bits 403.equ ADPS1 = 1 ; ADC Prescaler Select Bits 404.equ ADPS2 = 2 ; ADC Prescaler Select Bits 405.equ ADIE = 3 ; ADC Interrupt Enable 406.equ ADIF = 4 ; ADC Interrupt Flag 407.equ ADATE = 5 ; ADC Auto Trigger Enable 408.equ ADSC = 6 ; ADC Start Conversion 409.equ ADEN = 7 ; ADC Enable 410 411; ADCSRB - The ADC Control and Status register B 412.equ ADTS0 = 0 ; ADC Auto Trigger Source bit 0 413.equ ADTS1 = 1 ; ADC Auto Trigger Source bit 1 414.equ ADTS2 = 2 ; ADC Auto Trigger Source bit 2 415.equ ACME = 6 ; 416 417; ADCH - ADC Data Register High Byte 418.equ ADCH0 = 0 ; ADC Data Register High Byte Bit 0 419.equ ADCH1 = 1 ; ADC Data Register High Byte Bit 1 420.equ ADCH2 = 2 ; ADC Data Register High Byte Bit 2 421.equ ADCH3 = 3 ; ADC Data Register High Byte Bit 3 422.equ ADCH4 = 4 ; ADC Data Register High Byte Bit 4 423.equ ADCH5 = 5 ; ADC Data Register High Byte Bit 5 424.equ ADCH6 = 6 ; ADC Data Register High Byte Bit 6 425.equ ADCH7 = 7 ; ADC Data Register High Byte Bit 7 426 427; ADCL - ADC Data Register Low Byte 428.equ ADCL0 = 0 ; ADC Data Register Low Byte Bit 0 429.equ ADCL1 = 1 ; ADC Data Register Low Byte Bit 1 430.equ ADCL2 = 2 ; ADC Data Register Low Byte Bit 2 431.equ ADCL3 = 3 ; ADC Data Register Low Byte Bit 3 432.equ ADCL4 = 4 ; ADC Data Register Low Byte Bit 4 433.equ ADCL5 = 5 ; ADC Data Register Low Byte Bit 5 434.equ ADCL6 = 6 ; ADC Data Register Low Byte Bit 6 435.equ ADCL7 = 7 ; ADC Data Register Low Byte Bit 7 436 437; DIDR0 - Digital Input Disable Register 438.equ ADC0D = 0 ; 439.equ ADC1D = 1 ; 440.equ ADC2D = 2 ; 441.equ ADC3D = 3 ; 442.equ ADC4D = 4 ; 443.equ ADC5D = 5 ; 444 445 446; ***** ANALOG_COMPARATOR ************ 447; ACSR - Analog Comparator Control And Status Register 448.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0 449.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1 450.equ ACIC = 2 ; Analog Comparator Input Capture Enable 451.equ ACIE = 3 ; Analog Comparator Interrupt Enable 452.equ ACI = 4 ; Analog Comparator Interrupt Flag 453.equ ACO = 5 ; Analog Compare Output 454.equ ACBG = 6 ; Analog Comparator Bandgap Select 455.equ ACD = 7 ; Analog Comparator Disable 456 457; DIDR1 - Digital Input Disable Register 1 458.equ AIN0D = 0 ; AIN0 Digital Input Disable 459.equ AIN1D = 1 ; AIN1 Digital Input Disable 460 461 462; ***** PORTB ************************ 463; PORTB - Port B Data Register 464.equ PORTB0 = 0 ; Port B Data Register bit 0 465.equ PB0 = 0 ; For compatibility 466.equ PORTB1 = 1 ; Port B Data Register bit 1 467.equ PB1 = 1 ; For compatibility 468.equ PORTB2 = 2 ; Port B Data Register bit 2 469.equ PB2 = 2 ; For compatibility 470.equ PORTB3 = 3 ; Port B Data Register bit 3 471.equ PB3 = 3 ; For compatibility 472.equ PORTB4 = 4 ; Port B Data Register bit 4 473.equ PB4 = 4 ; For compatibility 474.equ PORTB5 = 5 ; Port B Data Register bit 5 475.equ PB5 = 5 ; For compatibility 476.equ PORTB6 = 6 ; Port B Data Register bit 6 477.equ PB6 = 6 ; For compatibility 478.equ PORTB7 = 7 ; Port B Data Register bit 7 479.equ PB7 = 7 ; For compatibility 480 481; DDRB - Port B Data Direction Register 482.equ DDB0 = 0 ; Port B Data Direction Register bit 0 483.equ DDB1 = 1 ; Port B Data Direction Register bit 1 484.equ DDB2 = 2 ; Port B Data Direction Register bit 2 485.equ DDB3 = 3 ; Port B Data Direction Register bit 3 486.equ DDB4 = 4 ; Port B Data Direction Register bit 4 487.equ DDB5 = 5 ; Port B Data Direction Register bit 5 488.equ DDB6 = 6 ; Port B Data Direction Register bit 6 489.equ DDB7 = 7 ; Port B Data Direction Register bit 7 490 491; PINB - Port B Input Pins 492.equ PINB0 = 0 ; Port B Input Pins bit 0 493.equ PINB1 = 1 ; Port B Input Pins bit 1 494.equ PINB2 = 2 ; Port B Input Pins bit 2 495.equ PINB3 = 3 ; Port B Input Pins bit 3 496.equ PINB4 = 4 ; Port B Input Pins bit 4 497.equ PINB5 = 5 ; Port B Input Pins bit 5 498.equ PINB6 = 6 ; Port B Input Pins bit 6 499.equ PINB7 = 7 ; Port B Input Pins bit 7 500 501 502; ***** PORTC ************************ 503; PORTC - Port C Data Register 504.equ PORTC0 = 0 ; Port C Data Register bit 0 505.equ PC0 = 0 ; For compatibility 506.equ PORTC1 = 1 ; Port C Data Register bit 1 507.equ PC1 = 1 ; For compatibility 508.equ PORTC2 = 2 ; Port C Data Register bit 2 509.equ PC2 = 2 ; For compatibility 510.equ PORTC3 = 3 ; Port C Data Register bit 3 511.equ PC3 = 3 ; For compatibility 512.equ PORTC4 = 4 ; Port C Data Register bit 4 513.equ PC4 = 4 ; For compatibility 514.equ PORTC5 = 5 ; Port C Data Register bit 5 515.equ PC5 = 5 ; For compatibility 516.equ PORTC6 = 6 ; Port C Data Register bit 6 517.equ PC6 = 6 ; For compatibility 518 519; DDRC - Port C Data Direction Register 520.equ DDC0 = 0 ; Port C Data Direction Register bit 0 521.equ DDC1 = 1 ; Port C Data Direction Register bit 1 522.equ DDC2 = 2 ; Port C Data Direction Register bit 2 523.equ DDC3 = 3 ; Port C Data Direction Register bit 3 524.equ DDC4 = 4 ; Port C Data Direction Register bit 4 525.equ DDC5 = 5 ; Port C Data Direction Register bit 5 526.equ DDC6 = 6 ; Port C Data Direction Register bit 6 527 528; PINC - Port C Input Pins 529.equ PINC0 = 0 ; Port C Input Pins bit 0 530.equ PINC1 = 1 ; Port C Input Pins bit 1 531.equ PINC2 = 2 ; Port C Input Pins bit 2 532.equ PINC3 = 3 ; Port C Input Pins bit 3 533.equ PINC4 = 4 ; Port C Input Pins bit 4 534.equ PINC5 = 5 ; Port C Input Pins bit 5 535.equ PINC6 = 6 ; Port C Input Pins bit 6 536 537 538; ***** PORTD ************************ 539; PORTD - Port D Data Register 540.equ PORTD0 = 0 ; Port D Data Register bit 0 541.equ PD0 = 0 ; For compatibility 542.equ PORTD1 = 1 ; Port D Data Register bit 1 543.equ PD1 = 1 ; For compatibility 544.equ PORTD2 = 2 ; Port D Data Register bit 2 545.equ PD2 = 2 ; For compatibility 546.equ PORTD3 = 3 ; Port D Data Register bit 3 547.equ PD3 = 3 ; For compatibility 548.equ PORTD4 = 4 ; Port D Data Register bit 4 549.equ PD4 = 4 ; For compatibility 550.equ PORTD5 = 5 ; Port D Data Register bit 5 551.equ PD5 = 5 ; For compatibility 552.equ PORTD6 = 6 ; Port D Data Register bit 6 553.equ PD6 = 6 ; For compatibility 554.equ PORTD7 = 7 ; Port D Data Register bit 7 555.equ PD7 = 7 ; For compatibility 556 557; DDRD - Port D Data Direction Register 558.equ DDD0 = 0 ; Port D Data Direction Register bit 0 559.equ DDD1 = 1 ; Port D Data Direction Register bit 1 560.equ DDD2 = 2 ; Port D Data Direction Register bit 2 561.equ DDD3 = 3 ; Port D Data Direction Register bit 3 562.equ DDD4 = 4 ; Port D Data Direction Register bit 4 563.equ DDD5 = 5 ; Port D Data Direction Register bit 5 564.equ DDD6 = 6 ; Port D Data Direction Register bit 6 565.equ DDD7 = 7 ; Port D Data Direction Register bit 7 566 567; PIND - Port D Input Pins 568.equ PIND0 = 0 ; Port D Input Pins bit 0 569.equ PIND1 = 1 ; Port D Input Pins bit 1 570.equ PIND2 = 2 ; Port D Input Pins bit 2 571.equ PIND3 = 3 ; Port D Input Pins bit 3 572.equ PIND4 = 4 ; Port D Input Pins bit 4 573.equ PIND5 = 5 ; Port D Input Pins bit 5 574.equ PIND6 = 6 ; Port D Input Pins bit 6 575.equ PIND7 = 7 ; Port D Input Pins bit 7 576 577 578; ***** TIMER_COUNTER_0 ************** 579; TIMSK0 - Timer/Counter0 Interrupt Mask Register 580.equ TOIE0 = 0 ; Timer/Counter0 Overflow Interrupt Enable 581.equ OCIE0A = 1 ; Timer/Counter0 Output Compare Match A Interrupt Enable 582.equ OCIE0B = 2 ; Timer/Counter0 Output Compare Match B Interrupt Enable 583 584; TIFR0 - Timer/Counter0 Interrupt Flag register 585.equ TOV0 = 0 ; Timer/Counter0 Overflow Flag 586.equ OCF0A = 1 ; Timer/Counter0 Output Compare Flag 0A 587.equ OCF0B = 2 ; Timer/Counter0 Output Compare Flag 0B 588 589; TCCR0A - Timer/Counter Control Register A 590.equ WGM00 = 0 ; Waveform Generation Mode 591.equ WGM01 = 1 ; Waveform Generation Mode 592.equ COM0B0 = 4 ; Compare Output Mode, Fast PWm 593.equ COM0B1 = 5 ; Compare Output Mode, Fast PWm 594.equ COM0A0 = 6 ; Compare Output Mode, Phase Correct PWM Mode 595.equ COM0A1 = 7 ; Compare Output Mode, Phase Correct PWM Mode 596 597; TCCR0B - Timer/Counter Control Register B 598.equ CS00 = 0 ; Clock Select 599.equ CS01 = 1 ; Clock Select 600.equ CS02 = 2 ; Clock Select 601.equ WGM02 = 3 ; 602.equ FOC0B = 6 ; Force Output Compare B 603.equ FOC0A = 7 ; Force Output Compare A 604 605; TCNT0 - Timer/Counter0 606.equ TCNT0_0 = 0 ; 607.equ TCNT0_1 = 1 ; 608.equ TCNT0_2 = 2 ; 609.equ TCNT0_3 = 3 ; 610.equ TCNT0_4 = 4 ; 611.equ TCNT0_5 = 5 ; 612.equ TCNT0_6 = 6 ; 613.equ TCNT0_7 = 7 ; 614 615; OCR0A - Timer/Counter0 Output Compare Register 616.equ OCR0A_0 = 0 ; 617.equ OCR0A_1 = 1 ; 618.equ OCR0A_2 = 2 ; 619.equ OCR0A_3 = 3 ; 620.equ OCR0A_4 = 4 ; 621.equ OCR0A_5 = 5 ; 622.equ OCR0A_6 = 6 ; 623.equ OCR0A_7 = 7 ; 624 625; OCR0B - Timer/Counter0 Output Compare Register 626.equ OCR0B_0 = 0 ; 627.equ OCR0B_1 = 1 ; 628.equ OCR0B_2 = 2 ; 629.equ OCR0B_3 = 3 ; 630.equ OCR0B_4 = 4 ; 631.equ OCR0B_5 = 5 ; 632.equ OCR0B_6 = 6 ; 633.equ OCR0B_7 = 7 ; 634 635; GTCCR - General Timer/Counter Control Register 636;.equ PSRSYNC = 0 ; Prescaler Reset Timer/Counter1 and Timer/Counter0 637.equ PSR10 = PSRSYNC ; For compatibility 638;.equ TSM = 7 ; Timer/Counter Synchronization Mode 639 640 641; ***** EXTERNAL_INTERRUPT *********** 642; EICRA - External Interrupt Control Register 643.equ ISC00 = 0 ; External Interrupt Sense Control 0 Bit 0 644.equ ISC01 = 1 ; External Interrupt Sense Control 0 Bit 1 645.equ ISC10 = 2 ; External Interrupt Sense Control 1 Bit 0 646.equ ISC11 = 3 ; External Interrupt Sense Control 1 Bit 1 647 648; EIMSK - External Interrupt Mask Register 649.equ INT0 = 0 ; External Interrupt Request 0 Enable 650.equ INT1 = 1 ; External Interrupt Request 1 Enable 651 652; EIFR - External Interrupt Flag Register 653.equ INTF0 = 0 ; External Interrupt Flag 0 654.equ INTF1 = 1 ; External Interrupt Flag 1 655 656; PCICR - Pin Change Interrupt Control Register 657.equ PCIE0 = 0 ; Pin Change Interrupt Enable 0 658.equ PCIE1 = 1 ; Pin Change Interrupt Enable 1 659.equ PCIE2 = 2 ; Pin Change Interrupt Enable 2 660 661; PCMSK2 - Pin Change Mask Register 2 662.equ PCINT16 = 0 ; Pin Change Enable Mask 16 663.equ PCINT17 = 1 ; Pin Change Enable Mask 17 664.equ PCINT18 = 2 ; Pin Change Enable Mask 18 665.equ PCINT19 = 3 ; Pin Change Enable Mask 19 666.equ PCINT20 = 4 ; Pin Change Enable Mask 20 667.equ PCINT21 = 5 ; Pin Change Enable Mask 21 668.equ PCINT22 = 6 ; Pin Change Enable Mask 22 669.equ PCINT23 = 7 ; Pin Change Enable Mask 23 670 671; PCMSK1 - Pin Change Mask Register 1 672.equ PCINT8 = 0 ; Pin Change Enable Mask 8 673.equ PCINT9 = 1 ; Pin Change Enable Mask 9 674.equ PCINT10 = 2 ; Pin Change Enable Mask 10 675.equ PCINT11 = 3 ; Pin Change Enable Mask 11 676.equ PCINT12 = 4 ; Pin Change Enable Mask 12 677.equ PCINT13 = 5 ; Pin Change Enable Mask 13 678.equ PCINT14 = 6 ; Pin Change Enable Mask 14 679 680; PCMSK0 - Pin Change Mask Register 0 681.equ PCINT0 = 0 ; Pin Change Enable Mask 0 682.equ PCINT1 = 1 ; Pin Change Enable Mask 1 683.equ PCINT2 = 2 ; Pin Change Enable Mask 2 684.equ PCINT3 = 3 ; Pin Change Enable Mask 3 685.equ PCINT4 = 4 ; Pin Change Enable Mask 4 686.equ PCINT5 = 5 ; Pin Change Enable Mask 5 687.equ PCINT6 = 6 ; Pin Change Enable Mask 6 688.equ PCINT7 = 7 ; Pin Change Enable Mask 7 689 690; PCIFR - Pin Change Interrupt Flag Register 691.equ PCIF0 = 0 ; Pin Change Interrupt Flag 0 692.equ PCIF1 = 1 ; Pin Change Interrupt Flag 1 693.equ PCIF2 = 2 ; Pin Change Interrupt Flag 2 694 695 696; ***** SPI ************************** 697; SPDR - SPI Data Register 698.equ SPDR0 = 0 ; SPI Data Register bit 0 699.equ SPDR1 = 1 ; SPI Data Register bit 1 700.equ SPDR2 = 2 ; SPI Data Register bit 2 701.equ SPDR3 = 3 ; SPI Data Register bit 3 702.equ SPDR4 = 4 ; SPI Data Register bit 4 703.equ SPDR5 = 5 ; SPI Data Register bit 5 704.equ SPDR6 = 6 ; SPI Data Register bit 6 705.equ SPDR7 = 7 ; SPI Data Register bit 7 706 707; SPSR - SPI Status Register 708.equ SPI2X = 0 ; Double SPI Speed Bit 709.equ WCOL = 6 ; Write Collision Flag 710.equ SPIF = 7 ; SPI Interrupt Flag 711 712; SPCR - SPI Control Register 713.equ SPR0 = 0 ; SPI Clock Rate Select 0 714.equ SPR1 = 1 ; SPI Clock Rate Select 1 715.equ CPHA = 2 ; Clock Phase 716.equ CPOL = 3 ; Clock polarity 717.equ MSTR = 4 ; Master/Slave Select 718.equ DORD = 5 ; Data Order 719.equ SPE = 6 ; SPI Enable 720.equ SPIE = 7 ; SPI Interrupt Enable 721 722 723; ***** WATCHDOG ********************* 724; WDTCSR - Watchdog Timer Control Register 725.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0 726.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1 727.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2 728.equ WDE = 3 ; Watch Dog Enable 729.equ WDCE = 4 ; Watchdog Change Enable 730.equ WDP3 = 5 ; Watchdog Timer Prescaler Bit 3 731.equ WDIE = 6 ; Watchdog Timeout Interrupt Enable 732.equ WDIF = 7 ; Watchdog Timeout Interrupt Flag 733 734 735; ***** CPU ************************** 736; SREG - Status Register 737.equ SREG_C = 0 ; Carry Flag 738.equ SREG_Z = 1 ; Zero Flag 739.equ SREG_N = 2 ; Negative Flag 740.equ SREG_V = 3 ; Two's Complement Overflow Flag 741.equ SREG_S = 4 ; Sign Bit 742.equ SREG_H = 5 ; Half Carry Flag 743.equ SREG_T = 6 ; Bit Copy Storage 744.equ SREG_I = 7 ; Global Interrupt Enable 745 746; OSCCAL - Oscillator Calibration Value 747.equ CAL0 = 0 ; Oscillator Calibration Value Bit0 748.equ CAL1 = 1 ; Oscillator Calibration Value Bit1 749.equ CAL2 = 2 ; Oscillator Calibration Value Bit2 750.equ CAL3 = 3 ; Oscillator Calibration Value Bit3 751.equ CAL4 = 4 ; Oscillator Calibration Value Bit4 752.equ CAL5 = 5 ; Oscillator Calibration Value Bit5 753.equ CAL6 = 6 ; Oscillator Calibration Value Bit6 754.equ CAL7 = 7 ; Oscillator Calibration Value Bit7 755 756; CLKPR - Clock Prescale Register 757.equ CLKPS0 = 0 ; Clock Prescaler Select Bit 0 758.equ CLKPS1 = 1 ; Clock Prescaler Select Bit 1 759.equ CLKPS2 = 2 ; Clock Prescaler Select Bit 2 760.equ CLKPS3 = 3 ; Clock Prescaler Select Bit 3 761.equ CLKPCE = 7 ; Clock Prescaler Change Enable 762 763; SPMCSR - Store Program Memory Control and Status Register 764.equ SELFPRGEN = 0 ; Added for backwards compatibility 765.equ SPMEN = 0 ; Store Program Memory 766.equ PGERS = 1 ; Page Erase 767.equ PGWRT = 2 ; Page Write 768.equ BLBSET = 3 ; Boot Lock Bit Set 769.equ RWWSRE = 4 ; Read-While-Write section read enable 770.equ SIGRD = 5 ; Signature Row Read 771.equ RWWSB = 6 ; Read-While-Write Section Busy 772.equ SPMIE = 7 ; SPM Interrupt Enable 773 774; MCUCR - MCU Control Register 775.equ IVCE = 0 ; 776.equ IVSEL = 1 ; 777.equ PUD = 4 ; 778.equ BODSE = 5 ; BOD Sleep Enable 779.equ BODS = 6 ; BOD Sleep 780 781; MCUSR - MCU Status Register 782.equ PORF = 0 ; Power-on reset flag 783.equ EXTRF = 1 ; External Reset Flag 784.equ EXTREF = EXTRF ; For compatibility 785.equ BORF = 2 ; Brown-out Reset Flag 786.equ WDRF = 3 ; Watchdog Reset Flag 787 788; SMCR - Sleep Mode Control Register 789.equ SE = 0 ; Sleep Enable 790.equ SM0 = 1 ; Sleep Mode Select Bit 0 791.equ SM1 = 2 ; Sleep Mode Select Bit 1 792.equ SM2 = 3 ; Sleep Mode Select Bit 2 793 794; GPIOR2 - General Purpose I/O Register 2 795.equ GPIOR20 = 0 ; 796.equ GPIOR21 = 1 ; 797.equ GPIOR22 = 2 ; 798.equ GPIOR23 = 3 ; 799.equ GPIOR24 = 4 ; 800.equ GPIOR25 = 5 ; 801.equ GPIOR26 = 6 ; 802.equ GPIOR27 = 7 ; 803 804; GPIOR1 - General Purpose I/O Register 1 805.equ GPIOR10 = 0 ; 806.equ GPIOR11 = 1 ; 807.equ GPIOR12 = 2 ; 808.equ GPIOR13 = 3 ; 809.equ GPIOR14 = 4 ; 810.equ GPIOR15 = 5 ; 811.equ GPIOR16 = 6 ; 812.equ GPIOR17 = 7 ; 813 814; GPIOR0 - General Purpose I/O Register 0 815.equ GPIOR00 = 0 ; 816.equ GPIOR01 = 1 ; 817.equ GPIOR02 = 2 ; 818.equ GPIOR03 = 3 ; 819.equ GPIOR04 = 4 ; 820.equ GPIOR05 = 5 ; 821.equ GPIOR06 = 6 ; 822.equ GPIOR07 = 7 ; 823 824; PRR - Power Reduction Register 825.equ PRADC = 0 ; Power Reduction ADC 826.equ PRUSART0 = 1 ; Power Reduction USART 827.equ PRSPI = 2 ; Power Reduction Serial Peripheral Interface 828.equ PRTIM1 = 3 ; Power Reduction Timer/Counter1 829.equ PRTIM0 = 5 ; Power Reduction Timer/Counter0 830.equ PRTIM2 = 6 ; Power Reduction Timer/Counter2 831.equ PRTWI = 7 ; Power Reduction TWI 832 833 834; ***** EEPROM *********************** 835; EEARL - EEPROM Address Register Low Byte 836.equ EEAR0 = 0 ; EEPROM Read/Write Access Bit 0 837.equ EEAR1 = 1 ; EEPROM Read/Write Access Bit 1 838.equ EEAR2 = 2 ; EEPROM Read/Write Access Bit 2 839.equ EEAR3 = 3 ; EEPROM Read/Write Access Bit 3 840.equ EEAR4 = 4 ; EEPROM Read/Write Access Bit 4 841.equ EEAR5 = 5 ; EEPROM Read/Write Access Bit 5 842.equ EEAR6 = 6 ; EEPROM Read/Write Access Bit 6 843.equ EEAR7 = 7 ; EEPROM Read/Write Access Bit 7 844 845; EEARH - EEPROM Address Register High Byte 846.equ EEAR8 = 0 ; EEPROM Read/Write Access Bit 8 847.equ EEAR9 = 1 ; EEPROM Read/Write Access Bit 9 848 849; EEDR - EEPROM Data Register 850.equ EEDR0 = 0 ; EEPROM Data Register bit 0 851.equ EEDR1 = 1 ; EEPROM Data Register bit 1 852.equ EEDR2 = 2 ; EEPROM Data Register bit 2 853.equ EEDR3 = 3 ; EEPROM Data Register bit 3 854.equ EEDR4 = 4 ; EEPROM Data Register bit 4 855.equ EEDR5 = 5 ; EEPROM Data Register bit 5 856.equ EEDR6 = 6 ; EEPROM Data Register bit 6 857.equ EEDR7 = 7 ; EEPROM Data Register bit 7 858 859; EECR - EEPROM Control Register 860.equ EERE = 0 ; EEPROM Read Enable 861.equ EEPE = 1 ; EEPROM Write Enable 862.equ EEMPE = 2 ; EEPROM Master Write Enable 863.equ EERIE = 3 ; EEPROM Ready Interrupt Enable 864.equ EEPM0 = 4 ; EEPROM Programming Mode Bit 0 865.equ EEPM1 = 5 ; EEPROM Programming Mode Bit 1 866 867 868 869; ***** LOCKSBITS ******************************************************** 870.equ LB1 = 0 ; Lock bit 871.equ LB2 = 1 ; Lock bit 872.equ BLB01 = 2 ; Boot Lock bit 873.equ BLB02 = 3 ; Boot Lock bit 874.equ BLB11 = 4 ; Boot lock bit 875.equ BLB12 = 5 ; Boot lock bit 876 877 878; ***** FUSES ************************************************************ 879; LOW fuse bits 880.equ CKSEL0 = 0 ; Select Clock Source 881.equ CKSEL1 = 1 ; Select Clock Source 882.equ CKSEL2 = 2 ; Select Clock Source 883.equ CKSEL3 = 3 ; Select Clock Source 884.equ SUT0 = 4 ; Select start-up time 885.equ SUT1 = 5 ; Select start-up time 886.equ CKOUT = 6 ; Clock output 887.equ CKDIV8 = 7 ; Divide clock by 8 888 889; HIGH fuse bits 890.equ BOOTRST = 0 ; Select reset vector 891.equ BOOTSZ0 = 1 ; Select boot size 892.equ BOOTSZ1 = 2 ; Select boot size 893.equ EESAVE = 3 ; EEPROM memory is preserved through chip erase 894.equ WDTON = 4 ; Watchdog Timer Always On 895.equ SPIEN = 5 ; Enable Serial programming and Data Downloading 896.equ DWEN = 6 ; debugWIRE Enable 897.equ RSTDISBL = 7 ; External reset disable 898 899; EXTENDED fuse bits 900.equ BODLEVEL0 = 0 ; Brown-out Detector trigger level 901.equ BODLEVEL1 = 1 ; Brown-out Detector trigger level 902.equ BODLEVEL2 = 2 ; Brown-out Detector trigger level 903 904 905 906; ***** CPU REGISTER DEFINITIONS ***************************************** 907.def XH = r27 908.def XL = r26 909.def YH = r29 910.def YL = r28 911.def ZH = r31 912.def ZL = r30 913 914 915 916; ***** DATA MEMORY DECLARATIONS ***************************************** 917.equ FLASHEND = 0x3fff ; Note: Word address 918.equ IOEND = 0x00ff 919.equ SRAM_START = 0x0100 920.equ SRAM_SIZE = 2048 921.equ RAMEND = 0x08ff 922.equ XRAMEND = 0x0000 923.equ E2END = 0x03ff 924.equ EEPROMEND = 0x03ff 925.equ EEADRBITS = 10 926#pragma AVRPART MEMORY PROG_FLASH 32768 927#pragma AVRPART MEMORY EEPROM 1024 928#pragma AVRPART MEMORY INT_SRAM SIZE 2048 929#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x100 930 931 932 933; ***** BOOTLOADER DECLARATIONS ****************************************** 934.equ NRWW_START_ADDR = 0x3800 935.equ NRWW_STOP_ADDR = 0x3fff 936.equ RWW_START_ADDR = 0x0 937.equ RWW_STOP_ADDR = 0x37ff 938.equ PAGESIZE = 64 939.equ FIRSTBOOTSTART = 0x3f00 940.equ SECONDBOOTSTART = 0x3e00 941.equ THIRDBOOTSTART = 0x3c00 942.equ FOURTHBOOTSTART = 0x3800 943.equ SMALLBOOTSTART = FIRSTBOOTSTART 944.equ LARGEBOOTSTART = FOURTHBOOTSTART 945 946 947 948; ***** INTERRUPT VECTORS ************************************************ 949.equ INT0addr = 0x0002 ; External Interrupt Request 0 950.equ INT1addr = 0x0004 ; External Interrupt Request 1 951.equ PCI0addr = 0x0006 ; Pin Change Interrupt Request 0 952.equ PCI1addr = 0x0008 ; Pin Change Interrupt Request 0 953.equ PCI2addr = 0x000a ; Pin Change Interrupt Request 1 954.equ WDTaddr = 0x000c ; Watchdog Time-out Interrupt 955.equ OC2Aaddr = 0x000e ; Timer/Counter2 Compare Match A 956.equ OC2Baddr = 0x0010 ; Timer/Counter2 Compare Match A 957.equ OVF2addr = 0x0012 ; Timer/Counter2 Overflow 958.equ ICP1addr = 0x0014 ; Timer/Counter1 Capture Event 959.equ OC1Aaddr = 0x0016 ; Timer/Counter1 Compare Match A 960.equ OC1Baddr = 0x0018 ; Timer/Counter1 Compare Match B 961.equ OVF1addr = 0x001a ; Timer/Counter1 Overflow 962.equ OC0Aaddr = 0x001c ; TimerCounter0 Compare Match A 963.equ OC0Baddr = 0x001e ; TimerCounter0 Compare Match B 964.equ OVF0addr = 0x0020 ; Timer/Couner0 Overflow 965.equ SPIaddr = 0x0022 ; SPI Serial Transfer Complete 966.equ URXCaddr = 0x0024 ; USART Rx Complete 967.equ UDREaddr = 0x0026 ; USART, Data Register Empty 968.equ UTXCaddr = 0x0028 ; USART Tx Complete 969.equ ADCCaddr = 0x002a ; ADC Conversion Complete 970.equ ERDYaddr = 0x002c ; EEPROM Ready 971.equ ACIaddr = 0x002e ; Analog Comparator 972.equ TWIaddr = 0x0030 ; Two-wire Serial Interface 973.equ SPMRaddr = 0x0032 ; Store Program Memory Read 974 975.equ INT_VECTORS_SIZE = 52 ; size in words 976 977#endif /* _M328PDEF_INC_ */ 978 979; ***** END OF FILE ****************************************************** 980