1;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ******************** 2;***** Created: 2005-01-11 10:31 ******* Source: ATtiny13.xml ************ 3;************************************************************************* 4;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y 5;* 6;* Number : AVR000 7;* File Name : "tn13def.inc" 8;* Title : Register/Bit Definitions for the ATtiny13 9;* Date : 2005-01-11 10;* Version : 2.14 11;* Support E-mail : avr@atmel.com 12;* Target MCU : ATtiny13 13;* 14;* DESCRIPTION 15;* When including this file in the assembly program file, all I/O register 16;* names and I/O register bit names appearing in the data book can be used. 17;* In addition, the six registers forming the three data pointers X, Y and 18;* Z have been assigned names XL - ZH. Highest RAM address for Internal 19;* SRAM is also defined 20;* 21;* The Register names are represented by their hexadecimal address. 22;* 23;* The Register Bit names are represented by their bit number (0-7). 24;* 25;* Please observe the difference in using the bit names with instructions 26;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" 27;* (skip if bit in register set/cleared). The following example illustrates 28;* this: 29;* 30;* in r16,PORTB ;read PORTB latch 31;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#) 32;* out PORTB,r16 ;output to PORTB 33;* 34;* in r16,TIFR ;read the Timer Interrupt Flag Register 35;* sbrc r16,TOV0 ;test the overflow flag (use bit#) 36;* rjmp TOV0_is_set ;jump if set 37;* ... ;otherwise do something else 38;************************************************************************* 39 40#ifndef _TN13DEF_INC_ 41#define _TN13DEF_INC_ 42 43 44#pragma partinc 0 45 46; ***** SPECIFY DEVICE *************************************************** 47.device ATtiny13 48#pragma AVRPART ADMIN PART_NAME ATtiny13 49.equ SIGNATURE_000 = 0x1e 50.equ SIGNATURE_001 = 0x90 51.equ SIGNATURE_002 = 0x07 52 53#pragma AVRPART CORE CORE_VERSION V2 54#pragma AVRPART CORE NEW_INSTRUCTIONS lpm rd,z+ 55 56 57; ***** I/O REGISTER DEFINITIONS ***************************************** 58; NOTE: 59; Definitions marked "MEMORY MAPPED"are extended I/O ports 60; and cannot be used with IN/OUT instructions 61.equ SREG = 0x3f 62.equ SPL = 0x3d 63.equ GIMSK = 0x3b 64.equ GIFR = 0x3a 65.equ TIMSK0 = 0x39 66.equ TIFR0 = 0x38 67.equ SPMCSR = 0x37 68.equ OCR0A = 0x36 69.equ MCUCR = 0x35 70.equ MCUSR = 0x34 71.equ TCCR0B = 0x33 72.equ TCNT0 = 0x32 73.equ OSCCAL = 0x31 74.equ TCCR0A = 0x2f 75.equ DWDR = 0x2e 76.equ OCR0B = 0x29 77.equ GTCCR = 0x28 78.equ CLKPR = 0x26 79.equ WDTCR = 0x21 80.equ EEAR = 0x1e 81.equ EEDR = 0x1d 82.equ EECR = 0x1c 83.equ PORTB = 0x18 84.equ DDRB = 0x17 85.equ PINB = 0x16 86.equ PCMSK = 0x15 87.equ DIDR0 = 0x14 88.equ ACSR = 0x08 89.equ ADMUX = 0x07 90.equ ADCSRA = 0x06 91.equ ADCH = 0x05 92.equ ADCL = 0x04 93.equ ADCSRB = 0x03 94 95 96; ***** BIT DEFINITIONS ************************************************** 97 98; ***** AD_CONVERTER ***************** 99; ADMUX - The ADC multiplexer Selection Register 100.equ MUX0 = 0 ; Analog Channel and Gain Selection Bits 101.equ MUX1 = 1 ; Analog Channel and Gain Selection Bits 102.equ ADLAR = 5 ; Left Adjust Result 103.equ REFS0 = 6 ; Reference Selection Bit 0 104 105; ADCSRA - The ADC Control and Status register 106.equ ADPS0 = 0 ; ADC Prescaler Select Bits 107.equ ADPS1 = 1 ; ADC Prescaler Select Bits 108.equ ADPS2 = 2 ; ADC Prescaler Select Bits 109.equ ADIE = 3 ; ADC Interrupt Enable 110.equ ADIF = 4 ; ADC Interrupt Flag 111.equ ADATE = 5 ; ADC Auto Trigger Enable 112.equ ADSC = 6 ; ADC Start Conversion 113.equ ADEN = 7 ; ADC Enable 114 115; ADCH - ADC Data Register High Byte 116.equ ADCH0 = 0 ; ADC Data Register High Byte Bit 0 117.equ ADCH1 = 1 ; ADC Data Register High Byte Bit 1 118.equ ADCH2 = 2 ; ADC Data Register High Byte Bit 2 119.equ ADCH3 = 3 ; ADC Data Register High Byte Bit 3 120.equ ADCH4 = 4 ; ADC Data Register High Byte Bit 4 121.equ ADCH5 = 5 ; ADC Data Register High Byte Bit 5 122.equ ADCH6 = 6 ; ADC Data Register High Byte Bit 6 123.equ ADCH7 = 7 ; ADC Data Register High Byte Bit 7 124 125; ADCL - ADC Data Register Low Byte 126.equ ADCL0 = 0 ; ADC Data Register Low Byte Bit 0 127.equ ADCL1 = 1 ; ADC Data Register Low Byte Bit 1 128.equ ADCL2 = 2 ; ADC Data Register Low Byte Bit 2 129.equ ADCL3 = 3 ; ADC Data Register Low Byte Bit 3 130.equ ADCL4 = 4 ; ADC Data Register Low Byte Bit 4 131.equ ADCL5 = 5 ; ADC Data Register Low Byte Bit 5 132.equ ADCL6 = 6 ; ADC Data Register Low Byte Bit 6 133.equ ADCL7 = 7 ; ADC Data Register Low Byte Bit 7 134 135; ADCSRB - ADC Control and Status Register B 136.equ ADTS0 = 0 ; ADC Auto Trigger Source 0 137.equ ADTS1 = 1 ; ADC Auto Trigger Source 1 138.equ ADTS2 = 2 ; ADC Auto Trigger Source 2 139 140; DIDR0 - Digital Input Disable Register 0 141.equ ADC1D = 2 ; ADC2 Digital input Disable 142.equ ADC3D = 3 ; ADC3 Digital input Disable 143.equ ADC2D = 4 ; ADC2 Digital input Disable 144.equ ADC0D = 5 ; ADC0 Digital input Disable 145 146 147; ***** ANALOG_COMPARATOR ************ 148; ADCSRB - ADC Control and Status Register B 149.equ ACME = 6 ; Analog Comparator Multiplexer Enable 150 151; ACSR - Analog Comparator Control And Status Register 152.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0 153.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1 154.equ ACIE = 3 ; Analog Comparator Interrupt Enable 155.equ ACI = 4 ; Analog Comparator Interrupt Flag 156.equ ACO = 5 ; Analog Compare Output 157.equ ACBG = 6 ; Analog Comparator Bandgap Select 158.equ AINBG = ACBG ; For compatibility 159.equ ACD = 7 ; Analog Comparator Disable 160 161; DIDR0 - 162.equ AIN0D = 0 ; AIN0 Digital Input Disable 163.equ AIN1D = 1 ; AIN1 Digital Input Disable 164 165 166; ***** EEPROM *********************** 167; EEAR - EEPROM Read/Write Access 168.equ EEARL = EEAR ; For compatibility 169.equ EEAR0 = 0 ; EEPROM Read/Write Access bit 0 170.equ EEAR1 = 1 ; EEPROM Read/Write Access bit 1 171.equ EEAR2 = 2 ; EEPROM Read/Write Access bit 2 172.equ EEAR3 = 3 ; EEPROM Read/Write Access bit 3 173.equ EEAR4 = 4 ; EEPROM Read/Write Access bit 4 174.equ EEAR5 = 5 ; EEPROM Read/Write Access bit 5 175 176; EEDR - EEPROM Data Register 177.equ EEDR0 = 0 ; EEPROM Data Register bit 0 178.equ EEDR1 = 1 ; EEPROM Data Register bit 1 179.equ EEDR2 = 2 ; EEPROM Data Register bit 2 180.equ EEDR3 = 3 ; EEPROM Data Register bit 3 181.equ EEDR4 = 4 ; EEPROM Data Register bit 4 182.equ EEDR5 = 5 ; EEPROM Data Register bit 5 183.equ EEDR6 = 6 ; EEPROM Data Register bit 6 184.equ EEDR7 = 7 ; EEPROM Data Register bit 7 185 186; EECR - EEPROM Control Register 187.equ EERE = 0 ; EEPROM Read Enable 188.equ EEWE = 1 ; EEPROM Write Enable 189.equ EEPE = EEWE ; For compatibility 190.equ EEMWE = 2 ; EEPROM Master Write Enable 191.equ EEMPE = EEMWE ; For compatibility 192.equ EERIE = 3 ; EEProm Ready Interrupt Enable 193.equ EEPM0 = 4 ; 194.equ EEPM1 = 5 ; 195 196 197; ***** CPU ************************** 198; SREG - Status Register 199.equ SREG_C = 0 ; Carry Flag 200.equ SREG_Z = 1 ; Zero Flag 201.equ SREG_N = 2 ; Negative Flag 202.equ SREG_V = 3 ; Two's Complement Overflow Flag 203.equ SREG_S = 4 ; Sign Bit 204.equ SREG_H = 5 ; Half Carry Flag 205.equ SREG_T = 6 ; Bit Copy Storage 206.equ SREG_I = 7 ; Global Interrupt Enable 207 208; SPL - Stack Pointer Low Byte 209.equ SP0 = 0 ; Stack Pointer Bit 0 210.equ SP1 = 1 ; Stack Pointer Bit 1 211.equ SP2 = 2 ; Stack Pointer Bit 2 212.equ SP3 = 3 ; Stack Pointer Bit 3 213.equ SP4 = 4 214.equ SP5 = 5 ; Stack Pointer Bit 5 215.equ SP6 = 6 ; Stack Pointer Bit 6 216.equ SP7 = 7 ; Stack Pointer Bit 7 217 218; MCUCR - MCU Control Register 219.equ ISC00 = 0 ; Interrupt Sense Control 0 bit 0 220.equ ISC01 = 1 ; Interrupt Sense Control 0 bit 1 221.equ SM0 = 3 ; Sleep Mode Select Bit 0 222.equ SM1 = 4 ; Sleep Mode Select Bit 1 223.equ SE = 5 ; Sleep Enable 224.equ PUD = 6 ; Pull-up Disable 225 226; MCUSR - MCU Status register 227.equ PORF = 0 ; Power-On Reset Flag 228.equ EXTRF = 1 ; External Reset Flag 229.equ BORF = 2 ; Brown-out Reset Flag 230.equ WDRF = 3 ; Watchdog Reset Flag 231 232; OSCCAL - Oscillator Calibration Register 233.equ CAL0 = 0 ; Oscillatro Calibration Value Bit 0 234.equ CAL1 = 1 ; Oscillatro Calibration Value Bit 1 235.equ CAL2 = 2 ; Oscillatro Calibration Value Bit 2 236.equ CAL3 = 3 ; Oscillatro Calibration Value Bit 3 237.equ CAL4 = 4 ; Oscillatro Calibration Value Bit 4 238.equ CAL5 = 5 ; Oscillatro Calibration Value Bit 5 239.equ CAL6 = 6 ; Oscillatro Calibration Value Bit 6 240 241; CLKPR - Clock Prescale Register 242.equ CLKPS0 = 0 ; Clock Prescaler Select Bit 0 243.equ CLKPS1 = 1 ; Clock Prescaler Select Bit 1 244.equ CLKPS2 = 2 ; Clock Prescaler Select Bit 2 245.equ CLKPS3 = 3 ; Clock Prescaler Select Bit 3 246.equ CLKPCE = 7 ; Clock Prescaler Change Enable 247 248; DWDR - Debug Wire Data Register 249.equ DWDR0 = 0 ; Debug Wire Data Register Bit 0 250.equ DWDR1 = 1 ; Debug Wire Data Register Bit 1 251.equ DWDR2 = 2 ; Debug Wire Data Register Bit 2 252.equ DWDR3 = 3 ; Debug Wire Data Register Bit 3 253.equ DWDR4 = 4 ; Debug Wire Data Register Bit 4 254.equ DWDR5 = 5 ; Debug Wire Data Register Bit 5 255.equ DWDR6 = 6 ; Debug Wire Data Register Bit 6 256.equ DWDR7 = 7 ; Debug Wire Data Register Bit 7 257 258; SPMCSR - Store Program Memory Control and Status Register 259.equ SPMEN = 0 ; Store program Memory Enable 260.equ PGERS = 1 ; Page Erase 261.equ PGWRT = 2 ; Page Write 262.equ RFLB = 3 ; Read Fuse and Lock Bits 263.equ CTPB = 4 ; Clear Temporary Page Buffer 264 265 266; ***** PORTB ************************ 267; PORTB - Data Register, Port B 268.equ PORTB0 = 0 ; 269.equ PB0 = 0 ; For compatibility 270.equ PORTB1 = 1 ; 271.equ PB1 = 1 ; For compatibility 272.equ PORTB2 = 2 ; 273.equ PB2 = 2 ; For compatibility 274.equ PORTB3 = 3 ; 275.equ PB3 = 3 ; For compatibility 276.equ PORTB4 = 4 ; 277.equ PB4 = 4 ; For compatibility 278.equ PORTB5 = 5 ; 279.equ PB5 = 5 ; For compatibility 280 281; DDRB - Data Direction Register, Port B 282.equ DDB0 = 0 ; 283.equ DDB1 = 1 ; 284.equ DDB2 = 2 ; 285.equ DDB3 = 3 ; 286.equ DDB4 = 4 ; 287.equ DDB5 = 5 ; 288 289; PINB - Input Pins, Port B 290.equ PINB0 = 0 ; 291.equ PINB1 = 1 ; 292.equ PINB2 = 2 ; 293.equ PINB3 = 3 ; 294.equ PINB4 = 4 ; 295.equ PINB5 = 5 ; 296 297 298; ***** EXTERNAL_INTERRUPT *********** 299; MCUCR - MCU Control Register 300;.equ ISC00 = 0 ; Interrupt Sense Control 0 Bit 0 301;.equ ISC01 = 1 ; Interrupt Sense Control 0 Bit 1 302 303; GIMSK - General Interrupt Mask Register 304.equ GICR = GIMSK ; For compatibility 305.equ PCIE = 5 ; Pin Change Interrupt Enable 306.equ INT0 = 6 ; External Interrupt Request 0 Enable 307 308; GIFR - General Interrupt Flag register 309.equ PCIF = 5 ; Pin Change Interrupt Flag 310.equ INTF0 = 6 ; External Interrupt Flag 0 311 312; PCMSK - Pin Change Enable Mask 313.equ PCINT0 = 0 ; Pin Change Enable Mask Bit 0 314.equ PCINT1 = 1 ; Pin Change Enable Mask Bit 1 315.equ PCINT2 = 2 ; Pin Change Enable Mask Bit 2 316.equ PCINT3 = 3 ; Pin Change Enable Mask Bit 3 317.equ PCINT4 = 4 ; Pin Change Enable Mask Bit 4 318.equ PCINT5 = 5 ; Pin Change Enable Mask Bit 5 319 320 321; ***** TIMER_COUNTER_0 ************** 322; TIMSK0 - Timer/Counter0 Interrupt Mask Register 323.equ TOIE0 = 1 ; Timer/Counter0 Overflow Interrupt Enable 324.equ OCIE0A = 2 ; Timer/Counter0 Output Compare Match A Interrupt Enable 325.equ OCIE0B = 3 ; Timer/Counter0 Output Compare Match B Interrupt Enable 326 327; TIFR0 - Timer/Counter0 Interrupt Flag register 328.equ TOV0 = 1 ; Timer/Counter0 Overflow Flag 329.equ OCF0A = 2 ; Timer/Counter0 Output Compare Flag 0A 330.equ OCF0B = 3 ; Timer/Counter0 Output Compare Flag 0B 331 332; OCR0A - Timer/Counter0 Output Compare Register 333.equ OCR0_0 = 0 ; 334.equ OCR0_1 = 1 ; 335.equ OCR0_2 = 2 ; 336.equ OCR0_3 = 3 ; 337.equ OCR0_4 = 4 ; 338.equ OCR0_5 = 5 ; 339.equ OCR0_6 = 6 ; 340.equ OCR0_7 = 7 ; 341 342; TCCR0A - Timer/Counter Control Register A 343.equ WGM00 = 0 ; Waveform Generation Mode 344.equ WGM01 = 1 ; Waveform Generation Mode 345.equ COM0B0 = 4 ; Compare Match Output B Mode 346.equ COM0B1 = 5 ; Compare Match Output B Mode 347.equ COM0A0 = 6 ; Compare Match Output A Mode 348.equ COM0A1 = 7 ; Compare Match Output A Mode 349 350; TCNT0 - Timer/Counter0 351.equ TCNT0_0 = 0 ; 352.equ TCNT0_1 = 1 ; 353.equ TCNT0_2 = 2 ; 354.equ TCNT0_3 = 3 ; 355.equ TCNT0_4 = 4 ; 356.equ TCNT0_5 = 5 ; 357.equ TCNT0_6 = 6 ; 358.equ TCNT0_7 = 7 ; 359 360; TCCR0B - Timer/Counter Control Register B 361.equ CS00 = 0 ; Clock Select 362.equ CS01 = 1 ; Clock Select 363.equ CS02 = 2 ; Clock Select 364.equ WGM02 = 3 ; Waveform Generation Mode 365.equ FOC0B = 6 ; Force Output Compare B 366.equ FOC0A = 7 ; Force Output Compare A 367 368; OCR0B - Timer/Counter0 Output Compare Register 369;.equ OCR0_0 = 0 ; 370;.equ OCR0_1 = 1 ; 371;.equ OCR0_2 = 2 ; 372;.equ OCR0_3 = 3 ; 373;.equ OCR0_4 = 4 ; 374;.equ OCR0_5 = 5 ; 375;.equ OCR0_6 = 6 ; 376;.equ OCR0_7 = 7 ; 377 378; GTCCR - General Timer Conuter Register 379.equ PSR10 = 0 ; Prescaler Reset Timer/Counter0 380.equ TSM = 7 ; Timer/Counter Synchronization Mode 381 382 383; ***** WATCHDOG ********************* 384; WDTCR - Watchdog Timer Control Register 385.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0 386.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1 387.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2 388.equ WDE = 3 ; Watch Dog Enable 389.equ WDCE = 4 ; Watchdog Change Enable 390.equ WDP3 = 5 ; Watchdog Timer Prescaler Bit 3 391.equ WDTIE = 6 ; Watchdog Timeout Interrupt Enable 392.equ WDTIF = 7 ; Watchdog Timeout Interrupt Flag 393 394 395 396; ***** LOCKSBITS ******************************************************** 397.equ LB1 = 0 ; Lockbit 398.equ LB2 = 1 ; Lockbit 399 400 401; ***** FUSES ************************************************************ 402; LOW fuse bits 403.equ CKSEL0 = 0 ; Select Clock Source 404.equ CKSEL1 = 1 ; Select Clock Source 405.equ SUT0 = 2 ; Select start-up time 406.equ SUT1 = 3 ; Select start-up time 407.equ CKDIV8 = 4 ; Start up with system clock divided by 8 408.equ WDTON = 5 ; Watch dog timer always on 409.equ EESAVE = 6 ; Keep EEprom contents during chip erase 410.equ SPIEN = 7 ; SPI programming enable 411 412; HIGH fuse bits 413.equ RSTDISBL = 0 ; Disable external reset 414.equ BODLEVEL0 = 1 ; Enable BOD and select level 415.equ BODLEVEL1 = 2 ; Enable BOD and select level 416.equ DWEN = 3 ; DebugWire Enable 417.equ SELFPRGEN = 4 ; Self Programming Enable 418 419 420 421; ***** CPU REGISTER DEFINITIONS ***************************************** 422.def XH = r27 423.def XL = r26 424.def YH = r29 425.def YL = r28 426.def ZH = r31 427.def ZL = r30 428 429 430 431; ***** DATA MEMORY DECLARATIONS ***************************************** 432.equ FLASHEND = 0x01ff ; Note: Word address 433.equ IOEND = 0x003f 434.equ SRAM_START = 0x0060 435.equ SRAM_SIZE = 64 436.equ RAMEND = 0x009f 437.equ XRAMEND = 0x0000 438.equ E2END = 0x003f 439.equ EEPROMEND = 0x003f 440.equ EEADRBITS = 6 441#pragma AVRPART MEMORY PROG_FLASH 1024 442#pragma AVRPART MEMORY EEPROM 64 443#pragma AVRPART MEMORY INT_SRAM SIZE 64 444#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x60 445 446 447 448; ***** BOOTLOADER DECLARATIONS ****************************************** 449.equ PAGESIZE = 16 450 451 452 453; ***** INTERRUPT VECTORS ************************************************ 454.equ INT0addr = 0x0001 ; External Interrupt 0 455.equ PCI0addr = 0x0002 ; External Interrupt Request 0 456.equ OVF0addr = 0x0003 ; Timer/Counter0 Overflow 457.equ ERDYaddr = 0x0004 ; EEPROM Ready 458.equ ACIaddr = 0x0005 ; Analog Comparator 459.equ OC0Aaddr = 0x0006 ; Timer/Counter Compare Match A 460.equ OC0Baddr = 0x0007 ; Timer/Counter Compare Match B 461.equ WDTaddr = 0x0008 ; Watchdog Time-out 462.equ ADCCaddr = 0x0009 ; ADC Conversion Complete 463 464.equ INT_VECTORS_SIZE = 10 ; size in words 465 466#endif /* _TN13DEF_INC_ */ 467 468; ***** END OF FILE ****************************************************** 469