1;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ********************
2;***** Created: 2005-01-11 10:31 ******* Source: ATtiny22.xml ************
3;*************************************************************************
4;* A P P L I C A T I O N   N O T E   F O R   T H E   A V R   F A M I L Y
5;*
6;* Number            : AVR000
7;* File Name         : "tn22def.inc"
8;* Title             : Register/Bit Definitions for the ATtiny22
9;* Date              : 2005-01-11
10;* Version           : 2.14
11;* Support E-mail    : avr@atmel.com
12;* Target MCU        : ATtiny22
13;*
14;* DESCRIPTION
15;* When including this file in the assembly program file, all I/O register
16;* names and I/O register bit names appearing in the data book can be used.
17;* In addition, the six registers forming the three data pointers X, Y and
18;* Z have been assigned names XL - ZH. Highest RAM address for Internal
19;* SRAM is also defined
20;*
21;* The Register names are represented by their hexadecimal address.
22;*
23;* The Register Bit names are represented by their bit number (0-7).
24;*
25;* Please observe the difference in using the bit names with instructions
26;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"
27;* (skip if bit in register set/cleared). The following example illustrates
28;* this:
29;*
30;* in    r16,PORTB             ;read PORTB latch
31;* sbr   r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)
32;* out   PORTB,r16             ;output to PORTB
33;*
34;* in    r16,TIFR              ;read the Timer Interrupt Flag Register
35;* sbrc  r16,TOV0              ;test the overflow flag (use bit#)
36;* rjmp  TOV0_is_set           ;jump if set
37;* ...                         ;otherwise do something else
38;*************************************************************************
39
40#ifndef _TN22DEF_INC_
41#define _TN22DEF_INC_
42
43
44#pragma partinc 0
45
46; ***** SPECIFY DEVICE ***************************************************
47.device ATtiny22
48#pragma AVRPART ADMIN PART_NAME ATtiny22
49.equ	SIGNATURE_000	= 0x1e
50.equ	SIGNATURE_001	= 0x91
51.equ	SIGNATURE_002	= 0x06
52
53#pragma AVRPART CORE CORE_VERSION V1
54
55
56; ***** I/O REGISTER DEFINITIONS *****************************************
57; NOTE:
58; Definitions marked "MEMORY MAPPED"are extended I/O ports
59; and cannot be used with IN/OUT instructions
60.equ	SREG	= 0x3f
61.equ	SPL	= 0x3d
62.equ	GIMSK	= 0x3b
63.equ	GIFR	= 0x3a
64.equ	TIMSK	= 0x39
65.equ	TIFR	= 0x38
66.equ	MCUCR	= 0x35
67.equ	MCUSR	= 0x34
68.equ	TCCR0	= 0x33
69.equ	TCNT0	= 0x32
70.equ	WDTCR	= 0x21
71.equ	EEAR	= 0x1e
72.equ	EEDR	= 0x1d
73.equ	EECR	= 0x1c
74.equ	PORTB	= 0x18
75.equ	DDRB	= 0x17
76.equ	PINB	= 0x16
77
78
79; ***** BIT DEFINITIONS **************************************************
80
81; ***** CPU **************************
82; SREG - Status Register
83.equ	SREG_C	= 0	; Carry Flag
84.equ	SREG_Z	= 1	; Zero Flag
85.equ	SREG_N	= 2	; Negative Flag
86.equ	SREG_V	= 3	; Two's Complement Overflow Flag
87.equ	SREG_S	= 4	; Sign Bit
88.equ	SREG_H	= 5	; Half Carry Flag
89.equ	SREG_T	= 6	; Bit Copy Storage
90.equ	SREG_I	= 7	; Global Interrupt Enable
91
92; SPL - Stack Pointer Low
93.equ	SP0	= 0	; Stack pointer bit 0
94.equ	SP1	= 1	; Stack pointer bit 1
95.equ	SP2	= 2	; Stack pointer bit 2
96.equ	SP3	= 3	; Stack pointer bit 3
97.equ	SP4	= 4
98.equ	SP5	= 5	; Stack pointer bit 5
99.equ	SP6	= 6	; Stack pointer bit 6
100.equ	SP7	= 7	; Stack pointer bit 7
101
102; MCUCR - MCU Control Register
103.equ	ISC00	= 0	; Interrupt Sense Control 0 bit 0
104.equ	ISC01	= 1	; Interrupt Sense Control 0 bit 1
105.equ	SM	= 4	; Sleep Mode
106.equ	SE	= 5	; Sleep Enable
107
108; MCUSR - MCU Status register
109.equ	PORF	= 0	; Power-On Reset Flag
110.equ	EXTRF	= 1	; External Reset Flag
111
112
113; ***** TIMER_COUNTER_0 **************
114; TIMSK - Timer/Counter Interrupt Mask Register
115.equ	TOIE0	= 1	; Timer/Counter0 Overflow Interrupt Enable
116
117; TIFR - Timer/Counter Interrupt Flag register
118.equ	TOV0	= 1	; Timer/Counter0 Overflow Flag
119
120; TCCR0 - Timer/Counter0 Control Register
121.equ	CS00	= 0	; Clock Select0 bit 0
122.equ	CS01	= 1	; Clock Select0 bit 1
123.equ	CS02	= 2	; Clock Select0 bit 2
124
125; TCNT0 - Timer Counter 0
126.equ	TCNT00	= 0	; Timer Counter 0 bit 0
127.equ	TCNT01	= 1	; Timer Counter 0 bit 1
128.equ	TCNT02	= 2	; Timer Counter 0 bit 2
129.equ	TCNT03	= 3	; Timer Counter 0 bit 3
130.equ	TCNT04	= 4	; Timer Counter 0 bit 4
131.equ	TCNT05	= 5	; Timer Counter 0 bit 5
132.equ	TCNT06	= 6	; Timer Counter 0 bit 6
133.equ	TCNT07	= 7	; Timer Counter 0 bit 7
134
135
136; ***** EEPROM ***********************
137; EEAR - EEPROM Read/Write Access
138.equ	EEAR0	= 0	; EEPROM Read/Write Access bit 0
139.equ	EEAR1	= 1	; EEPROM Read/Write Access bit 1
140.equ	EEAR2	= 2	; EEPROM Read/Write Access bit 2
141.equ	EEAR3	= 3	; EEPROM Read/Write Access bit 3
142.equ	EEAR4	= 4	; EEPROM Read/Write Access bit 4
143.equ	EEAR5	= 5	; EEPROM Read/Write Access bit 5
144.equ	EEAR6	= 6	; EEPROM Read/Write Access bit 6
145.equ	EEAR7	= 7	; EEPROM Read/Write Access bit 7
146
147; EEDR - EEPROM Data Register
148.equ	EEDR0	= 0	; EEPROM Data Register bit 0
149.equ	EEDR1	= 1	; EEPROM Data Register bit 1
150.equ	EEDR2	= 2	; EEPROM Data Register bit 2
151.equ	EEDR3	= 3	; EEPROM Data Register bit 3
152.equ	EEDR4	= 4	; EEPROM Data Register bit 4
153.equ	EEDR5	= 5	; EEPROM Data Register bit 5
154.equ	EEDR6	= 6	; EEPROM Data Register bit 6
155.equ	EEDR7	= 7	; EEPROM Data Register bit 7
156
157; EECR - EEPROM Control Register
158.equ	EERE	= 0	; EEPROM Read Enable
159.equ	EEWE	= 1	; EEPROM Write Enable
160.equ	EEMWE	= 2	; EEPROM Master Write Enable
161
162
163; ***** WATCHDOG *********************
164; WDTCR - Watchdog Timer Control Register
165.equ	WDP0	= 0	; Watch Dog Timer Prescaler bit 0
166.equ	WDP1	= 1	; Watch Dog Timer Prescaler bit 1
167.equ	WDP2	= 2	; Watch Dog Timer Prescaler bit 2
168.equ	WDE	= 3	; Watch Dog Enable
169.equ	WDTOE	= 4	; RW
170.equ	WDDE	= WDTOE	; For compatibility
171
172
173; ***** PORTB ************************
174; PORTB - Data Register, Port B
175.equ	PORTB0	= 0	;
176.equ	PB0	= 0	; For compatibility
177.equ	PORTB1	= 1	;
178.equ	PB1	= 1	; For compatibility
179.equ	PORTB2	= 2	;
180.equ	PB2	= 2	; For compatibility
181.equ	PORTB3	= 3	;
182.equ	PB3	= 3	; For compatibility
183.equ	PORTB4	= 4	;
184.equ	PB4	= 4	; For compatibility
185
186; DDRB - Data Direction Register, Port B
187.equ	DDB0	= 0	;
188.equ	DDB1	= 1	;
189.equ	DDB2	= 2	;
190.equ	DDB3	= 3	;
191.equ	DDB4	= 4	;
192
193; PINB - Input Pins, Port B
194.equ	PINB0	= 0	;
195.equ	PINB1	= 1	;
196.equ	PINB2	= 2	;
197.equ	PINB3	= 3	;
198.equ	PINB4	= 4	;
199
200
201
202; ***** LOCKSBITS ********************************************************
203.equ	LB1	= 0	; Lockbit
204.equ	LB2	= 1	; Lockbit
205
206
207; ***** FUSES ************************************************************
208; LOW fuse bits
209
210
211
212; ***** CPU REGISTER DEFINITIONS *****************************************
213.def	XH	= r27
214.def	XL	= r26
215.def	YH	= r29
216.def	YL	= r28
217.def	ZH	= r31
218.def	ZL	= r30
219
220
221
222; ***** DATA MEMORY DECLARATIONS *****************************************
223.equ	FLASHEND	= 0x03ff	; Note: Word address
224.equ	IOEND	= 0x003f
225.equ	SRAM_START	= 0x0060
226.equ	SRAM_SIZE	= 128
227.equ	RAMEND	= 0x00df
228.equ	XRAMEND	= 0x0000
229.equ	E2END	= 0x007f
230.equ	EEPROMEND	= 0x007f
231.equ	EEADRBITS	= 7
232#pragma AVRPART MEMORY PROG_FLASH 2048
233#pragma AVRPART MEMORY EEPROM 128
234#pragma AVRPART MEMORY INT_SRAM SIZE 128
235#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x60
236
237
238
239
240
241; ***** INTERRUPT VECTORS ************************************************
242.equ	INT0addr	= 0x0001	; External Interrupt 0
243.equ	OVF0addr	= 0x0002	; Timer/Counter0 Overflow
244
245.equ	INT_VECTORS_SIZE	= 3	; size in words
246
247#pragma AVRPART CORE INSTRUCTIONS_NOT_SUPPORTED break
248
249#endif  /* _TN22DEF_INC_ */
250
251; ***** END OF FILE ******************************************************
252