1;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ******************** 2;***** Created: 2011-02-09 12:04 ******* Source: ATtiny25.xml ************ 3;************************************************************************* 4;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y 5;* 6;* Number : AVR000 7;* File Name : "tn25def.inc" 8;* Title : Register/Bit Definitions for the ATtiny25 9;* Date : 2011-02-09 10;* Version : 2.35 11;* Support E-mail : avr@atmel.com 12;* Target MCU : ATtiny25 13;* 14;* DESCRIPTION 15;* When including this file in the assembly program file, all I/O register 16;* names and I/O register bit names appearing in the data book can be used. 17;* In addition, the six registers forming the three data pointers X, Y and 18;* Z have been assigned names XL - ZH. Highest RAM address for Internal 19;* SRAM is also defined 20;* 21;* The Register names are represented by their hexadecimal address. 22;* 23;* The Register Bit names are represented by their bit number (0-7). 24;* 25;* Please observe the difference in using the bit names with instructions 26;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" 27;* (skip if bit in register set/cleared). The following example illustrates 28;* this: 29;* 30;* in r16,PORTB ;read PORTB latch 31;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#) 32;* out PORTB,r16 ;output to PORTB 33;* 34;* in r16,TIFR ;read the Timer Interrupt Flag Register 35;* sbrc r16,TOV0 ;test the overflow flag (use bit#) 36;* rjmp TOV0_is_set ;jump if set 37;* ... ;otherwise do something else 38;************************************************************************* 39 40#ifndef _TN25DEF_INC_ 41#define _TN25DEF_INC_ 42 43 44#pragma partinc 0 45 46; ***** SPECIFY DEVICE *************************************************** 47.device ATtiny25 48#pragma AVRPART ADMIN PART_NAME ATtiny25 49.equ SIGNATURE_000 = 0x1e 50.equ SIGNATURE_001 = 0x91 51.equ SIGNATURE_002 = 0x08 52 53#pragma AVRPART CORE CORE_VERSION V2 54#pragma AVRPART CORE NEW_INSTRUCTIONS lpm rd,z+ 55 56 57; ***** I/O REGISTER DEFINITIONS ***************************************** 58; NOTE: 59; Definitions marked "MEMORY MAPPED"are extended I/O ports 60; and cannot be used with IN/OUT instructions 61.equ SREG = 0x3f 62.equ SPL = 0x3d 63.equ GIMSK = 0x3b 64.equ GIFR = 0x3a 65.equ TIMSK = 0x39 66.equ TIFR = 0x38 67.equ SPMCSR = 0x37 68.equ MCUCR = 0x35 69.equ MCUSR = 0x34 70.equ TCCR0B = 0x33 71.equ TCNT0 = 0x32 72.equ OSCCAL = 0x31 73.equ TCCR1 = 0x30 74.equ TCNT1 = 0x2f 75.equ OCR1A = 0x2e 76.equ OCR1C = 0x2d 77.equ GTCCR = 0x2c 78.equ OCR1B = 0x2b 79.equ TCCR0A = 0x2a 80.equ OCR0A = 0x29 81.equ OCR0B = 0x28 82.equ PLLCSR = 0x27 83.equ CLKPR = 0x26 84.equ DT1A = 0x25 85.equ DT1B = 0x24 86.equ DTPS = 0x23 87.equ DWDR = 0x22 88.equ WDTCR = 0x21 89.equ PRR = 0x20 90.equ EEARH = 0x1f 91.equ EEARL = 0x1e 92.equ EEDR = 0x1d 93.equ EECR = 0x1c 94.equ PORTB = 0x18 95.equ DDRB = 0x17 96.equ PINB = 0x16 97.equ PCMSK = 0x15 98.equ DIDR0 = 0x14 99.equ GPIOR2 = 0x13 100.equ GPIOR1 = 0x12 101.equ GPIOR0 = 0x11 102.equ USIBR = 0x10 103.equ USIDR = 0x0f 104.equ USISR = 0x0e 105.equ USICR = 0x0d 106.equ ACSR = 0x08 107.equ ADMUX = 0x07 108.equ ADCSRA = 0x06 109.equ ADCH = 0x05 110.equ ADCL = 0x04 111.equ ADCSRB = 0x03 112 113 114; ***** BIT DEFINITIONS ************************************************** 115 116; ***** PORTB ************************ 117; PORTB - Data Register, Port B 118.equ PORTB0 = 0 ; 119.equ PB0 = 0 ; For compatibility 120.equ PORTB1 = 1 ; 121.equ PB1 = 1 ; For compatibility 122.equ PORTB2 = 2 ; 123.equ PB2 = 2 ; For compatibility 124.equ PORTB3 = 3 ; 125.equ PB3 = 3 ; For compatibility 126.equ PORTB4 = 4 ; 127.equ PB4 = 4 ; For compatibility 128.equ PORTB5 = 5 ; 129.equ PB5 = 5 ; For compatibility 130 131; DDRB - Data Direction Register, Port B 132.equ DDB0 = 0 ; 133.equ DDB1 = 1 ; 134.equ DDB2 = 2 ; 135.equ DDB3 = 3 ; 136.equ DDB4 = 4 ; 137.equ DDB5 = 5 ; 138 139; PINB - Input Pins, Port B 140.equ PINB0 = 0 ; 141.equ PINB1 = 1 ; 142.equ PINB2 = 2 ; 143.equ PINB3 = 3 ; 144.equ PINB4 = 4 ; 145.equ PINB5 = 5 ; 146 147 148; ***** ANALOG_COMPARATOR ************ 149; ADCSRB - ADC Control and Status Register B 150.equ ACME = 6 ; Analog Comparator Multiplexer Enable 151 152; ACSR - Analog Comparator Control And Status Register 153.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0 154.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1 155.equ ACIE = 3 ; Analog Comparator Interrupt Enable 156.equ ACI = 4 ; Analog Comparator Interrupt Flag 157.equ ACO = 5 ; Analog Compare Output 158.equ ACBG = 6 ; Analog Comparator Bandgap Select 159.equ AINBG = ACBG ; For compatibility 160.equ ACD = 7 ; Analog Comparator Disable 161 162; DIDR0 - 163.equ AIN0D = 0 ; AIN0 Digital Input Disable 164.equ AIN1D = 1 ; AIN1 Digital Input Disable 165 166 167; ***** AD_CONVERTER ***************** 168; ADMUX - The ADC multiplexer Selection Register 169.equ MUX0 = 0 ; Analog Channel and Gain Selection Bits 170.equ MUX1 = 1 ; Analog Channel and Gain Selection Bits 171.equ MUX2 = 2 ; Analog Channel and Gain Selection Bits 172.equ MUX3 = 3 ; Analog Channel and Gain Selection Bits 173.equ REFS2 = 4 ; Reference Selection Bit 2 174.equ ADLAR = 5 ; Left Adjust Result 175.equ REFS0 = 6 ; Reference Selection Bit 0 176.equ REFS1 = 7 ; Reference Selection Bit 1 177 178; ADCSRA - The ADC Control and Status register 179.equ ADPS0 = 0 ; ADC Prescaler Select Bits 180.equ ADPS1 = 1 ; ADC Prescaler Select Bits 181.equ ADPS2 = 2 ; ADC Prescaler Select Bits 182.equ ADIE = 3 ; ADC Interrupt Enable 183.equ ADIF = 4 ; ADC Interrupt Flag 184.equ ADATE = 5 ; ADC Auto Trigger Enable 185.equ ADSC = 6 ; ADC Start Conversion 186.equ ADEN = 7 ; ADC Enable 187 188; ADCH - ADC Data Register High Byte 189.equ ADCH0 = 0 ; ADC Data Register High Byte Bit 0 190.equ ADCH1 = 1 ; ADC Data Register High Byte Bit 1 191.equ ADCH2 = 2 ; ADC Data Register High Byte Bit 2 192.equ ADCH3 = 3 ; ADC Data Register High Byte Bit 3 193.equ ADCH4 = 4 ; ADC Data Register High Byte Bit 4 194.equ ADCH5 = 5 ; ADC Data Register High Byte Bit 5 195.equ ADCH6 = 6 ; ADC Data Register High Byte Bit 6 196.equ ADCH7 = 7 ; ADC Data Register High Byte Bit 7 197 198; ADCL - ADC Data Register Low Byte 199.equ ADCL0 = 0 ; ADC Data Register Low Byte Bit 0 200.equ ADCL1 = 1 ; ADC Data Register Low Byte Bit 1 201.equ ADCL2 = 2 ; ADC Data Register Low Byte Bit 2 202.equ ADCL3 = 3 ; ADC Data Register Low Byte Bit 3 203.equ ADCL4 = 4 ; ADC Data Register Low Byte Bit 4 204.equ ADCL5 = 5 ; ADC Data Register Low Byte Bit 5 205.equ ADCL6 = 6 ; ADC Data Register Low Byte Bit 6 206.equ ADCL7 = 7 ; ADC Data Register Low Byte Bit 7 207 208; ADCSRB - ADC Control and Status Register B 209.equ ADTS0 = 0 ; ADC Auto Trigger Source 0 210.equ ADTS1 = 1 ; ADC Auto Trigger Source 1 211.equ ADTS2 = 2 ; ADC Auto Trigger Source 2 212.equ IPR = 5 ; Input Polarity Mode 213.equ BIN = 7 ; Bipolar Input Mode 214 215; DIDR0 - Digital Input Disable Register 0 216.equ ADC1D = 2 ; ADC1 Digital input Disable 217.equ ADC3D = 3 ; ADC3 Digital input Disable 218.equ ADC2D = 4 ; ADC2 Digital input Disable 219.equ ADC0D = 5 ; ADC0 Digital input Disable 220 221 222; ***** USI ************************** 223; USIBR - USI Buffer Register 224.equ USIBR0 = 0 ; USI Buffer Register bit 0 225.equ USIBR1 = 1 ; USI Buffer Register bit 1 226.equ USIBR2 = 2 ; USI Buffer Register bit 2 227.equ USIBR3 = 3 ; USI Buffer Register bit 3 228.equ USIBR4 = 4 ; USI Buffer Register bit 4 229.equ USIBR5 = 5 ; USI Buffer Register bit 5 230.equ USIBR6 = 6 ; USI Buffer Register bit 6 231.equ USIBR7 = 7 ; USI Buffer Register bit 7 232 233; USIDR - USI Data Register 234.equ USIDR0 = 0 ; USI Data Register bit 0 235.equ USIDR1 = 1 ; USI Data Register bit 1 236.equ USIDR2 = 2 ; USI Data Register bit 2 237.equ USIDR3 = 3 ; USI Data Register bit 3 238.equ USIDR4 = 4 ; USI Data Register bit 4 239.equ USIDR5 = 5 ; USI Data Register bit 5 240.equ USIDR6 = 6 ; USI Data Register bit 6 241.equ USIDR7 = 7 ; USI Data Register bit 7 242 243; USISR - USI Status Register 244.equ USICNT0 = 0 ; USI Counter Value Bit 0 245.equ USICNT1 = 1 ; USI Counter Value Bit 1 246.equ USICNT2 = 2 ; USI Counter Value Bit 2 247.equ USICNT3 = 3 ; USI Counter Value Bit 3 248.equ USIDC = 4 ; Data Output Collision 249.equ USIPF = 5 ; Stop Condition Flag 250.equ USIOIF = 6 ; Counter Overflow Interrupt Flag 251.equ USISIF = 7 ; Start Condition Interrupt Flag 252 253; USICR - USI Control Register 254.equ USITC = 0 ; Toggle Clock Port Pin 255.equ USICLK = 1 ; Clock Strobe 256.equ USICS0 = 2 ; USI Clock Source Select Bit 0 257.equ USICS1 = 3 ; USI Clock Source Select Bit 1 258.equ USIWM0 = 4 ; USI Wire Mode Bit 0 259.equ USIWM1 = 5 ; USI Wire Mode Bit 1 260.equ USIOIE = 6 ; Counter Overflow Interrupt Enable 261.equ USISIE = 7 ; Start Condition Interrupt Enable 262 263 264; ***** EXTERNAL_INTERRUPT *********** 265; MCUCR - MCU Control Register 266.equ ISC00 = 0 ; Interrupt Sense Control 0 Bit 0 267.equ ISC01 = 1 ; Interrupt Sense Control 0 Bit 1 268 269; GIMSK - General Interrupt Mask Register 270.equ GICR = GIMSK ; For compatibility 271.equ PCIE = 5 ; Pin Change Interrupt Enable 272.equ INT0 = 6 ; External Interrupt Request 0 Enable 273 274; GIFR - General Interrupt Flag register 275.equ PCIF = 5 ; Pin Change Interrupt Flag 276.equ INTF0 = 6 ; External Interrupt Flag 0 277 278; PCMSK - Pin Change Enable Mask 279.equ PCINT0 = 0 ; Pin Change Enable Mask Bit 0 280.equ PCINT1 = 1 ; Pin Change Enable Mask Bit 1 281.equ PCINT2 = 2 ; Pin Change Enable Mask Bit 2 282.equ PCINT3 = 3 ; Pin Change Enable Mask Bit 3 283.equ PCINT4 = 4 ; Pin Change Enable Mask Bit 4 284.equ PCINT5 = 5 ; Pin Change Enable Mask Bit 5 285 286 287; ***** EEPROM *********************** 288; EEARL - EEPROM Address Register Low Byte 289.equ EEAR0 = 0 ; EEPROM Read/Write Access Bit 0 290.equ EEAR1 = 1 ; EEPROM Read/Write Access Bit 1 291.equ EEAR2 = 2 ; EEPROM Read/Write Access Bit 2 292.equ EEAR3 = 3 ; EEPROM Read/Write Access Bit 3 293.equ EEAR4 = 4 ; EEPROM Read/Write Access Bit 4 294.equ EEAR5 = 5 ; EEPROM Read/Write Access Bit 5 295.equ EEAR6 = 6 ; EEPROM Read/Write Access Bit 6 296.equ EEAR7 = 7 ; EEPROM Read/Write Access Bit 7 297 298; EEARH - EEPROM Address Register High Byte 299.equ EEAR8 = 0 ; EEPROM Read/Write Access Bit 0 300 301; EEDR - EEPROM Data Register 302.equ EEDR0 = 0 ; EEPROM Data Register bit 0 303.equ EEDR1 = 1 ; EEPROM Data Register bit 1 304.equ EEDR2 = 2 ; EEPROM Data Register bit 2 305.equ EEDR3 = 3 ; EEPROM Data Register bit 3 306.equ EEDR4 = 4 ; EEPROM Data Register bit 4 307.equ EEDR5 = 5 ; EEPROM Data Register bit 5 308.equ EEDR6 = 6 ; EEPROM Data Register bit 6 309.equ EEDR7 = 7 ; EEPROM Data Register bit 7 310 311; EECR - EEPROM Control Register 312.equ EERE = 0 ; EEPROM Read Enable 313.equ EEPE = 1 ; EEPROM Write Enable 314.equ EEMPE = 2 ; EEPROM Master Write Enable 315.equ EERIE = 3 ; EEPROM Ready Interrupt Enable 316.equ EEPM0 = 4 ; EEPROM Programming Mode Bit 0 317.equ EEPM1 = 5 ; EEPROM Programming Mode Bit 1 318 319 320; ***** WATCHDOG ********************* 321; WDTCR - Watchdog Timer Control Register 322.equ WDTCSR = WDTCR ; For compatibility 323.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0 324.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1 325.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2 326.equ WDE = 3 ; Watch Dog Enable 327.equ WDCE = 4 ; Watchdog Change Enable 328.equ WDTOE = WDCE ; For compatibility 329.equ WDP3 = 5 ; Watchdog Timer Prescaler Bit 3 330.equ WDIE = 6 ; Watchdog Timeout Interrupt Enable 331.equ WDIF = 7 ; Watchdog Timeout Interrupt Flag 332 333 334; ***** TIMER_COUNTER_0 ************** 335; TIMSK - Timer/Counter Interrupt Mask Register 336.equ TOIE0 = 1 ; Timer/Counter0 Overflow Interrupt Enable 337.equ OCIE0B = 3 ; Timer/Counter0 Output Compare Match B Interrupt Enable 338.equ OCIE0A = 4 ; Timer/Counter0 Output Compare Match A Interrupt Enable 339 340; TIFR - Timer/Counter0 Interrupt Flag register 341.equ TOV0 = 1 ; Timer/Counter0 Overflow Flag 342.equ OCF0B = 3 ; Timer/Counter0 Output Compare Flag 0B 343.equ OCF0A = 4 ; Timer/Counter0 Output Compare Flag 0A 344 345; TCCR0A - Timer/Counter Control Register A 346.equ WGM00 = 0 ; Waveform Generation Mode 347.equ WGM01 = 1 ; Waveform Generation Mode 348.equ COM0B0 = 4 ; Compare Output Mode, Fast PWm 349.equ COM0B1 = 5 ; Compare Output Mode, Fast PWm 350.equ COM0A0 = 6 ; Compare Output Mode, Phase Correct PWM Mode 351.equ COM0A1 = 7 ; Compare Output Mode, Phase Correct PWM Mode 352 353; TCCR0B - Timer/Counter Control Register B 354.equ CS00 = 0 ; Clock Select 355.equ CS01 = 1 ; Clock Select 356.equ CS02 = 2 ; Clock Select 357.equ WGM02 = 3 ; 358.equ FOC0B = 6 ; Force Output Compare B 359.equ FOC0A = 7 ; Force Output Compare A 360 361; TCNT0 - Timer/Counter0 362.equ TCNT0_0 = 0 ; 363.equ TCNT0_1 = 1 ; 364.equ TCNT0_2 = 2 ; 365.equ TCNT0_3 = 3 ; 366.equ TCNT0_4 = 4 ; 367.equ TCNT0_5 = 5 ; 368.equ TCNT0_6 = 6 ; 369.equ TCNT0_7 = 7 ; 370 371; OCR0A - Timer/Counter0 Output Compare Register 372.equ OCR0_0 = 0 ; 373.equ OCR0_1 = 1 ; 374.equ OCR0_2 = 2 ; 375.equ OCR0_3 = 3 ; 376.equ OCR0_4 = 4 ; 377.equ OCR0_5 = 5 ; 378.equ OCR0_6 = 6 ; 379.equ OCR0_7 = 7 ; 380 381; OCR0B - Timer/Counter0 Output Compare Register 382;.equ OCR0_0 = 0 ; 383;.equ OCR0_1 = 1 ; 384;.equ OCR0_2 = 2 ; 385;.equ OCR0_3 = 3 ; 386;.equ OCR0_4 = 4 ; 387;.equ OCR0_5 = 5 ; 388;.equ OCR0_6 = 6 ; 389;.equ OCR0_7 = 7 ; 390 391; GTCCR - General Timer/Counter Control Register 392.equ PSR0 = 0 ; Prescaler Reset Timer/Counter1 and Timer/Counter0 393.equ TSM = 7 ; Timer/Counter Synchronization Mode 394 395 396; ***** TIMER_COUNTER_1 ************** 397; TCCR1 - Timer/Counter Control Register 398.equ CS10 = 0 ; Clock Select Bits 399.equ CS11 = 1 ; Clock Select Bits 400.equ CS12 = 2 ; Clock Select Bits 401.equ CS13 = 3 ; Clock Select Bits 402.equ COM1A0 = 4 ; Compare Output Mode, Bit 1 403.equ COM1A1 = 5 ; Compare Output Mode, Bit 0 404.equ PWM1A = 6 ; Pulse Width Modulator Enable 405.equ CTC1 = 7 ; Clear Timer/Counter on Compare Match 406 407; TCNT1 - Timer/Counter Register 408.equ TCNT1_0 = 0 ; Timer/Counter Register Bit 0 409.equ TCNT1_1 = 1 ; Timer/Counter Register Bit 1 410.equ TCNT1_2 = 2 ; Timer/Counter Register Bit 2 411.equ TCNT1_3 = 3 ; Timer/Counter Register Bit 3 412.equ TCNT1_4 = 4 ; Timer/Counter Register Bit 4 413.equ TCNT1_5 = 5 ; Timer/Counter Register Bit 5 414.equ TCNT1_6 = 6 ; Timer/Counter Register Bit 6 415.equ TCNT1_7 = 7 ; Timer/Counter Register Bit 7 416 417; OCR1A - Output Compare Register 418.equ OCR1A0 = 0 ; Output Compare Register A Bit 0 419.equ OCR1A1 = 1 ; Output Compare Register A Bit 1 420.equ OCR1A2 = 2 ; Output Compare Register A Bit 2 421.equ OCR1A3 = 3 ; Output Compare Register A Bit 3 422.equ OCR1A4 = 4 ; Output Compare Register A Bit 4 423.equ OCR1A5 = 5 ; Output Compare Register A Bit 5 424.equ OCR1A6 = 6 ; Output Compare Register A Bit 6 425.equ OCR1A7 = 7 ; Output Compare Register A Bit 7 426 427; OCR1B - Output Compare Register 428.equ OCR1B0 = 0 ; Output Compare Register B Bit 0 429.equ OCR1B1 = 1 ; Output Compare Register B Bit 1 430.equ OCR1B2 = 2 ; Output Compare Register B Bit 2 431.equ OCR1B3 = 3 ; Output Compare Register B Bit 3 432.equ OCR1B4 = 4 ; Output Compare Register B Bit 4 433.equ OCR1B5 = 5 ; Output Compare Register B Bit 5 434.equ OCR1B6 = 6 ; Output Compare Register B Bit 6 435.equ OCR1B7 = 7 ; Output Compare Register B Bit 7 436 437; OCR1C - Output compare register 438.equ OCR1C0 = 0 ; 439.equ OCR1C1 = 1 ; 440.equ OCR1C2 = 2 ; 441.equ OCR1C3 = 3 ; 442.equ OCR1C4 = 4 ; 443.equ OCR1C5 = 5 ; 444.equ OCR1C6 = 6 ; 445.equ OCR1C7 = 7 ; 446 447; TIMSK - Timer/Counter Interrupt Mask Register 448.equ TOIE1 = 2 ; Timer/Counter1 Overflow Interrupt Enable 449.equ OCIE1B = 5 ; OCIE1A: Timer/Counter1 Output Compare B Interrupt Enable 450.equ OCIE1A = 6 ; OCIE1A: Timer/Counter1 Output Compare Interrupt Enable 451 452; TIFR - Timer/Counter Interrupt Flag Register 453.equ TOV1 = 2 ; Timer/Counter1 Overflow Flag 454.equ OCF1B = 5 ; Timer/Counter1 Output Compare Flag 1B 455.equ OCF1A = 6 ; Timer/Counter1 Output Compare Flag 1A 456 457; GTCCR - Timer counter control register 458.equ PSR1 = 1 ; Prescaler Reset Timer/Counter1 459.equ FOC1A = 2 ; Force Output Compare 1A 460.equ FOC1B = 3 ; Force Output Compare Match 1B 461.equ COM1B0 = 4 ; Comparator B Output Mode 462.equ COM1B1 = 5 ; Comparator B Output Mode 463.equ PWM1B = 6 ; Pulse Width Modulator B Enable 464 465; DTPS - Dead time prescaler register 466.equ DTPS0 = 0 ; 467.equ DTPS1 = 1 ; 468 469; DT1A - Dead time value register 470.equ DTVL0 = 0 ; 471.equ DTVL1 = 1 ; 472.equ DTVL2 = 2 ; 473.equ DTVL3 = 3 ; 474.equ DTVH0 = 4 ; 475.equ DTVH1 = 5 ; 476.equ DTVH2 = 6 ; 477.equ DTVH3 = 7 ; 478 479; DT1B - Dead time value B 480;.equ DTVL0 = 0 ; 481;.equ DTVL1 = 1 ; 482;.equ DTVL2 = 2 ; 483;.equ DTVL3 = 3 ; 484;.equ DTVH0 = 4 ; 485;.equ DTVH1 = 5 ; 486;.equ DTVH2 = 6 ; 487;.equ DTVH3 = 7 ; 488 489 490; ***** BOOT_LOAD ******************** 491; SPMCSR - Store Program Memory Control Register 492.equ SPMEN = 0 ; Store Program Memory Enable 493.equ PGERS = 1 ; Page Erase 494.equ PGWRT = 2 ; Page Write 495.equ RFLB = 3 ; Read fuse and lock bits 496.equ CTPB = 4 ; Clear temporary page buffer 497 498 499; ***** CPU ************************** 500; SREG - Status Register 501.equ SREG_C = 0 ; Carry Flag 502.equ SREG_Z = 1 ; Zero Flag 503.equ SREG_N = 2 ; Negative Flag 504.equ SREG_V = 3 ; Two's Complement Overflow Flag 505.equ SREG_S = 4 ; Sign Bit 506.equ SREG_H = 5 ; Half Carry Flag 507.equ SREG_T = 6 ; Bit Copy Storage 508.equ SREG_I = 7 ; Global Interrupt Enable 509 510; SPL - Stack Pointer Low Byte 511.equ SP0 = 0 ; Stack Pointer Bit 0 512.equ SP1 = 1 ; Stack Pointer Bit 1 513.equ SP2 = 2 ; Stack Pointer Bit 2 514.equ SP3 = 3 ; Stack Pointer Bit 3 515.equ SP4 = 4 ; Stack Pointer Bit 4 516.equ SP5 = 5 ; Stack Pointer Bit 5 517.equ SP6 = 6 ; Stack Pointer Bit 6 518.equ SP7 = 7 ; Stack Pointer Bit 7 519 520; MCUCR - MCU Control Register 521;.equ ISC00 = 0 ; Interrupt Sense Control 0 bit 0 522;.equ ISC01 = 1 ; Interrupt Sense Control 0 bit 1 523.equ SM0 = 3 ; Sleep Mode Select Bit 0 524.equ SM1 = 4 ; Sleep Mode Select Bit 1 525.equ SE = 5 ; Sleep Enable 526.equ PUD = 6 ; Pull-up Disable 527 528; MCUSR - MCU Status register 529.equ PORF = 0 ; Power-On Reset Flag 530.equ EXTRF = 1 ; External Reset Flag 531.equ BORF = 2 ; Brown-out Reset Flag 532.equ WDRF = 3 ; Watchdog Reset Flag 533 534; PRR - Power Reduction Register 535.equ PRADC = 0 ; Power Reduction ADC 536.equ PRUSI = 1 ; Power Reduction USI 537.equ PRTIM0 = 2 ; Power Reduction Timer/Counter0 538.equ PRTIM1 = 3 ; Power Reduction Timer/Counter1 539 540; OSCCAL - Oscillator Calibration Register 541.equ CAL0 = 0 ; Oscillatro Calibration Value Bit 0 542.equ CAL1 = 1 ; Oscillatro Calibration Value Bit 1 543.equ CAL2 = 2 ; Oscillatro Calibration Value Bit 2 544.equ CAL3 = 3 ; Oscillatro Calibration Value Bit 3 545.equ CAL4 = 4 ; Oscillatro Calibration Value Bit 4 546.equ CAL5 = 5 ; Oscillatro Calibration Value Bit 5 547.equ CAL6 = 6 ; Oscillatro Calibration Value Bit 6 548.equ CAL7 = 7 ; Oscillatro Calibration Value Bit 7 549 550; PLLCSR - PLL Control and status register 551.equ PLOCK = 0 ; PLL Lock detector 552.equ PLLE = 1 ; PLL Enable 553.equ PCKE = 2 ; PCK Enable 554.equ LSM = 7 ; Low speed mode 555 556; CLKPR - Clock Prescale Register 557.equ CLKPS0 = 0 ; Clock Prescaler Select Bit 0 558.equ CLKPS1 = 1 ; Clock Prescaler Select Bit 1 559.equ CLKPS2 = 2 ; Clock Prescaler Select Bit 2 560.equ CLKPS3 = 3 ; Clock Prescaler Select Bit 3 561.equ CLKPCE = 7 ; Clock Prescaler Change Enable 562 563; DWDR - debugWire data register 564.equ DWDR0 = 0 ; 565.equ DWDR1 = 1 ; 566.equ DWDR2 = 2 ; 567.equ DWDR3 = 3 ; 568.equ DWDR4 = 4 ; 569.equ DWDR5 = 5 ; 570.equ DWDR6 = 6 ; 571.equ DWDR7 = 7 ; 572 573; GPIOR2 - General Purpose IO register 2 574.equ GPIOR20 = 0 ; 575.equ GPIOR21 = 1 ; 576.equ GPIOR22 = 2 ; 577.equ GPIOR23 = 3 ; 578.equ GPIOR24 = 4 ; 579.equ GPIOR25 = 5 ; 580.equ GPIOR26 = 6 ; 581.equ GPIOR27 = 7 ; 582 583; GPIOR1 - General Purpose register 1 584.equ GPIOR10 = 0 ; 585.equ GPIOR11 = 1 ; 586.equ GPIOR12 = 2 ; 587.equ GPIOR13 = 3 ; 588.equ GPIOR14 = 4 ; 589.equ GPIOR15 = 5 ; 590.equ GPIOR16 = 6 ; 591.equ GPIOR17 = 7 ; 592 593; GPIOR0 - General purpose register 0 594.equ GPIOR00 = 0 ; 595.equ GPIOR01 = 1 ; 596.equ GPIOR02 = 2 ; 597.equ GPIOR03 = 3 ; 598.equ GPIOR04 = 4 ; 599.equ GPIOR05 = 5 ; 600.equ GPIOR06 = 6 ; 601.equ GPIOR07 = 7 ; 602 603 604 605; ***** LOCKSBITS ******************************************************** 606.equ LB1 = 0 ; Lockbit 607.equ LB2 = 1 ; Lockbit 608 609 610; ***** FUSES ************************************************************ 611; LOW fuse bits 612.equ CKSEL0 = 0 ; Select Clock source 613.equ CKSEL1 = 1 ; Select Clock source 614.equ CKSEL2 = 2 ; Select Clock source 615.equ CKSEL3 = 3 ; Select Clock source 616.equ SUT0 = 4 ; Select start-up time 617.equ SUT1 = 5 ; Select start-up time 618.equ CKOUT = 6 ; Clock Output Enable 619.equ CKDIV8 = 7 ; Divide clock by 8 620 621; HIGH fuse bits 622.equ BODLEVEL0 = 0 ; Brown-out Detector trigger level 623.equ BODLEVEL1 = 1 ; Brown-out Detector trigger level 624.equ BODLEVEL2 = 2 ; Brown-out Detector trigger level 625.equ EESAVE = 3 ; EEPROM memory is preserved through the Chip Erase 626.equ WDTON = 4 ; Watchdog Timer always on 627.equ SPIEN = 5 ; Enable Serial Program and Data Downloading 628.equ DWEN = 6 ; DebugWIRE Enable 629.equ RSTDISBL = 7 ; External Reset disable 630 631; EXTENDED fuse bits 632.equ SELFPRGEN = 0 ; Self-Programming Enable 633 634 635 636; ***** CPU REGISTER DEFINITIONS ***************************************** 637.def XH = r27 638.def XL = r26 639.def YH = r29 640.def YL = r28 641.def ZH = r31 642.def ZL = r30 643 644 645 646; ***** DATA MEMORY DECLARATIONS ***************************************** 647.equ FLASHEND = 0x03ff ; Note: Word address 648.equ IOEND = 0x003f 649.equ SRAM_START = 0x0060 650.equ SRAM_SIZE = 128 651.equ RAMEND = 0x00df 652.equ XRAMEND = 0x0000 653.equ E2END = 0x007f 654.equ EEPROMEND = 0x007f 655.equ EEADRBITS = 7 656#pragma AVRPART MEMORY PROG_FLASH 2048 657#pragma AVRPART MEMORY EEPROM 128 658#pragma AVRPART MEMORY INT_SRAM SIZE 128 659#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x60 660 661 662 663; ***** BOOTLOADER DECLARATIONS ****************************************** 664.equ NRWW_START_ADDR = 0x0 665.equ NRWW_STOP_ADDR = 0x3ff 666.equ RWW_START_ADDR = 0x0 667.equ RWW_STOP_ADDR = 0x0 668.equ PAGESIZE = 16 669 670 671 672; ***** INTERRUPT VECTORS ************************************************ 673.equ INT0addr = 0x0001 ; External Interrupt 0 674.equ PCI0addr = 0x0002 ; Pin change Interrupt Request 0 675.equ OC1Aaddr = 0x0003 ; Timer/Counter1 Compare Match 1A 676.equ OVF1addr = 0x0004 ; Timer/Counter1 Overflow 677.equ OVF0addr = 0x0005 ; Timer/Counter0 Overflow 678.equ ERDYaddr = 0x0006 ; EEPROM Ready 679.equ ACIaddr = 0x0007 ; Analog comparator 680.equ ADCCaddr = 0x0008 ; ADC Conversion ready 681.equ OC1Baddr = 0x0009 ; Timer/Counter1 Compare Match B 682.equ OC0Aaddr = 0x000a ; Timer/Counter0 Compare Match A 683.equ OC0Baddr = 0x000b ; Timer/Counter0 Compare Match B 684.equ WDTaddr = 0x000c ; Watchdog Time-out 685.equ USI_STARTaddr = 0x000d ; USI START 686.equ USI_OVFaddr = 0x000e ; USI Overflow 687 688.equ INT_VECTORS_SIZE = 15 ; size in words 689 690#endif /* _TN25DEF_INC_ */ 691 692; ***** END OF FILE ****************************************************** 693