1;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ******************** 2;***** Created: 2011-02-09 12:04 ******* Source: ATtiny4313.xml ********** 3;************************************************************************* 4;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y 5;* 6;* Number : AVR000 7;* File Name : "tn4313def.inc" 8;* Title : Register/Bit Definitions for the ATtiny4313 9;* Date : 2011-02-09 10;* Version : 2.35 11;* Support E-mail : avr@atmel.com 12;* Target MCU : ATtiny4313 13;* 14;* DESCRIPTION 15;* When including this file in the assembly program file, all I/O register 16;* names and I/O register bit names appearing in the data book can be used. 17;* In addition, the six registers forming the three data pointers X, Y and 18;* Z have been assigned names XL - ZH. Highest RAM address for Internal 19;* SRAM is also defined 20;* 21;* The Register names are represented by their hexadecimal address. 22;* 23;* The Register Bit names are represented by their bit number (0-7). 24;* 25;* Please observe the difference in using the bit names with instructions 26;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" 27;* (skip if bit in register set/cleared). The following example illustrates 28;* this: 29;* 30;* in r16,PORTB ;read PORTB latch 31;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#) 32;* out PORTB,r16 ;output to PORTB 33;* 34;* in r16,TIFR ;read the Timer Interrupt Flag Register 35;* sbrc r16,TOV0 ;test the overflow flag (use bit#) 36;* rjmp TOV0_is_set ;jump if set 37;* ... ;otherwise do something else 38;************************************************************************* 39 40#ifndef _TN4313DEF_INC_ 41#define _TN4313DEF_INC_ 42 43 44#pragma partinc 0 45 46; ***** SPECIFY DEVICE *************************************************** 47.device ATtiny4313 48#pragma AVRPART ADMIN PART_NAME ATtiny4313 49.equ SIGNATURE_000 = 0x1e 50.equ SIGNATURE_001 = 0x92 51.equ SIGNATURE_002 = 0x0d 52 53#pragma AVRPART CORE CORE_VERSION V2 54#pragma AVRPART CORE NEW_INSTRUCTIONS lpm rd,z+ 55 56 57; ***** I/O REGISTER DEFINITIONS ***************************************** 58; NOTE: 59; Definitions marked "MEMORY MAPPED"are extended I/O ports 60; and cannot be used with IN/OUT instructions 61.equ SREG = 0x3f 62.equ SPL = 0x3d 63.equ SPH = 0x3e 64.equ OCR0B = 0x3c 65.equ GIMSK = 0x3b 66.equ EIFR = 0x3a 67.equ TIMSK = 0x39 68.equ TIFR = 0x38 69.equ SPMCSR = 0x37 70.equ OCR0A = 0x36 71.equ MCUCR = 0x35 72.equ MCUSR = 0x34 73.equ TCCR0B = 0x33 74.equ TCNT0 = 0x32 75.equ OSCCAL = 0x31 76.equ TCCR0A = 0x30 77.equ TCCR1A = 0x2f 78.equ TCCR1B = 0x2e 79.equ TCNT1L = 0x2c 80.equ TCNT1H = 0x2d 81.equ OCR1AL = 0x2a 82.equ OCR1AH = 0x2b 83.equ OCR1BL = 0x28 84.equ OCR1BH = 0x29 85.equ CLKPR = 0x26 86.equ ICR1L = 0x24 87.equ ICR1H = 0x25 88.equ GTCCR = 0x23 89.equ TCCR1C = 0x22 90.equ WDTCR = 0x21 91.equ PCMSK = 0x20 92.equ EEAR = 0x1e 93.equ EEDR = 0x1d 94.equ EECR = 0x1c 95.equ PORTA = 0x1b 96.equ DDRA = 0x1a 97.equ PINA = 0x19 98.equ PORTB = 0x18 99.equ DDRB = 0x17 100.equ PINB = 0x16 101.equ GPIOR2 = 0x15 102.equ GPIOR1 = 0x14 103.equ GPIOR0 = 0x13 104.equ PORTD = 0x12 105.equ DDRD = 0x11 106.equ PIND = 0x10 107.equ USIDR = 0x0f 108.equ USISR = 0x0e 109.equ USICR = 0x0d 110.equ UDR = 0x0c 111.equ UCSRA = 0x0b 112.equ UCSRB = 0x0a 113.equ UBRRL = 0x09 114.equ ACSR = 0x08 115.equ BODCR = 0x07 116.equ PRR = 0x06 117.equ PCMSK2 = 0x05 118.equ PCMSK1 = 0x04 119.equ UCSRC = 0x03 120.equ UBRRH = 0x02 121.equ DIDR = 0x01 122 123 124; ***** BIT DEFINITIONS ************************************************** 125 126; ***** PORTB ************************ 127; PORTB - Port B Data Register 128.equ PORTB0 = 0 ; Port B Data Register bit 0 129.equ PB0 = 0 ; For compatibility 130.equ PORTB1 = 1 ; Port B Data Register bit 1 131.equ PB1 = 1 ; For compatibility 132.equ PORTB2 = 2 ; Port B Data Register bit 2 133.equ PB2 = 2 ; For compatibility 134.equ PORTB3 = 3 ; Port B Data Register bit 3 135.equ PB3 = 3 ; For compatibility 136.equ PORTB4 = 4 ; Port B Data Register bit 4 137.equ PB4 = 4 ; For compatibility 138.equ PORTB5 = 5 ; Port B Data Register bit 5 139.equ PB5 = 5 ; For compatibility 140.equ PORTB6 = 6 ; Port B Data Register bit 6 141.equ PB6 = 6 ; For compatibility 142.equ PORTB7 = 7 ; Port B Data Register bit 7 143.equ PB7 = 7 ; For compatibility 144 145; DDRB - Port B Data Direction Register 146.equ DDB0 = 0 ; Port B Data Direction Register bit 0 147.equ DDB1 = 1 ; Port B Data Direction Register bit 1 148.equ DDB2 = 2 ; Port B Data Direction Register bit 2 149.equ DDB3 = 3 ; Port B Data Direction Register bit 3 150.equ DDB4 = 4 ; Port B Data Direction Register bit 4 151.equ DDB5 = 5 ; Port B Data Direction Register bit 5 152.equ DDB6 = 6 ; Port B Data Direction Register bit 6 153.equ DDB7 = 7 ; Port B Data Direction Register bit 7 154 155; PINB - Port B Input Pins 156.equ PINB0 = 0 ; Port B Input Pins bit 0 157.equ PINB1 = 1 ; Port B Input Pins bit 1 158.equ PINB2 = 2 ; Port B Input Pins bit 2 159.equ PINB3 = 3 ; Port B Input Pins bit 3 160.equ PINB4 = 4 ; Port B Input Pins bit 4 161.equ PINB5 = 5 ; Port B Input Pins bit 5 162.equ PINB6 = 6 ; Port B Input Pins bit 6 163.equ PINB7 = 7 ; Port B Input Pins bit 7 164 165 166; ***** TIMER_COUNTER_0 ************** 167; TIMSK - Timer/Counter Interrupt Mask Register 168.equ OCIE0A = 0 ; Timer/Counter0 Output Compare Match A Interrupt Enable 169.equ TOIE0 = 1 ; Timer/Counter0 Overflow Interrupt Enable 170.equ OCIE0B = 2 ; Timer/Counter0 Output Compare Match B Interrupt Enable 171 172; TIFR - Timer/Counter Interrupt Flag register 173.equ OCF0A = 0 ; Timer/Counter0 Output Compare Flag 0A 174.equ TOV0 = 1 ; Timer/Counter0 Overflow Flag 175.equ OCF0B = 2 ; Timer/Counter0 Output Compare Flag 0B 176 177; OCR0B - Timer/Counter0 Output Compare Register 178.equ OCR0_0 = 0 ; 179.equ OCR0_1 = 1 ; 180.equ OCR0_2 = 2 ; 181.equ OCR0_3 = 3 ; 182.equ OCR0_4 = 4 ; 183.equ OCR0_5 = 5 ; 184.equ OCR0_6 = 6 ; 185.equ OCR0_7 = 7 ; 186 187; OCR0A - Timer/Counter0 Output Compare Register 188.equ OCR0A_0 = 0 ; 189.equ OCR0A_1 = 1 ; 190.equ OCR0A_2 = 2 ; 191.equ OCR0A_3 = 3 ; 192.equ OCR0A_4 = 4 ; 193.equ OCR0A_5 = 5 ; 194.equ OCR0A_6 = 6 ; 195.equ OCR0A_7 = 7 ; 196 197; TCCR0A - Timer/Counter Control Register A 198.equ WGM00 = 0 ; Waveform Generation Mode 199.equ WGM01 = 1 ; Waveform Generation Mode 200.equ COM0B0 = 4 ; Compare Match Output B Mode 201.equ COM0B1 = 5 ; Compare Match Output B Mode 202.equ COM0A0 = 6 ; Compare Match Output A Mode 203.equ COM0A1 = 7 ; Compare Match Output A Mode 204 205; TCNT0 - Timer/Counter0 206.equ TCNT0_0 = 0 ; 207.equ TCNT0_1 = 1 ; 208.equ TCNT0_2 = 2 ; 209.equ TCNT0_3 = 3 ; 210.equ TCNT0_4 = 4 ; 211.equ TCNT0_5 = 5 ; 212.equ TCNT0_6 = 6 ; 213.equ TCNT0_7 = 7 ; 214 215; TCCR0B - Timer/Counter Control Register B 216.equ TCCR0 = TCCR0B ; For compatibility 217.equ CS00 = 0 ; Clock Select 218.equ CS01 = 1 ; Clock Select 219.equ CS02 = 2 ; Clock Select 220.equ WGM02 = 3 ; 221.equ FOC0B = 6 ; Force Output Compare B 222.equ FOC0A = 7 ; Force Output Compare B 223 224 225; ***** TIMER_COUNTER_1 ************** 226; TIMSK - Timer/Counter Interrupt Mask Register 227.equ ICIE1 = 3 ; Timer/Counter1 Input Capture Interrupt Enable 228.equ TICIE = ICIE1 ; For compatibility 229.equ OCIE1B = 5 ; Timer/Counter1 Output CompareB Match Interrupt Enable 230.equ OCIE1A = 6 ; Timer/Counter1 Output CompareA Match Interrupt Enable 231.equ TOIE1 = 7 ; Timer/Counter1 Overflow Interrupt Enable 232 233; TIFR - Timer/Counter Interrupt Flag register 234.equ ICF1 = 3 ; Input Capture Flag 1 235.equ OCF1B = 5 ; Output Compare Flag 1B 236.equ OCF1A = 6 ; Output Compare Flag 1A 237.equ TOV1 = 7 ; Timer/Counter1 Overflow Flag 238 239; TCCR1A - Timer/Counter1 Control Register A 240.equ WGM10 = 0 ; Pulse Width Modulator Select Bit 0 241.equ PWM10 = WGM10 ; For compatibility 242.equ WGM11 = 1 ; Pulse Width Modulator Select Bit 1 243.equ PWM11 = WGM11 ; For compatibility 244.equ COM1B0 = 4 ; Comparet Ouput Mode 1B, bit 0 245.equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1 246.equ COM1A0 = 6 ; Comparet Ouput Mode 1A, bit 0 247.equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1 248 249; TCCR1B - Timer/Counter1 Control Register B 250.equ CS10 = 0 ; Clock Select bit 0 251.equ CS11 = 1 ; Clock Select 1 bit 1 252.equ CS12 = 2 ; Clock Select1 bit 2 253.equ WGM12 = 3 ; Waveform Generation Mode Bit 2 254.equ CTC1 = WGM12 ; For compatibility 255.equ WGM13 = 4 ; Waveform Generation Mode Bit 3 256.equ ICES1 = 6 ; Input Capture 1 Edge Select 257.equ ICNC1 = 7 ; Input Capture 1 Noise Canceler 258 259; TCCR1C - Timer/Counter1 Control Register C 260.equ FOC1B = 6 ; Force Output Compare for Channel B 261.equ FOC1A = 7 ; Force Output Compare for Channel A 262 263 264; ***** WATCHDOG ********************* 265; WDTCR - Watchdog Timer Control Register 266.equ WDTCSR = WDTCR ; For compatibility 267.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0 268.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1 269.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2 270.equ WDE = 3 ; Watch Dog Enable 271.equ WDCE = 4 ; Watchdog Change Enable 272.equ WDTOE = WDCE ; For compatibility 273.equ WDP3 = 5 ; Watchdog Timer Prescaler Bit 3 274.equ WDIE = 6 ; Watchdog Timeout Interrupt Enable 275.equ WDIF = 7 ; Watchdog Timeout Interrupt Flag 276 277 278; ***** USART ************************ 279; UDR - USART I/O Data Register 280.equ UDR0 = 0 ; USART I/O Data Register bit 0 281.equ UDR1 = 1 ; USART I/O Data Register bit 1 282.equ UDR2 = 2 ; USART I/O Data Register bit 2 283.equ UDR3 = 3 ; USART I/O Data Register bit 3 284.equ UDR4 = 4 ; USART I/O Data Register bit 4 285.equ UDR5 = 5 ; USART I/O Data Register bit 5 286.equ UDR6 = 6 ; USART I/O Data Register bit 6 287.equ UDR7 = 7 ; USART I/O Data Register bit 7 288 289; UCSRA - USART Control and Status Register A 290.equ USR = UCSRA ; For compatibility 291.equ MPCM = 0 ; Multi-processor Communication Mode 292.equ U2X = 1 ; Double the USART Transmission Speed 293.equ UPE = 2 ; USART Parity Error 294.equ PE = UPE ; For compatibility 295.equ DOR = 3 ; Data overRun 296.equ FE = 4 ; Framing Error 297.equ UDRE = 5 ; USART Data Register Empty 298.equ TXC = 6 ; USART Transmitt Complete 299.equ RXC = 7 ; USART Receive Complete 300 301; UCSRB - USART Control and Status Register B 302.equ UCR = UCSRB ; For compatibility 303.equ TXB8 = 0 ; Transmit Data Bit 8 304.equ RXB8 = 1 ; Receive Data Bit 8 305.equ UCSZ2 = 2 ; Character Size 306.equ CHR9 = UCSZ2 ; For compatibility 307.equ TXEN = 3 ; Transmitter Enable 308.equ RXEN = 4 ; Receiver Enable 309.equ UDRIE = 5 ; USART Data register Empty Interrupt Enable 310.equ TXCIE = 6 ; TX Complete Interrupt Enable 311.equ RXCIE = 7 ; RX Complete Interrupt Enable 312 313; UCSRC - USART Control and Status Register C 314.equ UCPOL = 0 ; Clock Polarity 315.equ UCSZ0 = 1 ; Character Size Bit 0 316.equ UCSZ1 = 2 ; Character Size Bit 1 317.equ USBS = 3 ; Stop Bit Select 318.equ UPM0 = 4 ; Parity Mode Bit 0 319.equ UPM1 = 5 ; Parity Mode Bit 1 320.equ UMSEL = 6 ; USART Mode Select 321 322.equ UBRR = UBRRL ; For compatibility 323 324; ***** ANALOG_COMPARATOR ************ 325; ACSR - Analog Comparator Control And Status Register 326.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0 327.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1 328.equ ACIC = 2 ; 329.equ ACIE = 3 ; Analog Comparator Interrupt Enable 330.equ ACI = 4 ; Analog Comparator Interrupt Flag 331.equ ACO = 5 ; Analog Compare Output 332.equ ACBG = 6 ; Analog Comparator Bandgap Select 333.equ ACD = 7 ; Analog Comparator Disable 334 335; DIDR - Digital Input Disable Register 1 336.equ AIN0D = 0 ; AIN0 Digital Input Disable 337.equ AIN1D = 1 ; AIN1 Digital Input Disable 338 339 340; ***** PORTD ************************ 341; PORTD - Data Register, Port D 342.equ PORTD0 = 0 ; 343.equ PD0 = 0 ; For compatibility 344.equ PORTD1 = 1 ; 345.equ PD1 = 1 ; For compatibility 346.equ PORTD2 = 2 ; 347.equ PD2 = 2 ; For compatibility 348.equ PORTD3 = 3 ; 349.equ PD3 = 3 ; For compatibility 350.equ PORTD4 = 4 ; 351.equ PD4 = 4 ; For compatibility 352.equ PORTD5 = 5 ; 353.equ PD5 = 5 ; For compatibility 354.equ PORTD6 = 6 ; 355.equ PD6 = 6 ; For compatibility 356 357; DDRD - Data Direction Register, Port D 358.equ DDD0 = 0 ; 359.equ DDD1 = 1 ; 360.equ DDD2 = 2 ; 361.equ DDD3 = 3 ; 362.equ DDD4 = 4 ; 363.equ DDD5 = 5 ; 364.equ DDD6 = 6 ; 365 366; PIND - Input Pins, Port D 367.equ PIND0 = 0 ; 368.equ PIND1 = 1 ; 369.equ PIND2 = 2 ; 370.equ PIND3 = 3 ; 371.equ PIND4 = 4 ; 372.equ PIND5 = 5 ; 373.equ PIND6 = 6 ; 374 375 376; ***** EEPROM *********************** 377; EEAR - EEPROM Read/Write Access 378.equ EEARL = EEAR ; For compatibility 379.equ EEAR0 = 0 ; EEPROM Read/Write Access bit 0 380.equ EEAR1 = 1 ; EEPROM Read/Write Access bit 1 381.equ EEAR2 = 2 ; EEPROM Read/Write Access bit 2 382.equ EEAR3 = 3 ; EEPROM Read/Write Access bit 3 383.equ EEAR4 = 4 ; EEPROM Read/Write Access bit 4 384.equ EEAR5 = 5 ; EEPROM Read/Write Access bit 5 385.equ EEAR6 = 6 ; EEPROM Read/Write Access bit 6 386 387; EEDR - EEPROM Data Register 388.equ EEDR0 = 0 ; EEPROM Data Register bit 0 389.equ EEDR1 = 1 ; EEPROM Data Register bit 1 390.equ EEDR2 = 2 ; EEPROM Data Register bit 2 391.equ EEDR3 = 3 ; EEPROM Data Register bit 3 392.equ EEDR4 = 4 ; EEPROM Data Register bit 4 393.equ EEDR5 = 5 ; EEPROM Data Register bit 5 394.equ EEDR6 = 6 ; EEPROM Data Register bit 6 395.equ EEDR7 = 7 ; EEPROM Data Register bit 7 396 397; EECR - EEPROM Control Register 398.equ EERE = 0 ; EEPROM Read Enable 399.equ EEPE = 1 ; EEPROM Write Enable 400.equ EEWE = EEPE ; For compatibility 401.equ EEMPE = 2 ; EEPROM Master Write Enable 402.equ EEMWE = EEMPE ; For compatibility 403.equ EERIE = 3 ; EEProm Ready Interrupt Enable 404.equ EEPM0 = 4 ; 405.equ EEPM1 = 5 ; 406 407 408; ***** PORTA ************************ 409; PORTA - Port A Data Register 410.equ PORTA0 = 0 ; Port A Data Register bit 0 411.equ PA0 = 0 ; For compatibility 412.equ PORTA1 = 1 ; Port A Data Register bit 1 413.equ PA1 = 1 ; For compatibility 414.equ PORTA2 = 2 ; Port A Data Register bit 2 415.equ PA2 = 2 ; For compatibility 416 417; DDRA - Port A Data Direction Register 418.equ DDA0 = 0 ; Data Direction Register, Port A, bit 0 419.equ DDA1 = 1 ; Data Direction Register, Port A, bit 1 420.equ DDA2 = 2 ; Data Direction Register, Port A, bit 2 421 422; PINA - Port A Input Pins 423.equ PINA0 = 0 ; Input Pins, Port A bit 0 424.equ PINA1 = 1 ; Input Pins, Port A bit 1 425.equ PINA2 = 2 ; Input Pins, Port A bit 2 426 427 428; ***** USI ************************** 429; USIDR - USI Data Register 430.equ USIDR0 = 0 ; USI Data Register bit 0 431.equ USIDR1 = 1 ; USI Data Register bit 1 432.equ USIDR2 = 2 ; USI Data Register bit 2 433.equ USIDR3 = 3 ; USI Data Register bit 3 434.equ USIDR4 = 4 ; USI Data Register bit 4 435.equ USIDR5 = 5 ; USI Data Register bit 5 436.equ USIDR6 = 6 ; USI Data Register bit 6 437.equ USIDR7 = 7 ; USI Data Register bit 7 438 439; USISR - USI Status Register 440.equ USICNT0 = 0 ; USI Counter Value Bit 0 441.equ USICNT1 = 1 ; USI Counter Value Bit 1 442.equ USICNT2 = 2 ; USI Counter Value Bit 2 443.equ USICNT3 = 3 ; USI Counter Value Bit 3 444.equ USIDC = 4 ; Data Output Collision 445.equ USIPF = 5 ; Stop Condition Flag 446.equ USIOIF = 6 ; Counter Overflow Interrupt Flag 447.equ USISIF = 7 ; Start Condition Interrupt Flag 448 449; USICR - USI Control Register 450.equ USITC = 0 ; Toggle Clock Port Pin 451.equ USICLK = 1 ; Clock Strobe 452.equ USICS0 = 2 ; USI Clock Source Select Bit 0 453.equ USICS1 = 3 ; USI Clock Source Select Bit 1 454.equ USIWM0 = 4 ; USI Wire Mode Bit 0 455.equ USIWM1 = 5 ; USI Wire Mode Bit 1 456.equ USIOIE = 6 ; Counter Overflow Interrupt Enable 457.equ USISIE = 7 ; Start Condition Interrupt Enable 458 459 460; ***** EXTERNAL_INTERRUPT *********** 461; GIMSK - General Interrupt Mask Register 462.equ PCIE = 5 ; 463.equ INT0 = 6 ; External Interrupt Request 0 Enable 464.equ INT1 = 7 ; External Interrupt Request 1 Enable 465 466; EIFR - Extended Interrupt Flag Register 467.equ GIFR = EIFR ; For compatibility 468.equ PCIF = 5 ; 469.equ INTF0 = 6 ; External Interrupt Flag 0 470.equ INTF1 = 7 ; External Interrupt Flag 1 471 472; PCMSK2 - Pin Change Interrupt Mask Register 2 473.equ PCINT11 = 0 ; Pin Change Interrupt Mask 11 474.equ PCINT12 = 1 ; Pin Change Interrupt Mask 12 475.equ PCINT13 = 2 ; Pin Change Interrupt Mask 13 476.equ PCINT14 = 3 ; Pin Change Interrupt Mask 14 477.equ PCINT15 = 4 ; Pin Change Interrupt Mask 15 478.equ PCINT16 = 5 ; Pin Change Interrupt Mask 16 479.equ PCINT17 = 6 ; Pin Change Interrupt Mask 17 480 481; PCMSK1 - Pin Change Interrupt Mask Register 1 482.equ PCINT8 = 0 ; Pin Change Interrupt Mask 8 483.equ PCINT9 = 1 ; Pin Change Interrupt Mask 9 484.equ PCINT10 = 2 ; Pin Change Interrupt Mask 10 485 486 487; ***** CPU ************************** 488; SREG - Status Register 489.equ SREG_C = 0 ; Carry Flag 490.equ SREG_Z = 1 ; Zero Flag 491.equ SREG_N = 2 ; Negative Flag 492.equ SREG_V = 3 ; Two's Complement Overflow Flag 493.equ SREG_S = 4 ; Sign Bit 494.equ SREG_H = 5 ; Half Carry Flag 495.equ SREG_T = 6 ; Bit Copy Storage 496.equ SREG_I = 7 ; Global Interrupt Enable 497 498; SPMCSR - Store Program Memory Control and Status register 499.equ SPMEN = 0 ; Store Program Memory Enable 500.equ PGERS = 1 ; Page Erase 501.equ PGWRT = 2 ; Page Write 502.equ RFLB = 3 ; Read Fuse and Lock Bits 503.equ CTPB = 4 ; Clear Temporary Page Buffer 504 505; MCUCR - MCU Control Register 506.equ ISC00 = 0 ; Interrupt Sense Control 0 bit 0 507.equ ISC01 = 1 ; Interrupt Sense Control 0 bit 1 508.equ ISC10 = 2 ; Interrupt Sense Control 1 bit 0 509.equ ISC11 = 3 ; Interrupt Sense Control 1 bit 1 510.equ SM0 = 4 ; Sleep Mode Select Bit 0 511.equ SM = SM0 ; For compatibility 512.equ SE = 5 ; Sleep Enable 513.equ SM1 = 6 ; Sleep Mode Select Bit 1 514.equ PUD = 7 ; Pull-up Disable 515 516; CLKPR - Clock Prescale Register 517.equ CLKPS0 = 0 ; Clock Prescaler Select Bit 0 518.equ CLKPS1 = 1 ; Clock Prescaler Select Bit 1 519.equ CLKPS2 = 2 ; Clock Prescaler Select Bit 2 520.equ CLKPS3 = 3 ; Clock Prescaler Select Bit 3 521.equ CLKPCE = 7 ; Clock Prescaler Change Enable 522 523; MCUSR - MCU Status register 524.equ PORF = 0 ; Power-On Reset Flag 525.equ EXTRF = 1 ; External Reset Flag 526.equ BORF = 2 ; Brown-out Reset Flag 527.equ WDRF = 3 ; Watchdog Reset Flag 528 529; OSCCAL - Oscillator Calibration Register 530.equ CAL0 = 0 ; Oscillatro Calibration Value Bit 0 531.equ CAL1 = 1 ; Oscillatro Calibration Value Bit 1 532.equ CAL2 = 2 ; Oscillatro Calibration Value Bit 2 533.equ CAL3 = 3 ; Oscillatro Calibration Value Bit 3 534.equ CAL4 = 4 ; Oscillatro Calibration Value Bit 4 535.equ CAL5 = 5 ; Oscillatro Calibration Value Bit 5 536.equ CAL6 = 6 ; Oscillatro Calibration Value Bit 6 537 538; GTCCR - General Timer Counter Control Register 539.equ SFIOR = GTCCR ; For compatibility 540.equ PSR10 = 0 ; 541 542; PCMSK - Pin-Change Mask register 543.equ PCINT0 = 0 ; Pin-Change Interrupt 0 544.equ PCINT1 = 1 ; Pin-Change Interrupt 1 545.equ PCINT2 = 2 ; Pin-Change Interrupt 2 546.equ PCINT3 = 3 ; Pin-Change Interrupt 3 547.equ PCINT4 = 4 ; Pin-Change Interrupt 4 548.equ PCINT5 = 5 ; Pin-Change Interrupt 5 549.equ PCINT6 = 6 ; Pin-Change Interrupt 6 550.equ PCINT7 = 7 ; Pin-Change Interrupt 7 551 552; GPIOR2 - General Purpose I/O Register 2 553.equ GPIOR20 = 0 ; General Purpose I/O Register 2 bit 0 554.equ GPIOR21 = 1 ; General Purpose I/O Register 2 bit 1 555.equ GPIOR22 = 2 ; General Purpose I/O Register 2 bit 2 556.equ GPIOR23 = 3 ; General Purpose I/O Register 2 bit 3 557.equ GPIOR24 = 4 ; General Purpose I/O Register 2 bit 4 558.equ GPIOR25 = 5 ; General Purpose I/O Register 2 bit 5 559.equ GPIOR26 = 6 ; General Purpose I/O Register 2 bit 6 560.equ GPIOR27 = 7 ; General Purpose I/O Register 2 bit 7 561 562; GPIOR1 - General Purpose I/O Register 1 563.equ GPIOR10 = 0 ; General Purpose I/O Register 1 bit 0 564.equ GPIOR11 = 1 ; General Purpose I/O Register 1 bit 1 565.equ GPIOR12 = 2 ; General Purpose I/O Register 1 bit 2 566.equ GPIOR13 = 3 ; General Purpose I/O Register 1 bit 3 567.equ GPIOR14 = 4 ; General Purpose I/O Register 1 bit 4 568.equ GPIOR15 = 5 ; General Purpose I/O Register 1 bit 5 569.equ GPIOR16 = 6 ; General Purpose I/O Register 1 bit 6 570.equ GPIOR17 = 7 ; General Purpose I/O Register 1 bit 7 571 572; GPIOR0 - General Purpose I/O Register 0 573.equ GPIOR00 = 0 ; General Purpose I/O Register 0 bit 0 574.equ GPIOR01 = 1 ; General Purpose I/O Register 0 bit 1 575.equ GPIOR02 = 2 ; General Purpose I/O Register 0 bit 2 576.equ GPIOR03 = 3 ; General Purpose I/O Register 0 bit 3 577.equ GPIOR04 = 4 ; General Purpose I/O Register 0 bit 4 578.equ GPIOR05 = 5 ; General Purpose I/O Register 0 bit 5 579.equ GPIOR06 = 6 ; General Purpose I/O Register 0 bit 6 580.equ GPIOR07 = 7 ; General Purpose I/O Register 0 bit 7 581 582; PRR - Power reduction register 583.equ PRUSART = 0 ; 584.equ PRUSI = 1 ; 585.equ PRTIM0 = 2 ; 586.equ PRTIM1 = 3 ; 587 588; BODCR - BOD control register 589.equ BPDSE = 0 ; 590.equ BPDS = 1 ; 591 592 593 594; ***** LOCKSBITS ******************************************************** 595.equ LB1 = 0 ; Lockbit 596.equ LB2 = 1 ; Lockbit 597 598 599; ***** FUSES ************************************************************ 600; LOW fuse bits 601.equ CKSEL0 = 0 ; Select Clock Source 602.equ CKSEL1 = 1 ; Select Clock Source 603.equ CKSEL2 = 2 ; Select Clock Source 604.equ CKSEL3 = 3 ; Select Clock Source 605.equ SUT0 = 4 ; Select start-up time 606.equ SUT1 = 5 ; Select start-up time 607.equ CKOUT = 6 ; Clock output 608.equ CKDIV8 = 7 ; Divide clock by 8 609 610; HIGH fuse bits 611.equ BODLEVEL0 = 0 ; Brown-out Detector trigger level 612.equ BODLEVEL1 = 1 ; Brown-out Detector trigger level 613.equ BODLEVEL2 = 2 ; Brown-out Detector trigger level 614.equ EESAVE = 3 ; EEPROM memory is preserved through chip erase 615.equ WDTON = 4 ; Watchdog Timer Always On 616.equ SPIEN = 5 ; Enable Serial programming and Data Downloading 617.equ DWEN = 6 ; debugWIRE Enable 618.equ RSTDISBL = 7 ; External reset disable 619 620; EXTENDED fuse bits 621.equ SELFPRGEN = 0 ; Self Programming Enable 622 623 624 625; ***** CPU REGISTER DEFINITIONS ***************************************** 626.def XH = r27 627.def XL = r26 628.def YH = r29 629.def YL = r28 630.def ZH = r31 631.def ZL = r30 632 633 634 635; ***** DATA MEMORY DECLARATIONS ***************************************** 636.equ FLASHEND = 0x07ff ; Note: Word address 637.equ IOEND = 0x003f 638.equ SRAM_START = 0x0060 639.equ SRAM_SIZE = 256 640.equ RAMEND = 0x015f 641.equ XRAMEND = 0x0000 642.equ E2END = 0x00ff 643.equ EEPROMEND = 0x00ff 644.equ EEADRBITS = 8 645#pragma AVRPART MEMORY PROG_FLASH 4096 646#pragma AVRPART MEMORY EEPROM 256 647#pragma AVRPART MEMORY INT_SRAM SIZE 256 648#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x60 649 650 651 652; ***** BOOTLOADER DECLARATIONS ****************************************** 653.equ NRWW_START_ADDR = 0x0 654.equ NRWW_STOP_ADDR = 0x3ff 655.equ RWW_START_ADDR = 0x0 656.equ RWW_STOP_ADDR = 0x0 657.equ PAGESIZE = 32 658 659 660 661; ***** INTERRUPT VECTORS ************************************************ 662.equ INT0addr = 0x0001 ; External Interrupt Request 0 663.equ INT1addr = 0x0002 ; External Interrupt Request 1 664.equ ICP1addr = 0x0003 ; Timer/Counter1 Capture Event 665.equ OC1Aaddr = 0x0004 ; Timer/Counter1 Compare Match A 666.equ OC1addr = 0x0004 ; For compatibility 667.equ OVF1addr = 0x0005 ; Timer/Counter1 Overflow 668.equ OVF0addr = 0x0006 ; Timer/Counter0 Overflow 669.equ URXCaddr = 0x0007 ; USART, Rx Complete 670.equ URXC0addr = 0x0007 ; For compatibility 671.equ UDREaddr = 0x0008 ; USART Data Register Empty 672.equ UDRE0addr = 0x0008 ; For compatibility 673.equ UTXCaddr = 0x0009 ; USART, Tx Complete 674.equ UTXC0addr = 0x0009 ; For compatibility 675.equ ACIaddr = 0x000a ; Analog Comparator 676.equ PCIBaddr = 0x000b ; Pin Change Interrupt Request B 677.equ PCIaddr = 0x000b ; For compatibility 678.equ OC1Baddr = 0x000c ; 679.equ OC0Aaddr = 0x000d ; 680.equ OC0Baddr = 0x000e ; 681.equ USI_STARTaddr = 0x000f ; USI Start Condition 682.equ USI_OVFaddr = 0x0010 ; USI Overflow 683.equ ERDYaddr = 0x0011 ; 684.equ WDTaddr = 0x0012 ; Watchdog Timer Overflow 685.equ PCIAaddr = 0x0013 ; Pin Change Interrupt Request A 686.equ PCIDaddr = 0x0014 ; Pin Change Interrupt Request D 687 688.equ INT_VECTORS_SIZE = 21 ; size in words 689 690#endif /* _TN4313DEF_INC_ */ 691 692; ***** END OF FILE ****************************************************** 693