1;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ******************** 2;***** Created: 2011-02-09 12:04 ******* Source: ATtiny44.xml ************ 3;************************************************************************* 4;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y 5;* 6;* Number : AVR000 7;* File Name : "tn44def.inc" 8;* Title : Register/Bit Definitions for the ATtiny44 9;* Date : 2011-02-09 10;* Version : 2.35 11;* Support E-mail : avr@atmel.com 12;* Target MCU : ATtiny44 13;* 14;* DESCRIPTION 15;* When including this file in the assembly program file, all I/O register 16;* names and I/O register bit names appearing in the data book can be used. 17;* In addition, the six registers forming the three data pointers X, Y and 18;* Z have been assigned names XL - ZH. Highest RAM address for Internal 19;* SRAM is also defined 20;* 21;* The Register names are represented by their hexadecimal address. 22;* 23;* The Register Bit names are represented by their bit number (0-7). 24;* 25;* Please observe the difference in using the bit names with instructions 26;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" 27;* (skip if bit in register set/cleared). The following example illustrates 28;* this: 29;* 30;* in r16,PORTB ;read PORTB latch 31;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#) 32;* out PORTB,r16 ;output to PORTB 33;* 34;* in r16,TIFR ;read the Timer Interrupt Flag Register 35;* sbrc r16,TOV0 ;test the overflow flag (use bit#) 36;* rjmp TOV0_is_set ;jump if set 37;* ... ;otherwise do something else 38;************************************************************************* 39 40#ifndef _TN44DEF_INC_ 41#define _TN44DEF_INC_ 42 43 44#pragma partinc 0 45 46; ***** SPECIFY DEVICE *************************************************** 47.device ATtiny44 48#pragma AVRPART ADMIN PART_NAME ATtiny44 49.equ SIGNATURE_000 = 0x1e 50.equ SIGNATURE_001 = 0x92 51.equ SIGNATURE_002 = 0x07 52 53#pragma AVRPART CORE CORE_VERSION V2 54#pragma AVRPART CORE NEW_INSTRUCTIONS lpm rd,z+ 55 56 57; ***** I/O REGISTER DEFINITIONS ***************************************** 58; NOTE: 59; Definitions marked "MEMORY MAPPED"are extended I/O ports 60; and cannot be used with IN/OUT instructions 61.equ SREG = 0x3f 62.equ SPL = 0x3d 63.equ SPH = 0x3e 64.equ OCR0B = 0x3c 65.equ GIMSK = 0x3b 66.equ GIFR = 0x3a 67.equ TIMSK0 = 0x39 68.equ TIFR0 = 0x38 69.equ SPMCSR = 0x37 70.equ OCR0A = 0x36 71.equ MCUCR = 0x35 72.equ MCUSR = 0x34 73.equ TCCR0B = 0x33 74.equ TCNT0 = 0x32 75.equ OSCCAL = 0x31 76.equ TCCR0A = 0x30 77.equ TCCR1A = 0x2f 78.equ TCCR1B = 0x2e 79.equ TCNT1L = 0x2c 80.equ TCNT1H = 0x2d 81.equ OCR1AL = 0x2a 82.equ OCR1AH = 0x2b 83.equ OCR1BL = 0x28 84.equ OCR1BH = 0x29 85.equ DWDR = 0x27 86.equ CLKPR = 0x26 87.equ ICR1L = 0x24 88.equ ICR1H = 0x25 89.equ GTCCR = 0x23 90.equ TCCR1C = 0x22 91.equ WDTCSR = 0x21 92.equ PCMSK1 = 0x20 93.equ EEARH = 0x1f 94.equ EEARL = 0x1e 95.equ EEDR = 0x1d 96.equ EECR = 0x1c 97.equ PORTA = 0x1b 98.equ DDRA = 0x1a 99.equ PINA = 0x19 100.equ PORTB = 0x18 101.equ DDRB = 0x17 102.equ PINB = 0x16 103.equ GPIOR2 = 0x15 104.equ GPIOR1 = 0x14 105.equ GPIOR0 = 0x13 106.equ PCMSK0 = 0x12 107.equ USIBR = 0x10 108.equ USIDR = 0x0f 109.equ USISR = 0x0e 110.equ USICR = 0x0d 111.equ TIMSK1 = 0x0c 112.equ TIFR1 = 0x0b 113.equ ACSR = 0x08 114.equ ADMUX = 0x07 115.equ ADCSRA = 0x06 116.equ ADCH = 0x05 117.equ ADCL = 0x04 118.equ ADCSRB = 0x03 119.equ DIDR0 = 0x01 120.equ PRR = 0x00 121 122 123; ***** BIT DEFINITIONS ************************************************** 124 125; ***** PORTA ************************ 126; PORTA - Port A Data Register 127.equ PORTA0 = 0 ; Port A Data Register bit 0 128.equ PA0 = 0 ; For compatibility 129.equ PORTA1 = 1 ; Port A Data Register bit 1 130.equ PA1 = 1 ; For compatibility 131.equ PORTA2 = 2 ; Port A Data Register bit 2 132.equ PA2 = 2 ; For compatibility 133.equ PORTA3 = 3 ; Port A Data Register bit 3 134.equ PA3 = 3 ; For compatibility 135.equ PORTA4 = 4 ; Port A Data Register bit 4 136.equ PA4 = 4 ; For compatibility 137.equ PORTA5 = 5 ; Port A Data Register bit 5 138.equ PA5 = 5 ; For compatibility 139.equ PORTA6 = 6 ; Port A Data Register bit 6 140.equ PA6 = 6 ; For compatibility 141.equ PORTA7 = 7 ; Port A Data Register bit 7 142.equ PA7 = 7 ; For compatibility 143 144; DDRA - Port A Data Direction Register 145.equ DDA0 = 0 ; Data Direction Register, Port A, bit 0 146.equ DDA1 = 1 ; Data Direction Register, Port A, bit 1 147.equ DDA2 = 2 ; Data Direction Register, Port A, bit 2 148.equ DDA3 = 3 ; Data Direction Register, Port A, bit 3 149.equ DDA4 = 4 ; Data Direction Register, Port A, bit 4 150.equ DDA5 = 5 ; Data Direction Register, Port A, bit 5 151.equ DDA6 = 6 ; Data Direction Register, Port A, bit 6 152.equ DDA7 = 7 ; Data Direction Register, Port A, bit 7 153 154; PINA - Port A Input Pins 155.equ PINA0 = 0 ; Input Pins, Port A bit 0 156.equ PINA1 = 1 ; Input Pins, Port A bit 1 157.equ PINA2 = 2 ; Input Pins, Port A bit 2 158.equ PINA3 = 3 ; Input Pins, Port A bit 3 159.equ PINA4 = 4 ; Input Pins, Port A bit 4 160.equ PINA5 = 5 ; Input Pins, Port A bit 5 161.equ PINA6 = 6 ; Input Pins, Port A bit 6 162.equ PINA7 = 7 ; Input Pins, Port A bit 7 163 164 165; ***** PORTB ************************ 166; PORTB - Data Register, Port B 167.equ PORTB0 = 0 ; 168.equ PB0 = 0 ; For compatibility 169.equ PORTB1 = 1 ; 170.equ PB1 = 1 ; For compatibility 171.equ PORTB2 = 2 ; 172.equ PB2 = 2 ; For compatibility 173.equ PORTB3 = 3 ; 174.equ PB3 = 3 ; For compatibility 175 176; DDRB - Data Direction Register, Port B 177.equ DDB0 = 0 ; 178.equ DDB1 = 1 ; 179.equ DDB2 = 2 ; 180.equ DDB3 = 3 ; 181 182; PINB - Input Pins, Port B 183.equ PINB0 = 0 ; 184.equ PINB1 = 1 ; 185.equ PINB2 = 2 ; 186.equ PINB3 = 3 ; 187 188 189; ***** ANALOG_COMPARATOR ************ 190; ADCSRB - ADC Control and Status Register B 191.equ ACME = 6 ; Analog Comparator Multiplexer Enable 192 193; ACSR - Analog Comparator Control And Status Register 194.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0 195.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1 196.equ ACIC = 2 ; Analog Comparator Input Capture Enable 197.equ ACIE = 3 ; Analog Comparator Interrupt Enable 198.equ ACI = 4 ; Analog Comparator Interrupt Flag 199.equ ACO = 5 ; Analog Compare Output 200.equ ACBG = 6 ; Analog Comparator Bandgap Select 201.equ AINBG = ACBG ; For compatibility 202.equ ACD = 7 ; Analog Comparator Disable 203 204; DIDR0 - 205.equ ADC0D = 0 ; ADC 0 Digital input buffer disable 206.equ ADC1D = 1 ; ADC 1 Digital input buffer disable 207 208 209; ***** AD_CONVERTER ***************** 210; ADMUX - ADC Multiplexer Selection Register 211.equ MUX0 = 0 ; Analog Channel and Gain Selection Bit 0 212.equ MUX1 = 1 ; Analog Channel and Gain Selection Bit 1 213.equ MUX2 = 2 ; Analog Channel and Gain Selection Bit 2 214.equ MUX3 = 3 ; Analog Channel and Gain Selection Bit 3 215.equ MUX4 = 4 ; Analog Channel and Gain Selection Bit 4 216.equ MUX5 = 5 ; Analog Channel and Gain Selection Bit 5 217.equ REFS0 = 6 ; Reference Selection Bit 0 218.equ REFS1 = 7 ; Reference Selection Bit 1 219 220; ADCSRA - ADC Control and Status Register A 221.equ ADPS0 = 0 ; ADC Prescaler Select Bit 0 222.equ ADPS1 = 1 ; ADC Prescaler Select Bit 1 223.equ ADPS2 = 2 ; ADC Prescaler Select Bit 2 224.equ ADIE = 3 ; ADC Interrupt Enable 225.equ ADIF = 4 ; ADC Interrupt Flag 226.equ ADATE = 5 ; ADC Auto Trigger Enable 227.equ ADSC = 6 ; ADC Start Conversion 228.equ ADEN = 7 ; ADC Enable 229 230; ADCH - ADC Data Register High Byte 231.equ ADCH0 = 0 ; ADC Data Register High Byte Bit 0 232.equ ADCH1 = 1 ; ADC Data Register High Byte Bit 1 233.equ ADCH2 = 2 ; ADC Data Register High Byte Bit 2 234.equ ADCH3 = 3 ; ADC Data Register High Byte Bit 3 235.equ ADCH4 = 4 ; ADC Data Register High Byte Bit 4 236.equ ADCH5 = 5 ; ADC Data Register High Byte Bit 5 237.equ ADCH6 = 6 ; ADC Data Register High Byte Bit 6 238.equ ADCH7 = 7 ; ADC Data Register High Byte Bit 7 239 240; ADCL - ADC Data Register Low Byte 241.equ ADCL0 = 0 ; ADC Data Register Low Byte Bit 0 242.equ ADCL1 = 1 ; ADC Data Register Low Byte Bit 1 243.equ ADCL2 = 2 ; ADC Data Register Low Byte Bit 2 244.equ ADCL3 = 3 ; ADC Data Register Low Byte Bit 3 245.equ ADCL4 = 4 ; ADC Data Register Low Byte Bit 4 246.equ ADCL5 = 5 ; ADC Data Register Low Byte Bit 5 247.equ ADCL6 = 6 ; ADC Data Register Low Byte Bit 6 248.equ ADCL7 = 7 ; ADC Data Register Low Byte Bit 7 249 250; ADCSRB - ADC Control and Status Register B 251.equ ADTS0 = 0 ; ADC Auto Trigger Source bit 0 252.equ ADTS1 = 1 ; ADC Auto Trigger Source bit 1 253.equ ADTS2 = 2 ; ADC Auto Trigger Source bit 2 254.equ ADLAR = 4 ; ADC Left Adjust Result 255.equ BIN = 7 ; Bipolar Input Mode 256 257; DIDR0 - Digital Input Disable Register 0 258;.equ ADC0D = 0 ; ADC0 Digital Input Disable 259;.equ ADC1D = 1 ; ADC1 Digital Input Disable 260.equ ADC2D = 2 ; ADC2 Digital Input Disable 261.equ ADC3D = 3 ; ADC3 Digital Input Disable 262.equ ADC4D = 4 ; ADC4 Digital Input Disable 263.equ ADC5D = 5 ; ADC5 Digital Input Disable 264.equ ADC6D = 6 ; ADC6 Digital Input Disable 265.equ ADC7D = 7 ; ADC7 Digital Input Disable 266 267 268; ***** USI ************************** 269; USIBR - USI Buffer Register 270.equ USIBR0 = 0 ; USI Buffer Register bit 0 271.equ USIBR1 = 1 ; USI Buffer Register bit 1 272.equ USIBR2 = 2 ; USI Buffer Register bit 2 273.equ USIBR3 = 3 ; USI Buffer Register bit 3 274.equ USIBR4 = 4 ; USI Buffer Register bit 4 275.equ USIBR5 = 5 ; USI Buffer Register bit 5 276.equ USIBR6 = 6 ; USI Buffer Register bit 6 277.equ USIBR7 = 7 ; USI Buffer Register bit 7 278 279; USIDR - USI Data Register 280.equ USIDR0 = 0 ; USI Data Register bit 0 281.equ USIDR1 = 1 ; USI Data Register bit 1 282.equ USIDR2 = 2 ; USI Data Register bit 2 283.equ USIDR3 = 3 ; USI Data Register bit 3 284.equ USIDR4 = 4 ; USI Data Register bit 4 285.equ USIDR5 = 5 ; USI Data Register bit 5 286.equ USIDR6 = 6 ; USI Data Register bit 6 287.equ USIDR7 = 7 ; USI Data Register bit 7 288 289; USISR - USI Status Register 290.equ USICNT0 = 0 ; USI Counter Value Bit 0 291.equ USICNT1 = 1 ; USI Counter Value Bit 1 292.equ USICNT2 = 2 ; USI Counter Value Bit 2 293.equ USICNT3 = 3 ; USI Counter Value Bit 3 294.equ USIDC = 4 ; Data Output Collision 295.equ USIPF = 5 ; Stop Condition Flag 296.equ USIOIF = 6 ; Counter Overflow Interrupt Flag 297.equ USISIF = 7 ; Start Condition Interrupt Flag 298 299; USICR - USI Control Register 300.equ USITC = 0 ; Toggle Clock Port Pin 301.equ USICLK = 1 ; Clock Strobe 302.equ USICS0 = 2 ; USI Clock Source Select Bit 0 303.equ USICS1 = 3 ; USI Clock Source Select Bit 1 304.equ USIWM0 = 4 ; USI Wire Mode Bit 0 305.equ USIWM1 = 5 ; USI Wire Mode Bit 1 306.equ USIOIE = 6 ; Counter Overflow Interrupt Enable 307.equ USISIE = 7 ; Start Condition Interrupt Enable 308 309 310; ***** EXTERNAL_INTERRUPT *********** 311; MCUCR - MCU Control Register 312.equ ISC00 = 0 ; Interrupt Sense Control 0 Bit 0 313.equ ISC01 = 1 ; Interrupt Sense Control 0 Bit 1 314 315; GIMSK - General Interrupt Mask Register 316.equ GICR = GIMSK ; For compatibility 317.equ PCIE0 = 4 ; Pin Change Interrupt Enable 0 318.equ PCIE1 = 5 ; Pin Change Interrupt Enable 1 319.equ INT0 = 6 ; External Interrupt Request 0 Enable 320 321; GIFR - General Interrupt Flag register 322.equ PCIF0 = 4 ; Pin Change Interrupt Flag 0 323.equ PCIF1 = 5 ; Pin Change Interrupt Flag 1 324.equ INTF0 = 6 ; External Interrupt Flag 0 325 326; PCMSK1 - Pin Change Enable Mask 1 327.equ PCINT8 = 0 ; Pin Change Enable Mask Bit 8 328.equ PCINT9 = 1 ; Pin Change Enable Mask Bit 9 329.equ PCINT10 = 2 ; Pin Change Enable Mask Bit 10 330.equ PCINT11 = 3 ; Pin Change Enable Mask Bit 11 331 332; PCMSK0 - Pin Change Enable Mask 0 333.equ PCINT0 = 0 ; Pin Change Enable Mask Bit 0 334.equ PCINT1 = 1 ; Pin Change Enable Mask Bit 1 335.equ PCINT2 = 2 ; Pin Change Enable Mask Bit 2 336.equ PCINT3 = 3 ; Pin Change Enable Mask Bit 3 337.equ PCINT4 = 4 ; Pin Change Enable Mask Bit 4 338.equ PCINT5 = 5 ; Pin Change Enable Mask Bit 5 339.equ PCINT6 = 6 ; Pin Change Enable Mask Bit 6 340.equ PCINT7 = 7 ; Pin Change Enable Mask Bit 7 341 342 343; ***** EEPROM *********************** 344; EEARL - EEPROM Address Register Low Byte 345.equ EEAR0 = 0 ; EEPROM Read/Write Access Bit 0 346.equ EEAR1 = 1 ; EEPROM Read/Write Access Bit 1 347.equ EEAR2 = 2 ; EEPROM Read/Write Access Bit 2 348.equ EEAR3 = 3 ; EEPROM Read/Write Access Bit 3 349.equ EEAR4 = 4 ; EEPROM Read/Write Access Bit 4 350.equ EEAR5 = 5 ; EEPROM Read/Write Access Bit 5 351.equ EEAR6 = 6 ; EEPROM Read/Write Access Bit 6 352.equ EEAR7 = 7 ; EEPROM Read/Write Access Bit 7 353 354; EEARH - EEPROM Address Register High Byte 355.equ EEAR8 = 0 ; EEPROM Read/Write Access Bit 0 356 357; EEDR - EEPROM Data Register 358.equ EEDR0 = 0 ; EEPROM Data Register bit 0 359.equ EEDR1 = 1 ; EEPROM Data Register bit 1 360.equ EEDR2 = 2 ; EEPROM Data Register bit 2 361.equ EEDR3 = 3 ; EEPROM Data Register bit 3 362.equ EEDR4 = 4 ; EEPROM Data Register bit 4 363.equ EEDR5 = 5 ; EEPROM Data Register bit 5 364.equ EEDR6 = 6 ; EEPROM Data Register bit 6 365.equ EEDR7 = 7 ; EEPROM Data Register bit 7 366 367; EECR - EEPROM Control Register 368.equ EERE = 0 ; EEPROM Read Enable 369.equ EEPE = 1 ; EEPROM Write Enable 370.equ EEMPE = 2 ; EEPROM Master Write Enable 371.equ EERIE = 3 ; EEPROM Ready Interrupt Enable 372.equ EEPM0 = 4 ; EEPROM Programming Mode Bit 0 373.equ EEPM1 = 5 ; EEPROM Programming Mode Bit 1 374 375 376; ***** WATCHDOG ********************* 377; WDTCSR - Watchdog Timer Control Register 378.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0 379.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1 380.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2 381.equ WDE = 3 ; Watch Dog Enable 382.equ WDCE = 4 ; Watchdog Change Enable 383.equ WDP3 = 5 ; Watchdog Timer Prescaler Bit 3 384.equ WDIE = 6 ; Watchdog Timeout Interrupt Enable 385.equ WDIF = 7 ; Watchdog Timeout Interrupt Flag 386 387 388; ***** TIMER_COUNTER_0 ************** 389; TIMSK0 - Timer/Counter Interrupt Mask Register 390.equ TOIE0 = 0 ; Timer/Counter0 Overflow Interrupt Enable 391.equ OCIE0A = 1 ; Timer/Counter0 Output Compare Match A Interrupt Enable 392.equ OCIE0B = 2 ; Timer/Counter0 Output Compare Match B Interrupt Enable 393 394; TIFR0 - Timer/Counter0 Interrupt Flag Register 395.equ TOV0 = 0 ; Timer/Counter0 Overflow Flag 396.equ OCF0A = 1 ; Timer/Counter0 Output Compare Flag A 397.equ OCF0B = 2 ; Timer/Counter0 Output Compare Flag B 398 399; TCCR0A - Timer/Counter Control Register A 400.equ WGM00 = 0 ; Waveform Generation Mode bit 0 401.equ WGM01 = 1 ; Waveform Generation Mode bit 1 402.equ COM0B0 = 4 ; Compare Match Output B Mode bit 0 403.equ COM0B1 = 5 ; Compare Match Output B Mode bit 1 404.equ COM0A0 = 6 ; Compare Match Output A Mode bit 0 405.equ COM0A1 = 7 ; Compare Match Output A Mode bit 1 406 407; TCCR0B - Timer/Counter Control Register B 408.equ CS00 = 0 ; Clock Select bit 0 409.equ CS01 = 1 ; Clock Select bit 1 410.equ CS02 = 2 ; Clock Select bit 2 411.equ WGM02 = 3 ; Waveform Generation Mode bit 2 412.equ FOC0B = 6 ; Force Output Compare B 413.equ FOC0A = 7 ; Force Output Compare A 414 415; TCNT0 - Timer/Counter0 416.equ TCNT0_0 = 0 ; 417.equ TCNT0_1 = 1 ; 418.equ TCNT0_2 = 2 ; 419.equ TCNT0_3 = 3 ; 420.equ TCNT0_4 = 4 ; 421.equ TCNT0_5 = 5 ; 422.equ TCNT0_6 = 6 ; 423.equ TCNT0_7 = 7 ; 424 425; OCR0A - Timer/Counter0 Output Compare Register A 426.equ OCR0A_0 = 0 ; 427.equ OCR0A_1 = 1 ; 428.equ OCR0A_2 = 2 ; 429.equ OCR0A_3 = 3 ; 430.equ OCR0A_4 = 4 ; 431.equ OCR0A_5 = 5 ; 432.equ OCR0A_6 = 6 ; 433.equ OCR0A_7 = 7 ; 434 435; OCR0B - Timer/Counter0 Output Compare Register B 436.equ OCR0_0 = 0 ; 437.equ OCR0_1 = 1 ; 438.equ OCR0_2 = 2 ; 439.equ OCR0_3 = 3 ; 440.equ OCR0_4 = 4 ; 441.equ OCR0_5 = 5 ; 442.equ OCR0_6 = 6 ; 443.equ OCR0_7 = 7 ; 444 445; GTCCR - General Timer/Counter Control Register 446.equ PSR10 = 0 ; Prescaler Reset Timer/CounterN 447.equ TSM = 7 ; Timer/Counter Synchronization Mode 448 449 450; ***** TIMER_COUNTER_1 ************** 451; TIMSK1 - Timer/Counter1 Interrupt Mask Register 452.equ TOIE1 = 0 ; Timer/Counter1 Overflow Interrupt Enable 453.equ OCIE1A = 1 ; Timer/Counter1 Output Compare A Match Interrupt Enable 454.equ OCIE1B = 2 ; Timer/Counter1 Output Compare B Match Interrupt Enable 455.equ ICIE1 = 5 ; Timer/Counter1 Input Capture Interrupt Enable 456 457; TIFR1 - Timer/Counter Interrupt Flag register 458.equ TOV1 = 0 ; Timer/Counter1 Overflow Flag 459.equ OCF1A = 1 ; Timer/Counter1 Output Compare A Match Flag 460.equ OCF1B = 2 ; Timer/Counter1 Output Compare B Match Flag 461.equ ICF1 = 5 ; Timer/Counter1 Input Capture Flag 462 463; TCCR1A - Timer/Counter1 Control Register A 464.equ WGM10 = 0 ; Pulse Width Modulator Select Bit 0 465.equ PWM10 = WGM10 ; For compatibility 466.equ WGM11 = 1 ; Pulse Width Modulator Select Bit 1 467.equ PWM11 = WGM11 ; For compatibility 468.equ COM1B0 = 4 ; Comparet Ouput Mode 1B, bit 0 469.equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1 470.equ COM1A0 = 6 ; Comparet Ouput Mode 1A, bit 0 471.equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1 472 473; TCCR1B - Timer/Counter1 Control Register B 474.equ CS10 = 0 ; Clock Select bit 0 475.equ CS11 = 1 ; Clock Select 1 bit 1 476.equ CS12 = 2 ; Clock Select1 bit 2 477.equ WGM12 = 3 ; Waveform Generation Mode Bit 2 478.equ CTC1 = WGM12 ; For compatibility 479.equ WGM13 = 4 ; Waveform Generation Mode Bit 3 480.equ ICES1 = 6 ; Input Capture 1 Edge Select 481.equ ICNC1 = 7 ; Input Capture 1 Noise Canceler 482 483; TCCR1C - Timer/Counter1 Control Register C 484.equ FOC1B = 6 ; Force Output Compare for Channel B 485.equ FOC1A = 7 ; Force Output Compare for Channel A 486 487 488; ***** BOOT_LOAD ******************** 489; SPMCSR - Store Program Memory Control Register 490.equ SPMEN = 0 ; Store Program Memory Enable 491.equ PGERS = 1 ; Page Erase 492.equ PGWRT = 2 ; Page Write 493.equ RFLB = 3 ; Read fuse and lock bits 494.equ CTPB = 4 ; Clear temporary page buffer 495 496 497; ***** CPU ************************** 498; SREG - Status Register 499.equ SREG_C = 0 ; Carry Flag 500.equ SREG_Z = 1 ; Zero Flag 501.equ SREG_N = 2 ; Negative Flag 502.equ SREG_V = 3 ; Two's Complement Overflow Flag 503.equ SREG_S = 4 ; Sign Bit 504.equ SREG_H = 5 ; Half Carry Flag 505.equ SREG_T = 6 ; Bit Copy Storage 506.equ SREG_I = 7 ; Global Interrupt Enable 507 508; MCUCR - MCU Control Register 509.equ SM0 = 3 ; Sleep Mode Select Bit 0 510.equ SM1 = 4 ; Sleep Mode Select Bit 1 511.equ SE = 5 ; Sleep Enable 512.equ PUD = 6 ; 513 514; MCUSR - MCU Status Register 515.equ PORF = 0 ; Power-on reset flag 516.equ EXTRF = 1 ; External Reset Flag 517.equ BORF = 2 ; Brown-out Reset Flag 518.equ WDRF = 3 ; Watchdog Reset Flag 519 520; OSCCAL - Oscillator Calibration Value 521.equ CAL0 = 0 ; Oscillator Calibration Value Bit0 522.equ CAL1 = 1 ; Oscillator Calibration Value Bit1 523.equ CAL2 = 2 ; Oscillator Calibration Value Bit2 524.equ CAL3 = 3 ; Oscillator Calibration Value Bit3 525.equ CAL4 = 4 ; Oscillator Calibration Value Bit4 526.equ CAL5 = 5 ; Oscillator Calibration Value Bit5 527.equ CAL6 = 6 ; Oscillator Calibration Value Bit6 528.equ CAL7 = 7 ; Oscillator Calibration Value Bit7 529 530; GPIOR2 - General Purpose I/O Register 2 531.equ GPIOR20 = 0 ; 532.equ GPIOR21 = 1 ; 533.equ GPIOR22 = 2 ; 534.equ GPIOR23 = 3 ; 535.equ GPIOR24 = 4 ; 536.equ GPIOR25 = 5 ; 537.equ GPIOR26 = 6 ; 538.equ GPIOR27 = 7 ; 539 540; GPIOR1 - General Purpose I/O Register 1 541.equ GPIOR10 = 0 ; 542.equ GPIOR11 = 1 ; 543.equ GPIOR12 = 2 ; 544.equ GPIOR13 = 3 ; 545.equ GPIOR14 = 4 ; 546.equ GPIOR15 = 5 ; 547.equ GPIOR16 = 6 ; 548.equ GPIOR17 = 7 ; 549 550; GPIOR0 - General Purpose I/O Register 0 551.equ GPIOR00 = 0 ; 552.equ GPIOR01 = 1 ; 553.equ GPIOR02 = 2 ; 554.equ GPIOR03 = 3 ; 555.equ GPIOR04 = 4 ; 556.equ GPIOR05 = 5 ; 557.equ GPIOR06 = 6 ; 558.equ GPIOR07 = 7 ; 559 560; PRR - Power Reduction Register 561.equ PRADC = 0 ; Power Reduction ADC 562.equ PRUSI = 1 ; Power Reduction USI 563.equ PRTIM0 = 2 ; Power Reduction Timer/Counter0 564.equ PRTIM1 = 3 ; Power Reduction Timer/Counter1 565 566; CLKPR - Clock Prescale Register 567.equ CLKPS0 = 0 ; Clock Prescaler Select Bit 0 568.equ CLKPS1 = 1 ; Clock Prescaler Select Bit 1 569.equ CLKPS2 = 2 ; Clock Prescaler Select Bit 2 570.equ CLKPS3 = 3 ; Clock Prescaler Select Bit 3 571.equ CLKPCE = 7 ; Clock Prescaler Change Enable 572 573 574 575; ***** LOCKSBITS ******************************************************** 576.equ LB1 = 0 ; Lockbit 577.equ LB2 = 1 ; Lockbit 578 579 580; ***** FUSES ************************************************************ 581; LOW fuse bits 582.equ CKSEL0 = 0 ; Select Clock source 583.equ CKSEL1 = 1 ; Select Clock source 584.equ CKSEL2 = 2 ; Select Clock source 585.equ CKSEL3 = 3 ; Select Clock source 586.equ SUT0 = 4 ; Select start-up time 587.equ SUT1 = 5 ; Select start-up time 588.equ CKOUT = 6 ; Clock Output Enable 589.equ CKDIV8 = 7 ; Divide clock by 8 590 591; HIGH fuse bits 592.equ BODLEVEL0 = 0 ; Brown-out Detector trigger level 593.equ BODLEVEL1 = 1 ; Brown-out Detector trigger level 594.equ BODLEVEL2 = 2 ; Brown-out Detector trigger level 595.equ EESAVE = 3 ; EEPROM memory is preserved through the Chip Erase 596.equ WDTON = 4 ; Watchdog Timer always on 597.equ SPIEN = 5 ; Enable Serial Program and Data Downloading 598.equ DWEN = 6 ; DebugWIRE Enable 599.equ RSTDISBL = 7 ; External Reset disable 600 601; EXTENDED fuse bits 602.equ SELFPRGEN = 0 ; Self-Programming Enable 603 604 605 606; ***** CPU REGISTER DEFINITIONS ***************************************** 607.def XH = r27 608.def XL = r26 609.def YH = r29 610.def YL = r28 611.def ZH = r31 612.def ZL = r30 613 614 615 616; ***** DATA MEMORY DECLARATIONS ***************************************** 617.equ FLASHEND = 0x07ff ; Note: Word address 618.equ IOEND = 0x003f 619.equ SRAM_START = 0x0060 620.equ SRAM_SIZE = 256 621.equ RAMEND = 0x015f 622.equ XRAMEND = 0x0000 623.equ E2END = 0x00ff 624.equ EEPROMEND = 0x00ff 625.equ EEADRBITS = 8 626#pragma AVRPART MEMORY PROG_FLASH 4096 627#pragma AVRPART MEMORY EEPROM 256 628#pragma AVRPART MEMORY INT_SRAM SIZE 256 629#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x60 630 631 632 633; ***** BOOTLOADER DECLARATIONS ****************************************** 634.equ NRWW_START_ADDR = 0x0 635.equ NRWW_STOP_ADDR = 0x7ff 636.equ RWW_START_ADDR = 0x0 637.equ RWW_STOP_ADDR = 0x0 638.equ PAGESIZE = 32 639 640 641 642; ***** INTERRUPT VECTORS ************************************************ 643.equ EXT_INT0addr = 0x0001 ; External Interrupt Request 0 644.equ PCI0addr = 0x0002 ; Pin Change Interrupt Request 0 645.equ PCI1addr = 0x0003 ; Pin Change Interrupt Request 1 646.equ WATCHDOGaddr = 0x0004 ; Watchdog Time-out 647.equ ICP1addr = 0x0005 ; Timer/Counter1 Capture Event 648.equ OC1Aaddr = 0x0006 ; Timer/Counter1 Compare Match A 649.equ OC1Baddr = 0x0007 ; Timer/Counter1 Compare Match B 650.equ OVF1addr = 0x0008 ; Timer/Counter1 Overflow 651.equ OC0Aaddr = 0x0009 ; Timer/Counter0 Compare Match A 652.equ OC0Baddr = 0x000a ; Timer/Counter0 Compare Match B 653.equ OVF0addr = 0x000b ; Timer/Counter0 Overflow 654.equ ACIaddr = 0x000c ; Analog Comparator 655.equ ADCCaddr = 0x000d ; ADC Conversion Complete 656.equ ERDYaddr = 0x000e ; EEPROM Ready 657.equ USI_STRaddr = 0x000f ; USI START 658.equ USI_OVFaddr = 0x0010 ; USI Overflow 659 660.equ INT_VECTORS_SIZE = 17 ; size in words 661 662#endif /* _TN44DEF_INC_ */ 663 664; ***** END OF FILE ****************************************************** 665