1;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ******************** 2;***** Created: 2011-02-09 12:04 ******* Source: ATtiny48.xml ************ 3;************************************************************************* 4;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y 5;* 6;* Number : AVR000 7;* File Name : "tn48def.inc" 8;* Title : Register/Bit Definitions for the ATtiny48 9;* Date : 2011-02-09 10;* Version : 2.35 11;* Support E-mail : avr@atmel.com 12;* Target MCU : ATtiny48 13;* 14;* DESCRIPTION 15;* When including this file in the assembly program file, all I/O register 16;* names and I/O register bit names appearing in the data book can be used. 17;* In addition, the six registers forming the three data pointers X, Y and 18;* Z have been assigned names XL - ZH. Highest RAM address for Internal 19;* SRAM is also defined 20;* 21;* The Register names are represented by their hexadecimal address. 22;* 23;* The Register Bit names are represented by their bit number (0-7). 24;* 25;* Please observe the difference in using the bit names with instructions 26;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" 27;* (skip if bit in register set/cleared). The following example illustrates 28;* this: 29;* 30;* in r16,PORTB ;read PORTB latch 31;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#) 32;* out PORTB,r16 ;output to PORTB 33;* 34;* in r16,TIFR ;read the Timer Interrupt Flag Register 35;* sbrc r16,TOV0 ;test the overflow flag (use bit#) 36;* rjmp TOV0_is_set ;jump if set 37;* ... ;otherwise do something else 38;************************************************************************* 39 40#ifndef _TN48DEF_INC_ 41#define _TN48DEF_INC_ 42 43 44#pragma partinc 0 45 46; ***** SPECIFY DEVICE *************************************************** 47.device ATtiny48 48#pragma AVRPART ADMIN PART_NAME ATtiny48 49.equ SIGNATURE_000 = 0x1e 50.equ SIGNATURE_001 = 0x92 51.equ SIGNATURE_002 = 0x09 52 53#pragma AVRPART CORE CORE_VERSION V2 54#pragma AVRPART CORE NEW_INSTRUCTIONS lpm rd,z+ 55 56 57; ***** I/O REGISTER DEFINITIONS ***************************************** 58; NOTE: 59; Definitions marked "MEMORY MAPPED"are extended I/O ports 60; and cannot be used with IN/OUT instructions 61.equ TWHSR = 0xbe ; MEMORY MAPPED 62.equ TWAMR = 0xbd ; MEMORY MAPPED 63.equ TWCR = 0xbc ; MEMORY MAPPED 64.equ TWDR = 0xbb ; MEMORY MAPPED 65.equ TWAR = 0xba ; MEMORY MAPPED 66.equ TWSR = 0xb9 ; MEMORY MAPPED 67.equ TWBR = 0xb8 ; MEMORY MAPPED 68.equ OCR1BL = 0x8a ; MEMORY MAPPED 69.equ OCR1BH = 0x8b ; MEMORY MAPPED 70.equ OCR1AL = 0x88 ; MEMORY MAPPED 71.equ OCR1AH = 0x89 ; MEMORY MAPPED 72.equ ICR1L = 0x86 ; MEMORY MAPPED 73.equ ICR1H = 0x87 ; MEMORY MAPPED 74.equ TCNT1L = 0x84 ; MEMORY MAPPED 75.equ TCNT1H = 0x85 ; MEMORY MAPPED 76.equ TCCR1C = 0x82 ; MEMORY MAPPED 77.equ TCCR1B = 0x81 ; MEMORY MAPPED 78.equ TCCR1A = 0x80 ; MEMORY MAPPED 79.equ DIDR1 = 0x7f ; MEMORY MAPPED 80.equ DIDR0 = 0x7e ; MEMORY MAPPED 81.equ ADMUX = 0x7c ; MEMORY MAPPED 82.equ ADCSRB = 0x7b ; MEMORY MAPPED 83.equ ADCSRA = 0x7a ; MEMORY MAPPED 84.equ ADCH = 0x79 ; MEMORY MAPPED 85.equ ADCL = 0x78 ; MEMORY MAPPED 86.equ TIMSK1 = 0x6f ; MEMORY MAPPED 87.equ TIMSK0 = 0x6e ; MEMORY MAPPED 88.equ PCMSK2 = 0x6d ; MEMORY MAPPED 89.equ PCMSK1 = 0x6c ; MEMORY MAPPED 90.equ PCMSK0 = 0x6b ; MEMORY MAPPED 91.equ PCMSK3 = 0x6a ; MEMORY MAPPED 92.equ EICRA = 0x69 ; MEMORY MAPPED 93.equ PCICR = 0x68 ; MEMORY MAPPED 94.equ OSCCAL = 0x66 ; MEMORY MAPPED 95.equ PRR = 0x64 ; MEMORY MAPPED 96.equ CLKPR = 0x61 ; MEMORY MAPPED 97.equ WDTCSR = 0x60 ; MEMORY MAPPED 98.equ SREG = 0x3f 99.equ SPH = 0x3e 100.equ SPL = 0x3d 101.equ SPMCSR = 0x37 102.equ MCUCR = 0x35 103.equ MCUSR = 0x34 104.equ SMCR = 0x33 105.equ ACSR = 0x30 106.equ SPDR = 0x2e 107.equ SPSR = 0x2d 108.equ SPCR = 0x2c 109.equ GPIOR2 = 0x2b 110.equ GPIOR1 = 0x2a 111.equ OCR0B = 0x28 112.equ OCR0A = 0x27 113.equ TCNT0 = 0x26 114.equ TCCR0A = 0x25 115.equ GTCCR = 0x23 116.equ EEARL = 0x21 117.equ EEDR = 0x20 118.equ EECR = 0x1f 119.equ GPIOR0 = 0x1e 120.equ EIMSK = 0x1d 121.equ EIFR = 0x1c 122.equ PCIFR = 0x1b 123.equ TIFR1 = 0x16 124.equ TIFR0 = 0x15 125.equ PORTCR = 0x12 126.equ PORTA = 0x0e 127.equ DDRA = 0x0d 128.equ PINA = 0x0c 129.equ PORTD = 0x0b 130.equ DDRD = 0x0a 131.equ PIND = 0x09 132.equ PORTC = 0x08 133.equ DDRC = 0x07 134.equ PINC = 0x06 135.equ PORTB = 0x05 136.equ DDRB = 0x04 137.equ PINB = 0x03 138 139 140; ***** BIT DEFINITIONS ************************************************** 141 142; ***** TIMER_COUNTER_1 ************** 143; TIMSK1 - Timer/Counter Interrupt Mask Register 144.equ TOIE1 = 0 ; Timer/Counter1 Overflow Interrupt Enable 145.equ OCIE1A = 1 ; Timer/Counter1 Output CompareA Match Interrupt Enable 146.equ OCIE1B = 2 ; Timer/Counter1 Output CompareB Match Interrupt Enable 147.equ ICIE1 = 5 ; Timer/Counter1 Input Capture Interrupt Enable 148 149; TIFR1 - Timer/Counter Interrupt Flag register 150.equ TOV1 = 0 ; Timer/Counter1 Overflow Flag 151.equ OCF1A = 1 ; Output Compare Flag 1A 152.equ OCF1B = 2 ; Output Compare Flag 1B 153.equ ICF1 = 5 ; Input Capture Flag 1 154 155; TCCR1A - Timer/Counter1 Control Register A 156.equ WGM10 = 0 ; Waveform Generation Mode 157.equ WGM11 = 1 ; Waveform Generation Mode 158.equ COM1B0 = 4 ; Compare Output Mode 1B, bit 0 159.equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1 160.equ COM1A0 = 6 ; Comparet Ouput Mode 1A, bit 0 161.equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1 162 163; TCCR1B - Timer/Counter1 Control Register B 164.equ CS10 = 0 ; Prescaler source of Timer/Counter 1 165.equ CS11 = 1 ; Prescaler source of Timer/Counter 1 166.equ CS12 = 2 ; Prescaler source of Timer/Counter 1 167.equ WGM12 = 3 ; Waveform Generation Mode 168.equ WGM13 = 4 ; Waveform Generation Mode 169.equ ICES1 = 6 ; Input Capture 1 Edge Select 170.equ ICNC1 = 7 ; Input Capture 1 Noise Canceler 171 172; TCCR1C - Timer/Counter1 Control Register C 173.equ FOC1B = 6 ; 174.equ FOC1A = 7 ; 175 176; GTCCR - General Timer/Counter Control Register 177.equ PSRSYNC = 0 ; Prescaler Reset Timer/Counter1 and Timer/Counter0 178.equ TSM = 7 ; Timer/Counter Synchronization Mode 179 180 181; ***** ANALOG_COMPARATOR ************ 182; ACSR - Analog Comparator Control And Status Register 183.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0 184.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1 185.equ ACIC = 2 ; Analog Comparator Input Capture Enable 186.equ ACIE = 3 ; Analog Comparator Interrupt Enable 187.equ ACI = 4 ; Analog Comparator Interrupt Flag 188.equ ACO = 5 ; Analog Compare Output 189.equ ACBG = 6 ; Analog Comparator Bandgap Select 190.equ ACD = 7 ; Analog Comparator Disable 191 192; DIDR1 - Digital Input Disable Register 1 193.equ AIN0D = 0 ; AIN0 Digital Input Disable 194.equ AIN1D = 1 ; AIN1 Digital Input Disable 195 196 197; ***** PORTB ************************ 198; PORTB - Port B Data Register 199.equ PORTB0 = 0 ; Port B Data Register bit 0 200.equ PB0 = 0 ; For compatibility 201.equ PORTB1 = 1 ; Port B Data Register bit 1 202.equ PB1 = 1 ; For compatibility 203.equ PORTB2 = 2 ; Port B Data Register bit 2 204.equ PB2 = 2 ; For compatibility 205.equ PORTB3 = 3 ; Port B Data Register bit 3 206.equ PB3 = 3 ; For compatibility 207.equ PORTB4 = 4 ; Port B Data Register bit 4 208.equ PB4 = 4 ; For compatibility 209.equ PORTB5 = 5 ; Port B Data Register bit 5 210.equ PB5 = 5 ; For compatibility 211.equ PORTB6 = 6 ; Port B Data Register bit 6 212.equ PB6 = 6 ; For compatibility 213.equ PORTB7 = 7 ; Port B Data Register bit 7 214.equ PB7 = 7 ; For compatibility 215 216; DDRB - Port B Data Direction Register 217.equ DDB0 = 0 ; Port B Data Direction Register bit 0 218.equ DDB1 = 1 ; Port B Data Direction Register bit 1 219.equ DDB2 = 2 ; Port B Data Direction Register bit 2 220.equ DDB3 = 3 ; Port B Data Direction Register bit 3 221.equ DDB4 = 4 ; Port B Data Direction Register bit 4 222.equ DDB5 = 5 ; Port B Data Direction Register bit 5 223.equ DDB6 = 6 ; Port B Data Direction Register bit 6 224.equ DDB7 = 7 ; Port B Data Direction Register bit 7 225 226; PINB - Port B Input Pins 227.equ PINB0 = 0 ; Port B Input Pins bit 0 228.equ PINB1 = 1 ; Port B Input Pins bit 1 229.equ PINB2 = 2 ; Port B Input Pins bit 2 230.equ PINB3 = 3 ; Port B Input Pins bit 3 231.equ PINB4 = 4 ; Port B Input Pins bit 4 232.equ PINB5 = 5 ; Port B Input Pins bit 5 233.equ PINB6 = 6 ; Port B Input Pins bit 6 234.equ PINB7 = 7 ; Port B Input Pins bit 7 235 236 237; ***** PORTD ************************ 238; PORTD - Port D Data Register 239.equ PORTD0 = 0 ; Port D Data Register bit 0 240.equ PD0 = 0 ; For compatibility 241.equ PORTD1 = 1 ; Port D Data Register bit 1 242.equ PD1 = 1 ; For compatibility 243.equ PORTD2 = 2 ; Port D Data Register bit 2 244.equ PD2 = 2 ; For compatibility 245.equ PORTD3 = 3 ; Port D Data Register bit 3 246.equ PD3 = 3 ; For compatibility 247.equ PORTD4 = 4 ; Port D Data Register bit 4 248.equ PD4 = 4 ; For compatibility 249.equ PORTD5 = 5 ; Port D Data Register bit 5 250.equ PD5 = 5 ; For compatibility 251.equ PORTD6 = 6 ; Port D Data Register bit 6 252.equ PD6 = 6 ; For compatibility 253.equ PORTD7 = 7 ; Port D Data Register bit 7 254.equ PD7 = 7 ; For compatibility 255 256; DDRD - Port D Data Direction Register 257.equ DDD0 = 0 ; Port D Data Direction Register bit 0 258.equ DDD1 = 1 ; Port D Data Direction Register bit 1 259.equ DDD2 = 2 ; Port D Data Direction Register bit 2 260.equ DDD3 = 3 ; Port D Data Direction Register bit 3 261.equ DDD4 = 4 ; Port D Data Direction Register bit 4 262.equ DDD5 = 5 ; Port D Data Direction Register bit 5 263.equ DDD6 = 6 ; Port D Data Direction Register bit 6 264.equ DDD7 = 7 ; Port D Data Direction Register bit 7 265 266; PIND - Port D Input Pins 267.equ PIND0 = 0 ; Port D Input Pins bit 0 268.equ PIND1 = 1 ; Port D Input Pins bit 1 269.equ PIND2 = 2 ; Port D Input Pins bit 2 270.equ PIND3 = 3 ; Port D Input Pins bit 3 271.equ PIND4 = 4 ; Port D Input Pins bit 4 272.equ PIND5 = 5 ; Port D Input Pins bit 5 273.equ PIND6 = 6 ; Port D Input Pins bit 6 274.equ PIND7 = 7 ; Port D Input Pins bit 7 275 276 277; ***** SPI ************************** 278; SPDR - SPI Data Register 279.equ SPDR0 = 0 ; SPI Data Register bit 0 280.equ SPDR1 = 1 ; SPI Data Register bit 1 281.equ SPDR2 = 2 ; SPI Data Register bit 2 282.equ SPDR3 = 3 ; SPI Data Register bit 3 283.equ SPDR4 = 4 ; SPI Data Register bit 4 284.equ SPDR5 = 5 ; SPI Data Register bit 5 285.equ SPDR6 = 6 ; SPI Data Register bit 6 286.equ SPDR7 = 7 ; SPI Data Register bit 7 287 288; SPSR - SPI Status Register 289.equ SPI2X = 0 ; Double SPI Speed Bit 290.equ WCOL = 6 ; Write Collision Flag 291.equ SPIF = 7 ; SPI Interrupt Flag 292 293; SPCR - SPI Control Register 294.equ SPR0 = 0 ; SPI Clock Rate Select 0 295.equ SPR1 = 1 ; SPI Clock Rate Select 1 296.equ CPHA = 2 ; Clock Phase 297.equ CPOL = 3 ; Clock polarity 298.equ MSTR = 4 ; Master/Slave Select 299.equ DORD = 5 ; Data Order 300.equ SPE = 6 ; SPI Enable 301.equ SPIE = 7 ; SPI Interrupt Enable 302 303 304; ***** WATCHDOG ********************* 305; WDTCSR - Watchdog Timer Control Register 306.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0 307.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1 308.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2 309.equ WDE = 3 ; Watch Dog Enable 310.equ WDCE = 4 ; Watchdog Change Enable 311.equ WDP3 = 5 ; Watchdog Timer Prescaler Bit 3 312.equ WDIE = 6 ; Watchdog Timeout Interrupt Enable 313.equ WDIF = 7 ; Watchdog Timeout Interrupt Flag 314 315 316; ***** CPU ************************** 317; SREG - Status Register 318.equ SREG_C = 0 ; Carry Flag 319.equ SREG_Z = 1 ; Zero Flag 320.equ SREG_N = 2 ; Negative Flag 321.equ SREG_V = 3 ; Two's Complement Overflow Flag 322.equ SREG_S = 4 ; Sign Bit 323.equ SREG_H = 5 ; Half Carry Flag 324.equ SREG_T = 6 ; Bit Copy Storage 325.equ SREG_I = 7 ; Global Interrupt Enable 326 327; SPH - Stack Pointe High 328.equ SP8 = 0 ; Stack pointer bit 8 329 330; SPL - Stack Pointe Low 331.equ SP0 = 0 ; Stack pointer bit 0 332.equ SP1 = 1 ; Stack pointer bit 1 333.equ SP2 = 2 ; Stack pointer bit 2 334.equ SP3 = 3 ; Stack pointer bit 3 335.equ SP4 = 4 ; Stack pointer bit 4 336.equ SP5 = 5 ; Stack pointer bit 5 337.equ SP6 = 6 ; Stack pointer bit 6 338.equ SP7 = 7 ; Stack pointer bit 7 339 340; OSCCAL - Oscillator Calibration Value 341.equ CAL0 = 0 ; Oscillator Calibration Value Bit0 342.equ CAL1 = 1 ; Oscillator Calibration Value Bit1 343.equ CAL2 = 2 ; Oscillator Calibration Value Bit2 344.equ CAL3 = 3 ; Oscillator Calibration Value Bit3 345.equ CAL4 = 4 ; Oscillator Calibration Value Bit4 346.equ CAL5 = 5 ; Oscillator Calibration Value Bit5 347.equ CAL6 = 6 ; Oscillator Calibration Value Bit6 348.equ CAL7 = 7 ; Oscillator Calibration Value Bit7 349 350; CLKPR - Clock Prescale Register 351.equ CLKPS0 = 0 ; Clock Prescaler Select Bit 0 352.equ CLKPS1 = 1 ; Clock Prescaler Select Bit 1 353.equ CLKPS2 = 2 ; Clock Prescaler Select Bit 2 354.equ CLKPS3 = 3 ; Clock Prescaler Select Bit 3 355.equ CLKPCE = 7 ; Clock Prescaler Change Enable 356 357; SPMCSR - Store Program Memory Control Register 358.equ SELFPRGEN = 0 ; Self Programming Enable 359.equ PGERS = 1 ; Page Erase 360.equ PGWRT = 2 ; Page Write 361.equ RFLB = 3 ; Read Fuse and Lock Bits 362.equ CTPB = 4 ; Clear Temporary Page Buffer 363.equ RWWSB = 6 ; Read-While-Write Section Busy 364 365; MCUCR - MCU Control Register 366.equ PUD = 4 ; 367.equ BODSE = 5 ; BOD Sleep Enable 368.equ BODS = 6 ; BOD Sleep 369 370; MCUSR - MCU Status Register 371.equ PORF = 0 ; Power-on reset flag 372.equ EXTRF = 1 ; External Reset Flag 373.equ EXTREF = EXTRF ; For compatibility 374.equ BORF = 2 ; Brown-out Reset Flag 375.equ WDRF = 3 ; Watchdog Reset Flag 376 377; SMCR - 378.equ SE = 0 ; 379.equ SM0 = 1 ; 380.equ SM1 = 2 ; 381 382; GPIOR2 - General Purpose I/O Register 2 383.equ GPIOR20 = 0 ; 384.equ GPIOR21 = 1 ; 385.equ GPIOR22 = 2 ; 386.equ GPIOR23 = 3 ; 387.equ GPIOR24 = 4 ; 388.equ GPIOR25 = 5 ; 389.equ GPIOR26 = 6 ; 390.equ GPIOR27 = 7 ; 391 392; GPIOR1 - General Purpose I/O Register 1 393.equ GPIOR10 = 0 ; 394.equ GPIOR11 = 1 ; 395.equ GPIOR12 = 2 ; 396.equ GPIOR13 = 3 ; 397.equ GPIOR14 = 4 ; 398.equ GPIOR15 = 5 ; 399.equ GPIOR16 = 6 ; 400.equ GPIOR17 = 7 ; 401 402; GPIOR0 - General Purpose I/O Register 0 403.equ GPIOR00 = 0 ; 404.equ GPIOR01 = 1 ; 405.equ GPIOR02 = 2 ; 406.equ GPIOR03 = 3 ; 407.equ GPIOR04 = 4 ; 408.equ GPIOR05 = 5 ; 409.equ GPIOR06 = 6 ; 410.equ GPIOR07 = 7 ; 411 412; PRR - Power Reduction Register 413.equ PRADC = 0 ; Power Reduction ADC 414.equ PRSPI = 2 ; Power Reduction Serial Peripheral Interface 415.equ PRTIM1 = 3 ; Power Reduction Timer/Counter1 416.equ PRTIM0 = 5 ; Power Reduction Timer/Counter0 417.equ PRTWI = 7 ; Power Reduction TWI 418 419; PORTCR - Port Configuration Register 420.equ PUDA = 0 ; 421.equ PUDB = 1 ; 422.equ PUDC = 2 ; 423.equ PUDD = 3 ; 424.equ BBMA = 4 ; 425.equ BBMB = 5 ; 426.equ BBMC = 6 ; 427.equ BBMD = 7 ; 428 429 430; ***** TWI ************************** 431; TWHSR - TWHSR 432.equ TWHS = 0 ; 433 434; TWAMR - TWI (Slave) Address Mask Register 435.equ TWAM0 = 1 ; 436.equ TWAMR0 = TWAM0 ; For compatibility 437.equ TWAM1 = 2 ; 438.equ TWAMR1 = TWAM1 ; For compatibility 439.equ TWAM2 = 3 ; 440.equ TWAMR2 = TWAM2 ; For compatibility 441.equ TWAM3 = 4 ; 442.equ TWAMR3 = TWAM3 ; For compatibility 443.equ TWAM4 = 5 ; 444.equ TWAMR4 = TWAM4 ; For compatibility 445.equ TWAM5 = 6 ; 446.equ TWAMR5 = TWAM5 ; For compatibility 447.equ TWAM6 = 7 ; 448.equ TWAMR6 = TWAM6 ; For compatibility 449 450; TWBR - TWI Bit Rate register 451.equ TWBR0 = 0 ; 452.equ TWBR1 = 1 ; 453.equ TWBR2 = 2 ; 454.equ TWBR3 = 3 ; 455.equ TWBR4 = 4 ; 456.equ TWBR5 = 5 ; 457.equ TWBR6 = 6 ; 458.equ TWBR7 = 7 ; 459 460; TWCR - TWI Control Register 461.equ TWIE = 0 ; TWI Interrupt Enable 462.equ TWEN = 2 ; TWI Enable Bit 463.equ TWWC = 3 ; TWI Write Collition Flag 464.equ TWSTO = 4 ; TWI Stop Condition Bit 465.equ TWSTA = 5 ; TWI Start Condition Bit 466.equ TWEA = 6 ; TWI Enable Acknowledge Bit 467.equ TWINT = 7 ; TWI Interrupt Flag 468 469; TWSR - TWI Status Register 470.equ TWPS0 = 0 ; TWI Prescaler 471.equ TWPS1 = 1 ; TWI Prescaler 472.equ TWS3 = 3 ; TWI Status 473.equ TWS4 = 4 ; TWI Status 474.equ TWS5 = 5 ; TWI Status 475.equ TWS6 = 6 ; TWI Status 476.equ TWS7 = 7 ; TWI Status 477 478; TWDR - TWI Data register 479.equ TWD0 = 0 ; TWI Data Register Bit 0 480.equ TWD1 = 1 ; TWI Data Register Bit 1 481.equ TWD2 = 2 ; TWI Data Register Bit 2 482.equ TWD3 = 3 ; TWI Data Register Bit 3 483.equ TWD4 = 4 ; TWI Data Register Bit 4 484.equ TWD5 = 5 ; TWI Data Register Bit 5 485.equ TWD6 = 6 ; TWI Data Register Bit 6 486.equ TWD7 = 7 ; TWI Data Register Bit 7 487 488; TWAR - TWI (Slave) Address register 489.equ TWGCE = 0 ; TWI General Call Recognition Enable Bit 490.equ TWA0 = 1 ; TWI (Slave) Address register Bit 0 491.equ TWA1 = 2 ; TWI (Slave) Address register Bit 1 492.equ TWA2 = 3 ; TWI (Slave) Address register Bit 2 493.equ TWA3 = 4 ; TWI (Slave) Address register Bit 3 494.equ TWA4 = 5 ; TWI (Slave) Address register Bit 4 495.equ TWA5 = 6 ; TWI (Slave) Address register Bit 5 496.equ TWA6 = 7 ; TWI (Slave) Address register Bit 6 497 498 499; ***** AD_CONVERTER ***************** 500; ADMUX - The ADC multiplexer Selection Register 501.equ MUX0 = 0 ; Analog Channel and Gain Selection Bits 502.equ MUX1 = 1 ; Analog Channel and Gain Selection Bits 503.equ MUX2 = 2 ; Analog Channel and Gain Selection Bits 504.equ MUX3 = 3 ; Analog Channel and Gain Selection Bits 505.equ ADLAR = 5 ; Left Adjust Result 506.equ REFS0 = 6 ; Reference Selection Bit 0 507 508; ADCSRA - The ADC Control and Status register A 509.equ ADPS0 = 0 ; ADC Prescaler Select Bits 510.equ ADPS1 = 1 ; ADC Prescaler Select Bits 511.equ ADPS2 = 2 ; ADC Prescaler Select Bits 512.equ ADIE = 3 ; ADC Interrupt Enable 513.equ ADIF = 4 ; ADC Interrupt Flag 514.equ ADATE = 5 ; ADC Auto Trigger Enable 515.equ ADSC = 6 ; ADC Start Conversion 516.equ ADEN = 7 ; ADC Enable 517 518; ADCSRB - The ADC Control and Status register B 519.equ ADTS0 = 0 ; ADC Auto Trigger Source bit 0 520.equ ADTS1 = 1 ; ADC Auto Trigger Source bit 1 521.equ ADTS2 = 2 ; ADC Auto Trigger Source bit 2 522.equ ACME = 6 ; 523 524; ADCH - ADC Data Register High Byte 525.equ ADCH0 = 0 ; ADC Data Register High Byte Bit 0 526.equ ADCH1 = 1 ; ADC Data Register High Byte Bit 1 527.equ ADCH2 = 2 ; ADC Data Register High Byte Bit 2 528.equ ADCH3 = 3 ; ADC Data Register High Byte Bit 3 529.equ ADCH4 = 4 ; ADC Data Register High Byte Bit 4 530.equ ADCH5 = 5 ; ADC Data Register High Byte Bit 5 531.equ ADCH6 = 6 ; ADC Data Register High Byte Bit 6 532.equ ADCH7 = 7 ; ADC Data Register High Byte Bit 7 533 534; ADCL - ADC Data Register Low Byte 535.equ ADCL0 = 0 ; ADC Data Register Low Byte Bit 0 536.equ ADCL1 = 1 ; ADC Data Register Low Byte Bit 1 537.equ ADCL2 = 2 ; ADC Data Register Low Byte Bit 2 538.equ ADCL3 = 3 ; ADC Data Register Low Byte Bit 3 539.equ ADCL4 = 4 ; ADC Data Register Low Byte Bit 4 540.equ ADCL5 = 5 ; ADC Data Register Low Byte Bit 5 541.equ ADCL6 = 6 ; ADC Data Register Low Byte Bit 6 542.equ ADCL7 = 7 ; ADC Data Register Low Byte Bit 7 543 544; DIDR1 - Digital Input Disable Register 1 545;.equ AIN0D = 0 ; 546;.equ AIN1D = 1 ; 547 548; DIDR0 - Digital Input Disable Register 0 549.equ ADC0D = 0 ; 550.equ ADC1D = 1 ; 551.equ ADC2D = 2 ; 552.equ ADC3D = 3 ; 553.equ ADC4D = 4 ; 554.equ ADC5D = 5 ; 555.equ ADC6D = 6 ; 556.equ ADC7D = 7 ; 557 558 559; ***** EXTERNAL_INTERRUPT *********** 560; EICRA - External Interrupt Control Register 561.equ ISC00 = 0 ; External Interrupt Sense Control 0 Bit 0 562.equ ISC01 = 1 ; External Interrupt Sense Control 0 Bit 1 563.equ ISC10 = 2 ; External Interrupt Sense Control 1 Bit 0 564.equ ISC11 = 3 ; External Interrupt Sense Control 1 Bit 1 565 566; EIMSK - External Interrupt Mask Register 567.equ INT0 = 0 ; External Interrupt Request 0 Enable 568.equ INT1 = 1 ; External Interrupt Request 1 Enable 569 570; EIFR - External Interrupt Flag Register 571.equ INTF0 = 0 ; External Interrupt Flag 0 572.equ INTF1 = 1 ; External Interrupt Flag 1 573 574; PCICR - 575.equ PCIE0 = 0 ; 576.equ PCIE1 = 1 ; 577.equ PCIE2 = 2 ; 578.equ PCIE3 = 3 ; 579 580; PCMSK3 - Pin Change Mask Register 3 581.equ PCINT24 = 0 ; Pin Change Enable Mask 24 582.equ PCINT25 = 1 ; Pin Change Enable Mask 25 583.equ PCINT26 = 2 ; Pin Change Enable Mask 26 584.equ PCINT27 = 3 ; Pin Change Enable Mask 27 585 586; PCMSK2 - Pin Change Mask Register 2 587.equ PCINT16 = 0 ; Pin Change Enable Mask 16 588.equ PCINT17 = 1 ; Pin Change Enable Mask 17 589.equ PCINT18 = 2 ; Pin Change Enable Mask 18 590.equ PCINT19 = 3 ; Pin Change Enable Mask 19 591.equ PCINT20 = 4 ; Pin Change Enable Mask 20 592.equ PCINT21 = 5 ; Pin Change Enable Mask 21 593.equ PCINT22 = 6 ; Pin Change Enable Mask 22 594.equ PCINT23 = 7 ; Pin Change Enable Mask 23 595 596; PCMSK1 - Pin Change Mask Register 1 597.equ PCINT8 = 0 ; Pin Change Enable Mask 8 598.equ PCINT9 = 1 ; Pin Change Enable Mask 9 599.equ PCINT10 = 2 ; Pin Change Enable Mask 10 600.equ PCINT11 = 3 ; Pin Change Enable Mask 11 601.equ PCINT12 = 4 ; Pin Change Enable Mask 12 602.equ PCINT13 = 5 ; Pin Change Enable Mask 13 603.equ PCINT14 = 6 ; Pin Change Enable Mask 14 604.equ PCINT15 = 7 ; Pin Change Enable Mask 15 605 606; PCMSK0 - Pin Change Mask Register 0 607.equ PCINT0 = 0 ; Pin Change Enable Mask 0 608.equ PCINT1 = 1 ; Pin Change Enable Mask 1 609.equ PCINT2 = 2 ; Pin Change Enable Mask 2 610.equ PCINT3 = 3 ; Pin Change Enable Mask 3 611.equ PCINT4 = 4 ; Pin Change Enable Mask 4 612.equ PCINT5 = 5 ; Pin Change Enable Mask 5 613.equ PCINT6 = 6 ; Pin Change Enable Mask 6 614.equ PCINT7 = 7 ; Pin Change Enable Mask 7 615 616; PCIFR - Pin Change Interrupt Flag Register 617.equ PCIF0 = 0 ; Pin Change Interrupt Flag 0 618.equ PCIF1 = 1 ; Pin Change Interrupt Flag 1 619.equ PCIF2 = 2 ; Pin Change Interrupt Flag 2 620.equ PCIF3 = 3 ; Pin Change Interrupt Flag 3 621 622 623; ***** PORTC ************************ 624; PORTC - Port C Data Register 625.equ PORTC0 = 0 ; Port C Data Register bit 0 626.equ PC0 = 0 ; For compatibility 627.equ PORTC1 = 1 ; Port C Data Register bit 1 628.equ PC1 = 1 ; For compatibility 629.equ PORTC2 = 2 ; Port C Data Register bit 2 630.equ PC2 = 2 ; For compatibility 631.equ PORTC3 = 3 ; Port C Data Register bit 3 632.equ PC3 = 3 ; For compatibility 633.equ PORTC4 = 4 ; Port C Data Register bit 4 634.equ PC4 = 4 ; For compatibility 635.equ PORTC5 = 5 ; Port C Data Register bit 5 636.equ PC5 = 5 ; For compatibility 637.equ PORTC6 = 6 ; Port C Data Register bit 6 638.equ PC6 = 6 ; For compatibility 639.equ PORTC7 = 7 ; Port C Data Register bit 7 640.equ PC7 = 7 ; For compatibility 641 642; DDRC - Port C Data Direction Register 643.equ DDC0 = 0 ; Port C Data Direction Register bit 0 644.equ DDC1 = 1 ; Port C Data Direction Register bit 1 645.equ DDC2 = 2 ; Port C Data Direction Register bit 2 646.equ DDC3 = 3 ; Port C Data Direction Register bit 3 647.equ DDC4 = 4 ; Port C Data Direction Register bit 4 648.equ DDC5 = 5 ; Port C Data Direction Register bit 5 649.equ DDC6 = 6 ; Port C Data Direction Register bit 6 650.equ DDC7 = 7 ; Port C Data Direction Register bit 7 651 652; PINC - Port C Input Pins 653.equ PINC0 = 0 ; Port C Input Pins bit 0 654.equ PINC1 = 1 ; Port C Input Pins bit 1 655.equ PINC2 = 2 ; Port C Input Pins bit 2 656.equ PINC3 = 3 ; Port C Input Pins bit 3 657.equ PINC4 = 4 ; Port C Input Pins bit 4 658.equ PINC5 = 5 ; Port C Input Pins bit 5 659.equ PINC6 = 6 ; Port C Input Pins bit 6 660.equ PINC7 = 7 ; Port C Input Pins bit 7 661 662 663; ***** PORTA ************************ 664; PORTA - Port A Data Register 665.equ PORTA0 = 0 ; Port A Data Register bit 0 666.equ PA0 = 0 ; For compatibility 667.equ PORTA1 = 1 ; Port A Data Register bit 1 668.equ PA1 = 1 ; For compatibility 669.equ PORTA2 = 2 ; Port A Data Register bit 2 670.equ PA2 = 2 ; For compatibility 671.equ PORTA3 = 3 ; Port A Data Register bit 3 672.equ PA3 = 3 ; For compatibility 673 674; DDRA - Port A Data Direction Register 675.equ DDA0 = 0 ; Data Direction Register, Port A, bit 0 676.equ DDA1 = 1 ; Data Direction Register, Port A, bit 1 677.equ DDA2 = 2 ; Data Direction Register, Port A, bit 2 678.equ DDA3 = 3 ; Data Direction Register, Port A, bit 3 679 680; PINA - Port A Input Pins 681.equ PINA0 = 0 ; Input Pins, Port A bit 0 682.equ PINA1 = 1 ; Input Pins, Port A bit 1 683.equ PINA2 = 2 ; Input Pins, Port A bit 2 684.equ PINA3 = 3 ; Input Pins, Port A bit 3 685 686 687; ***** TIMER_COUNTER_0 ************** 688; TIMSK0 - Timer/Counter0 Interrupt Mask Register 689.equ TOIE0 = 0 ; Timer/Counter0 Overflow Interrupt Enable 690.equ OCIE0A = 1 ; Timer/Counter0 Output Compare Match A Interrupt Enable 691.equ OCIE0B = 2 ; Timer/Counter0 Output Compare Match B Interrupt Enable 692 693; TIFR0 - Timer/Counter0 Interrupt Flag register 694.equ TOV0 = 0 ; Timer/Counter0 Overflow Flag 695.equ OCF0A = 1 ; Timer/Counter0 Output Compare Flag 0A 696.equ OCF0B = 2 ; Timer/Counter0 Output Compare Flag 0B 697 698; TCCR0A - Timer/Counter Control Register A 699.equ CS00 = 0 ; Clock Select 700.equ CS01 = 1 ; Clock Select 701.equ CS02 = 2 ; Clock Select 702.equ CTC0 = 3 ; Clear Timer on Compare Match 703 704; TCNT0 - Timer/Counter0 705.equ TCNT0_0 = 0 ; 706.equ TCNT0_1 = 1 ; 707.equ TCNT0_2 = 2 ; 708.equ TCNT0_3 = 3 ; 709.equ TCNT0_4 = 4 ; 710.equ TCNT0_5 = 5 ; 711.equ TCNT0_6 = 6 ; 712.equ TCNT0_7 = 7 ; 713 714; OCR0A - Timer/Counter0 Output Compare Register 715.equ OCR0A_0 = 0 ; 716.equ OCR0A_1 = 1 ; 717.equ OCR0A_2 = 2 ; 718.equ OCR0A_3 = 3 ; 719.equ OCR0A_4 = 4 ; 720.equ OCR0A_5 = 5 ; 721.equ OCR0A_6 = 6 ; 722.equ OCR0A_7 = 7 ; 723 724; OCR0B - Timer/Counter0 Output Compare Register 725.equ OCR0B_0 = 0 ; 726.equ OCR0B_1 = 1 ; 727.equ OCR0B_2 = 2 ; 728.equ OCR0B_3 = 3 ; 729.equ OCR0B_4 = 4 ; 730.equ OCR0B_5 = 5 ; 731.equ OCR0B_6 = 6 ; 732.equ OCR0B_7 = 7 ; 733 734; GTCCR - General Timer/Counter Control Register 735;.equ PSRSYNC = 0 ; Prescaler Reset Timer/Counter1 and Timer/Counter0 736.equ PSR10 = PSRSYNC ; For compatibility 737;.equ TSM = 7 ; Timer/Counter Synchronization Mode 738 739 740; ***** EEPROM *********************** 741; EEARL - EEPROM Address Register Low Byte 742.equ EEAR0 = 0 ; EEPROM Read/Write Access Bit 0 743.equ EEAR1 = 1 ; EEPROM Read/Write Access Bit 1 744.equ EEAR2 = 2 ; EEPROM Read/Write Access Bit 2 745.equ EEAR3 = 3 ; EEPROM Read/Write Access Bit 3 746.equ EEAR4 = 4 ; EEPROM Read/Write Access Bit 4 747.equ EEAR5 = 5 ; EEPROM Read/Write Access Bit 5 748 749; EEDR - EEPROM Data Register 750.equ EEDR0 = 0 ; EEPROM Data Register bit 0 751.equ EEDR1 = 1 ; EEPROM Data Register bit 1 752.equ EEDR2 = 2 ; EEPROM Data Register bit 2 753.equ EEDR3 = 3 ; EEPROM Data Register bit 3 754.equ EEDR4 = 4 ; EEPROM Data Register bit 4 755.equ EEDR5 = 5 ; EEPROM Data Register bit 5 756.equ EEDR6 = 6 ; EEPROM Data Register bit 6 757.equ EEDR7 = 7 ; EEPROM Data Register bit 7 758 759; EECR - EEPROM Control Register 760.equ EERE = 0 ; EEPROM Read Enable 761.equ EEPE = 1 ; EEPROM Write Enable 762.equ EEWE = EEPE ; For compatibility 763.equ EEMPE = 2 ; EEPROM Master Write Enable 764.equ EEMWE = EEMPE ; For compatibility 765.equ EERIE = 3 ; EEPROM Ready Interrupt Enable 766.equ EEPM0 = 4 ; EEPROM Programming Mode Bit 0 767.equ EEPM1 = 5 ; EEPROM Programming Mode Bit 1 768 769 770 771; ***** LOCKSBITS ******************************************************** 772.equ LB1 = 0 ; Lockbit 773.equ LB2 = 1 ; Lockbit 774 775 776; ***** FUSES ************************************************************ 777; LOW fuse bits 778.equ CKSEL0 = 0 ; Select Clock Source 779.equ CKSEL1 = 1 ; Select Clock Source 780.equ SUT0 = 4 ; Select start-up time 781.equ SUT1 = 5 ; Select start-up time 782.equ CKOUT = 6 ; Clock output 783.equ CKDIV8 = 7 ; Divide clock by 8 784 785; HIGH fuse bits 786.equ BODLEVEL0 = 0 ; Brown-out Detector trigger level 787.equ BODLEVEL1 = 1 ; Brown-out Detector trigger level 788.equ BODLEVEL2 = 2 ; Brown-out Detector trigger level 789.equ EESAVE = 3 ; EEPROM memory is preserved through chip erase 790.equ WDTON = 4 ; Watchdog Timer Always On 791.equ SPIEN = 5 ; Enable Serial programming and Data Downloading 792.equ DWEN = 6 ; debugWIRE Enable 793.equ RSTDISBL = 7 ; External reset disable 794 795; EXTENDED fuse bits 796;.equ SELFPRGEN = 0 ; Self Programming Enable 797 798 799 800; ***** CPU REGISTER DEFINITIONS ***************************************** 801.def XH = r27 802.def XL = r26 803.def YH = r29 804.def YL = r28 805.def ZH = r31 806.def ZL = r30 807 808 809 810; ***** DATA MEMORY DECLARATIONS ***************************************** 811.equ FLASHEND = 0x07ff ; Note: Word address 812.equ IOEND = 0x00ff 813.equ SRAM_START = 0x0100 814.equ SRAM_SIZE = 256 815.equ RAMEND = 0x01ff 816.equ XRAMEND = 0x0000 817.equ E2END = 0x003f 818.equ EEPROMEND = 0x003f 819.equ EEADRBITS = 6 820#pragma AVRPART MEMORY PROG_FLASH 4096 821#pragma AVRPART MEMORY EEPROM 64 822#pragma AVRPART MEMORY INT_SRAM SIZE 256 823#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x100 824 825 826 827; ***** BOOTLOADER DECLARATIONS ****************************************** 828.equ NRWW_START_ADDR = 0x0 829.equ NRWW_STOP_ADDR = 0x7ff 830.equ RWW_START_ADDR = 0x0 831.equ RWW_STOP_ADDR = 0x0 832.equ PAGESIZE = 32 833 834 835 836; ***** INTERRUPT VECTORS ************************************************ 837.equ INT0addr = 0x0001 ; External Interrupt Request 0 838.equ INT1addr = 0x0002 ; External Interrupt Request 1 839.equ PCI0addr = 0x0003 ; Pin Change Interrupt Request 0 840.equ PCI1addr = 0x0004 ; Pin Change Interrupt Request 1 841.equ PCI2addr = 0x0005 ; Pin Change Interrupt Request 2 842.equ PCI3addr = 0x0006 ; Pin Change Interrupt Request 3 843.equ WDTaddr = 0x0007 ; Watchdog Time-out Interrupt 844.equ ICP1addr = 0x0008 ; Timer/Counter1 Capture Event 845.equ OC1Aaddr = 0x0009 ; Timer/Counter1 Compare Match A 846.equ OC1Baddr = 0x000a ; Timer/Counter1 Compare Match B 847.equ OVF1addr = 0x000b ; Timer/Counter1 Overflow 848.equ OC0Aaddr = 0x000c ; TimerCounter0 Compare Match A 849.equ OC0Baddr = 0x000d ; TimerCounter0 Compare Match B 850.equ OVF0addr = 0x000e ; Timer/Couner0 Overflow 851.equ SPIaddr = 0x000f ; SPI Serial Transfer Complete 852.equ ADCCaddr = 0x0010 ; ADC Conversion Complete 853.equ ERDYaddr = 0x0011 ; EEPROM Ready 854.equ ACIaddr = 0x0012 ; Analog Comparator 855.equ TWIaddr = 0x0013 ; Two-wire Serial Interface 856 857.equ INT_VECTORS_SIZE = 20 ; size in words 858 859#endif /* _TN48DEF_INC_ */ 860 861; ***** END OF FILE ****************************************************** 862