1;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ******************** 2;***** Created: 2011-02-09 12:04 ******* Source: ATtiny88.xml ************ 3;************************************************************************* 4;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y 5;* 6;* Number : AVR000 7;* File Name : "tn88def.inc" 8;* Title : Register/Bit Definitions for the ATtiny88 9;* Date : 2011-02-09 10;* Version : 2.35 11;* Support E-mail : avr@atmel.com 12;* Target MCU : ATtiny88 13;* 14;* DESCRIPTION 15;* When including this file in the assembly program file, all I/O register 16;* names and I/O register bit names appearing in the data book can be used. 17;* In addition, the six registers forming the three data pointers X, Y and 18;* Z have been assigned names XL - ZH. Highest RAM address for Internal 19;* SRAM is also defined 20;* 21;* The Register names are represented by their hexadecimal address. 22;* 23;* The Register Bit names are represented by their bit number (0-7). 24;* 25;* Please observe the difference in using the bit names with instructions 26;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" 27;* (skip if bit in register set/cleared). The following example illustrates 28;* this: 29;* 30;* in r16,PORTB ;read PORTB latch 31;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#) 32;* out PORTB,r16 ;output to PORTB 33;* 34;* in r16,TIFR ;read the Timer Interrupt Flag Register 35;* sbrc r16,TOV0 ;test the overflow flag (use bit#) 36;* rjmp TOV0_is_set ;jump if set 37;* ... ;otherwise do something else 38;************************************************************************* 39 40#ifndef _TN88DEF_INC_ 41#define _TN88DEF_INC_ 42 43 44#pragma partinc 0 45 46; ***** SPECIFY DEVICE *************************************************** 47.device ATtiny88 48#pragma AVRPART ADMIN PART_NAME ATtiny88 49.equ SIGNATURE_000 = 0x1e 50.equ SIGNATURE_001 = 0x93 51.equ SIGNATURE_002 = 0x11 52 53#pragma AVRPART CORE CORE_VERSION V2 54#pragma AVRPART CORE NEW_INSTRUCTIONS lpm rd,z+ 55 56 57; ***** I/O REGISTER DEFINITIONS ***************************************** 58; NOTE: 59; Definitions marked "MEMORY MAPPED"are extended I/O ports 60; and cannot be used with IN/OUT instructions 61.equ TWHSR = 0xbe ; MEMORY MAPPED 62.equ TWAMR = 0xbd ; MEMORY MAPPED 63.equ TWCR = 0xbc ; MEMORY MAPPED 64.equ TWDR = 0xbb ; MEMORY MAPPED 65.equ TWAR = 0xba ; MEMORY MAPPED 66.equ TWSR = 0xb9 ; MEMORY MAPPED 67.equ TWBR = 0xb8 ; MEMORY MAPPED 68.equ OCR1BL = 0x8a ; MEMORY MAPPED 69.equ OCR1BH = 0x8b ; MEMORY MAPPED 70.equ OCR1AL = 0x88 ; MEMORY MAPPED 71.equ OCR1AH = 0x89 ; MEMORY MAPPED 72.equ ICR1L = 0x86 ; MEMORY MAPPED 73.equ ICR1H = 0x87 ; MEMORY MAPPED 74.equ TCNT1L = 0x84 ; MEMORY MAPPED 75.equ TCNT1H = 0x85 ; MEMORY MAPPED 76.equ TCCR1C = 0x82 ; MEMORY MAPPED 77.equ TCCR1B = 0x81 ; MEMORY MAPPED 78.equ TCCR1A = 0x80 ; MEMORY MAPPED 79.equ DIDR1 = 0x7f ; MEMORY MAPPED 80.equ DIDR0 = 0x7e ; MEMORY MAPPED 81.equ ADMUX = 0x7c ; MEMORY MAPPED 82.equ ADCSRB = 0x7b ; MEMORY MAPPED 83.equ ADCSRA = 0x7a ; MEMORY MAPPED 84.equ ADCH = 0x79 ; MEMORY MAPPED 85.equ ADCL = 0x78 ; MEMORY MAPPED 86.equ TIMSK1 = 0x6f ; MEMORY MAPPED 87.equ TIMSK0 = 0x6e ; MEMORY MAPPED 88.equ PCMSK2 = 0x6d ; MEMORY MAPPED 89.equ PCMSK1 = 0x6c ; MEMORY MAPPED 90.equ PCMSK0 = 0x6b ; MEMORY MAPPED 91.equ PCMSK3 = 0x6a ; MEMORY MAPPED 92.equ EICRA = 0x69 ; MEMORY MAPPED 93.equ PCICR = 0x68 ; MEMORY MAPPED 94.equ OSCCAL = 0x66 ; MEMORY MAPPED 95.equ PRR = 0x64 ; MEMORY MAPPED 96.equ CLKPR = 0x61 ; MEMORY MAPPED 97.equ WDTCSR = 0x60 ; MEMORY MAPPED 98.equ SREG = 0x3f 99.equ SPH = 0x3e 100.equ SPL = 0x3d 101.equ SPMCSR = 0x37 102.equ MCUCR = 0x35 103.equ MCUSR = 0x34 104.equ SMCR = 0x33 105.equ ACSR = 0x30 106.equ SPDR = 0x2e 107.equ SPSR = 0x2d 108.equ SPCR = 0x2c 109.equ GPIOR2 = 0x2b 110.equ GPIOR1 = 0x2a 111.equ OCR0B = 0x28 112.equ OCR0A = 0x27 113.equ TCNT0 = 0x26 114.equ TCCR0A = 0x25 115.equ GTCCR = 0x23 116.equ EEARL = 0x21 117.equ EEDR = 0x20 118.equ EECR = 0x1f 119.equ GPIOR0 = 0x1e 120.equ EIMSK = 0x1d 121.equ EIFR = 0x1c 122.equ PCIFR = 0x1b 123.equ TIFR1 = 0x16 124.equ TIFR0 = 0x15 125.equ PORTCR = 0x12 126.equ PORTA = 0x0e 127.equ DDRA = 0x0d 128.equ PINA = 0x0c 129.equ PORTD = 0x0b 130.equ DDRD = 0x0a 131.equ PIND = 0x09 132.equ PORTC = 0x08 133.equ DDRC = 0x07 134.equ PINC = 0x06 135.equ PORTB = 0x05 136.equ DDRB = 0x04 137.equ PINB = 0x03 138 139 140; ***** BIT DEFINITIONS ************************************************** 141 142; ***** TIMER_COUNTER_1 ************** 143; TIMSK1 - Timer/Counter Interrupt Mask Register 144.equ TOIE1 = 0 ; Timer/Counter1 Overflow Interrupt Enable 145.equ OCIE1A = 1 ; Timer/Counter1 Output CompareA Match Interrupt Enable 146.equ OCIE1B = 2 ; Timer/Counter1 Output CompareB Match Interrupt Enable 147.equ ICIE1 = 5 ; Timer/Counter1 Input Capture Interrupt Enable 148 149; TIFR1 - Timer/Counter Interrupt Flag register 150.equ TOV1 = 0 ; Timer/Counter1 Overflow Flag 151.equ OCF1A = 1 ; Output Compare Flag 1A 152.equ OCF1B = 2 ; Output Compare Flag 1B 153.equ ICF1 = 5 ; Input Capture Flag 1 154 155; TCCR1A - Timer/Counter1 Control Register A 156.equ WGM10 = 0 ; Waveform Generation Mode 157.equ WGM11 = 1 ; Waveform Generation Mode 158.equ COM1B0 = 4 ; Compare Output Mode 1B, bit 0 159.equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1 160.equ COM1A0 = 6 ; Comparet Ouput Mode 1A, bit 0 161.equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1 162 163; TCCR1B - Timer/Counter1 Control Register B 164.equ CS10 = 0 ; Prescaler source of Timer/Counter 1 165.equ CS11 = 1 ; Prescaler source of Timer/Counter 1 166.equ CS12 = 2 ; Prescaler source of Timer/Counter 1 167.equ WGM12 = 3 ; Waveform Generation Mode 168.equ WGM13 = 4 ; Waveform Generation Mode 169.equ ICES1 = 6 ; Input Capture 1 Edge Select 170.equ ICNC1 = 7 ; Input Capture 1 Noise Canceler 171 172; TCCR1C - Timer/Counter1 Control Register C 173.equ FOC1B = 6 ; 174.equ FOC1A = 7 ; 175 176; GTCCR - General Timer/Counter Control Register 177.equ PSRSYNC = 0 ; Prescaler Reset Timer/Counter1 and Timer/Counter0 178.equ TSM = 7 ; Timer/Counter Synchronization Mode 179 180 181; ***** ANALOG_COMPARATOR ************ 182; ACSR - Analog Comparator Control And Status Register 183.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0 184.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1 185.equ ACIC = 2 ; Analog Comparator Input Capture Enable 186.equ ACIE = 3 ; Analog Comparator Interrupt Enable 187.equ ACI = 4 ; Analog Comparator Interrupt Flag 188.equ ACO = 5 ; Analog Compare Output 189.equ ACBG = 6 ; Analog Comparator Bandgap Select 190.equ ACD = 7 ; Analog Comparator Disable 191 192; DIDR1 - Digital Input Disable Register 1 193.equ AIN0D = 0 ; AIN0 Digital Input Disable 194.equ AIN1D = 1 ; AIN1 Digital Input Disable 195 196 197; ***** PORTB ************************ 198; PORTB - Port B Data Register 199.equ PORTB0 = 0 ; Port B Data Register bit 0 200.equ PB0 = 0 ; For compatibility 201.equ PORTB1 = 1 ; Port B Data Register bit 1 202.equ PB1 = 1 ; For compatibility 203.equ PORTB2 = 2 ; Port B Data Register bit 2 204.equ PB2 = 2 ; For compatibility 205.equ PORTB3 = 3 ; Port B Data Register bit 3 206.equ PB3 = 3 ; For compatibility 207.equ PORTB4 = 4 ; Port B Data Register bit 4 208.equ PB4 = 4 ; For compatibility 209.equ PORTB5 = 5 ; Port B Data Register bit 5 210.equ PB5 = 5 ; For compatibility 211.equ PORTB6 = 6 ; Port B Data Register bit 6 212.equ PB6 = 6 ; For compatibility 213.equ PORTB7 = 7 ; Port B Data Register bit 7 214.equ PB7 = 7 ; For compatibility 215 216; DDRB - Port B Data Direction Register 217.equ DDB0 = 0 ; Port B Data Direction Register bit 0 218.equ DDB1 = 1 ; Port B Data Direction Register bit 1 219.equ DDB2 = 2 ; Port B Data Direction Register bit 2 220.equ DDB3 = 3 ; Port B Data Direction Register bit 3 221.equ DDB4 = 4 ; Port B Data Direction Register bit 4 222.equ DDB5 = 5 ; Port B Data Direction Register bit 5 223.equ DDB6 = 6 ; Port B Data Direction Register bit 6 224.equ DDB7 = 7 ; Port B Data Direction Register bit 7 225 226; PINB - Port B Input Pins 227.equ PINB0 = 0 ; Port B Input Pins bit 0 228.equ PINB1 = 1 ; Port B Input Pins bit 1 229.equ PINB2 = 2 ; Port B Input Pins bit 2 230.equ PINB3 = 3 ; Port B Input Pins bit 3 231.equ PINB4 = 4 ; Port B Input Pins bit 4 232.equ PINB5 = 5 ; Port B Input Pins bit 5 233.equ PINB6 = 6 ; Port B Input Pins bit 6 234.equ PINB7 = 7 ; Port B Input Pins bit 7 235 236 237; ***** PORTD ************************ 238; PORTD - Port D Data Register 239.equ PORTD0 = 0 ; Port D Data Register bit 0 240.equ PD0 = 0 ; For compatibility 241.equ PORTD1 = 1 ; Port D Data Register bit 1 242.equ PD1 = 1 ; For compatibility 243.equ PORTD2 = 2 ; Port D Data Register bit 2 244.equ PD2 = 2 ; For compatibility 245.equ PORTD3 = 3 ; Port D Data Register bit 3 246.equ PD3 = 3 ; For compatibility 247.equ PORTD4 = 4 ; Port D Data Register bit 4 248.equ PD4 = 4 ; For compatibility 249.equ PORTD5 = 5 ; Port D Data Register bit 5 250.equ PD5 = 5 ; For compatibility 251.equ PORTD6 = 6 ; Port D Data Register bit 6 252.equ PD6 = 6 ; For compatibility 253.equ PORTD7 = 7 ; Port D Data Register bit 7 254.equ PD7 = 7 ; For compatibility 255 256; DDRD - Port D Data Direction Register 257.equ DDD0 = 0 ; Port D Data Direction Register bit 0 258.equ DDD1 = 1 ; Port D Data Direction Register bit 1 259.equ DDD2 = 2 ; Port D Data Direction Register bit 2 260.equ DDD3 = 3 ; Port D Data Direction Register bit 3 261.equ DDD4 = 4 ; Port D Data Direction Register bit 4 262.equ DDD5 = 5 ; Port D Data Direction Register bit 5 263.equ DDD6 = 6 ; Port D Data Direction Register bit 6 264.equ DDD7 = 7 ; Port D Data Direction Register bit 7 265 266; PIND - Port D Input Pins 267.equ PIND0 = 0 ; Port D Input Pins bit 0 268.equ PIND1 = 1 ; Port D Input Pins bit 1 269.equ PIND2 = 2 ; Port D Input Pins bit 2 270.equ PIND3 = 3 ; Port D Input Pins bit 3 271.equ PIND4 = 4 ; Port D Input Pins bit 4 272.equ PIND5 = 5 ; Port D Input Pins bit 5 273.equ PIND6 = 6 ; Port D Input Pins bit 6 274.equ PIND7 = 7 ; Port D Input Pins bit 7 275 276 277; ***** SPI ************************** 278; SPDR - SPI Data Register 279.equ SPDR0 = 0 ; SPI Data Register bit 0 280.equ SPDR1 = 1 ; SPI Data Register bit 1 281.equ SPDR2 = 2 ; SPI Data Register bit 2 282.equ SPDR3 = 3 ; SPI Data Register bit 3 283.equ SPDR4 = 4 ; SPI Data Register bit 4 284.equ SPDR5 = 5 ; SPI Data Register bit 5 285.equ SPDR6 = 6 ; SPI Data Register bit 6 286.equ SPDR7 = 7 ; SPI Data Register bit 7 287 288; SPSR - SPI Status Register 289.equ SPI2X = 0 ; Double SPI Speed Bit 290.equ WCOL = 6 ; Write Collision Flag 291.equ SPIF = 7 ; SPI Interrupt Flag 292 293; SPCR - SPI Control Register 294.equ SPR0 = 0 ; SPI Clock Rate Select 0 295.equ SPR1 = 1 ; SPI Clock Rate Select 1 296.equ CPHA = 2 ; Clock Phase 297.equ CPOL = 3 ; Clock polarity 298.equ MSTR = 4 ; Master/Slave Select 299.equ DORD = 5 ; Data Order 300.equ SPE = 6 ; SPI Enable 301.equ SPIE = 7 ; SPI Interrupt Enable 302 303 304; ***** WATCHDOG ********************* 305; WDTCSR - Watchdog Timer Control Register 306.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0 307.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1 308.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2 309.equ WDE = 3 ; Watch Dog Enable 310.equ WDCE = 4 ; Watchdog Change Enable 311.equ WDP3 = 5 ; Watchdog Timer Prescaler Bit 3 312.equ WDIE = 6 ; Watchdog Timeout Interrupt Enable 313.equ WDIF = 7 ; Watchdog Timeout Interrupt Flag 314 315 316; ***** TWI ************************** 317; TWHSR - TWHSR 318.equ TWHS = 0 ; 319 320; TWAMR - TWI (Slave) Address Mask Register 321.equ TWAM0 = 1 ; 322.equ TWAMR0 = TWAM0 ; For compatibility 323.equ TWAM1 = 2 ; 324.equ TWAMR1 = TWAM1 ; For compatibility 325.equ TWAM2 = 3 ; 326.equ TWAMR2 = TWAM2 ; For compatibility 327.equ TWAM3 = 4 ; 328.equ TWAMR3 = TWAM3 ; For compatibility 329.equ TWAM4 = 5 ; 330.equ TWAMR4 = TWAM4 ; For compatibility 331.equ TWAM5 = 6 ; 332.equ TWAMR5 = TWAM5 ; For compatibility 333.equ TWAM6 = 7 ; 334.equ TWAMR6 = TWAM6 ; For compatibility 335 336; TWBR - TWI Bit Rate register 337.equ TWBR0 = 0 ; 338.equ TWBR1 = 1 ; 339.equ TWBR2 = 2 ; 340.equ TWBR3 = 3 ; 341.equ TWBR4 = 4 ; 342.equ TWBR5 = 5 ; 343.equ TWBR6 = 6 ; 344.equ TWBR7 = 7 ; 345 346; TWCR - TWI Control Register 347.equ TWIE = 0 ; TWI Interrupt Enable 348.equ TWEN = 2 ; TWI Enable Bit 349.equ TWWC = 3 ; TWI Write Collition Flag 350.equ TWSTO = 4 ; TWI Stop Condition Bit 351.equ TWSTA = 5 ; TWI Start Condition Bit 352.equ TWEA = 6 ; TWI Enable Acknowledge Bit 353.equ TWINT = 7 ; TWI Interrupt Flag 354 355; TWSR - TWI Status Register 356.equ TWPS0 = 0 ; TWI Prescaler 357.equ TWPS1 = 1 ; TWI Prescaler 358.equ TWS3 = 3 ; TWI Status 359.equ TWS4 = 4 ; TWI Status 360.equ TWS5 = 5 ; TWI Status 361.equ TWS6 = 6 ; TWI Status 362.equ TWS7 = 7 ; TWI Status 363 364; TWDR - TWI Data register 365.equ TWD0 = 0 ; TWI Data Register Bit 0 366.equ TWD1 = 1 ; TWI Data Register Bit 1 367.equ TWD2 = 2 ; TWI Data Register Bit 2 368.equ TWD3 = 3 ; TWI Data Register Bit 3 369.equ TWD4 = 4 ; TWI Data Register Bit 4 370.equ TWD5 = 5 ; TWI Data Register Bit 5 371.equ TWD6 = 6 ; TWI Data Register Bit 6 372.equ TWD7 = 7 ; TWI Data Register Bit 7 373 374; TWAR - TWI (Slave) Address register 375.equ TWGCE = 0 ; TWI General Call Recognition Enable Bit 376.equ TWA0 = 1 ; TWI (Slave) Address register Bit 0 377.equ TWA1 = 2 ; TWI (Slave) Address register Bit 1 378.equ TWA2 = 3 ; TWI (Slave) Address register Bit 2 379.equ TWA3 = 4 ; TWI (Slave) Address register Bit 3 380.equ TWA4 = 5 ; TWI (Slave) Address register Bit 4 381.equ TWA5 = 6 ; TWI (Slave) Address register Bit 5 382.equ TWA6 = 7 ; TWI (Slave) Address register Bit 6 383 384 385; ***** AD_CONVERTER ***************** 386; ADMUX - The ADC multiplexer Selection Register 387.equ MUX0 = 0 ; Analog Channel and Gain Selection Bits 388.equ MUX1 = 1 ; Analog Channel and Gain Selection Bits 389.equ MUX2 = 2 ; Analog Channel and Gain Selection Bits 390.equ MUX3 = 3 ; Analog Channel and Gain Selection Bits 391.equ ADLAR = 5 ; Left Adjust Result 392.equ REFS0 = 6 ; Reference Selection Bit 0 393 394; ADCSRA - The ADC Control and Status register A 395.equ ADPS0 = 0 ; ADC Prescaler Select Bits 396.equ ADPS1 = 1 ; ADC Prescaler Select Bits 397.equ ADPS2 = 2 ; ADC Prescaler Select Bits 398.equ ADIE = 3 ; ADC Interrupt Enable 399.equ ADIF = 4 ; ADC Interrupt Flag 400.equ ADATE = 5 ; ADC Auto Trigger Enable 401.equ ADSC = 6 ; ADC Start Conversion 402.equ ADEN = 7 ; ADC Enable 403 404; ADCSRB - The ADC Control and Status register B 405.equ ADTS0 = 0 ; ADC Auto Trigger Source bit 0 406.equ ADTS1 = 1 ; ADC Auto Trigger Source bit 1 407.equ ADTS2 = 2 ; ADC Auto Trigger Source bit 2 408.equ ACME = 6 ; 409 410; ADCH - ADC Data Register High Byte 411.equ ADCH0 = 0 ; ADC Data Register High Byte Bit 0 412.equ ADCH1 = 1 ; ADC Data Register High Byte Bit 1 413.equ ADCH2 = 2 ; ADC Data Register High Byte Bit 2 414.equ ADCH3 = 3 ; ADC Data Register High Byte Bit 3 415.equ ADCH4 = 4 ; ADC Data Register High Byte Bit 4 416.equ ADCH5 = 5 ; ADC Data Register High Byte Bit 5 417.equ ADCH6 = 6 ; ADC Data Register High Byte Bit 6 418.equ ADCH7 = 7 ; ADC Data Register High Byte Bit 7 419 420; ADCL - ADC Data Register Low Byte 421.equ ADCL0 = 0 ; ADC Data Register Low Byte Bit 0 422.equ ADCL1 = 1 ; ADC Data Register Low Byte Bit 1 423.equ ADCL2 = 2 ; ADC Data Register Low Byte Bit 2 424.equ ADCL3 = 3 ; ADC Data Register Low Byte Bit 3 425.equ ADCL4 = 4 ; ADC Data Register Low Byte Bit 4 426.equ ADCL5 = 5 ; ADC Data Register Low Byte Bit 5 427.equ ADCL6 = 6 ; ADC Data Register Low Byte Bit 6 428.equ ADCL7 = 7 ; ADC Data Register Low Byte Bit 7 429 430; DIDR1 - Digital Input Disable Register 1 431;.equ AIN0D = 0 ; 432;.equ AIN1D = 1 ; 433 434; DIDR0 - Digital Input Disable Register 0 435.equ ADC0D = 0 ; 436.equ ADC1D = 1 ; 437.equ ADC2D = 2 ; 438.equ ADC3D = 3 ; 439.equ ADC4D = 4 ; 440.equ ADC5D = 5 ; 441.equ ADC6D = 6 ; 442.equ ADC7D = 7 ; 443 444 445; ***** EXTERNAL_INTERRUPT *********** 446; EICRA - External Interrupt Control Register 447.equ ISC00 = 0 ; External Interrupt Sense Control 0 Bit 0 448.equ ISC01 = 1 ; External Interrupt Sense Control 0 Bit 1 449.equ ISC10 = 2 ; External Interrupt Sense Control 1 Bit 0 450.equ ISC11 = 3 ; External Interrupt Sense Control 1 Bit 1 451 452; EIMSK - External Interrupt Mask Register 453.equ INT0 = 0 ; External Interrupt Request 0 Enable 454.equ INT1 = 1 ; External Interrupt Request 1 Enable 455 456; EIFR - External Interrupt Flag Register 457.equ INTF0 = 0 ; External Interrupt Flag 0 458.equ INTF1 = 1 ; External Interrupt Flag 1 459 460; PCICR - 461.equ PCIE0 = 0 ; 462.equ PCIE1 = 1 ; 463.equ PCIE2 = 2 ; 464.equ PCIE3 = 3 ; 465 466; PCMSK3 - Pin Change Mask Register 3 467.equ PCINT24 = 0 ; Pin Change Enable Mask 24 468.equ PCINT25 = 1 ; Pin Change Enable Mask 25 469.equ PCINT26 = 2 ; Pin Change Enable Mask 26 470.equ PCINT27 = 3 ; Pin Change Enable Mask 27 471 472; PCMSK2 - Pin Change Mask Register 2 473.equ PCINT16 = 0 ; Pin Change Enable Mask 16 474.equ PCINT17 = 1 ; Pin Change Enable Mask 17 475.equ PCINT18 = 2 ; Pin Change Enable Mask 18 476.equ PCINT19 = 3 ; Pin Change Enable Mask 19 477.equ PCINT20 = 4 ; Pin Change Enable Mask 20 478.equ PCINT21 = 5 ; Pin Change Enable Mask 21 479.equ PCINT22 = 6 ; Pin Change Enable Mask 22 480.equ PCINT23 = 7 ; Pin Change Enable Mask 23 481 482; PCMSK1 - Pin Change Mask Register 1 483.equ PCINT8 = 0 ; Pin Change Enable Mask 8 484.equ PCINT9 = 1 ; Pin Change Enable Mask 9 485.equ PCINT10 = 2 ; Pin Change Enable Mask 10 486.equ PCINT11 = 3 ; Pin Change Enable Mask 11 487.equ PCINT12 = 4 ; Pin Change Enable Mask 12 488.equ PCINT13 = 5 ; Pin Change Enable Mask 13 489.equ PCINT14 = 6 ; Pin Change Enable Mask 14 490.equ PCINT15 = 7 ; Pin Change Enable Mask 15 491 492; PCMSK0 - Pin Change Mask Register 0 493.equ PCINT0 = 0 ; Pin Change Enable Mask 0 494.equ PCINT1 = 1 ; Pin Change Enable Mask 1 495.equ PCINT2 = 2 ; Pin Change Enable Mask 2 496.equ PCINT3 = 3 ; Pin Change Enable Mask 3 497.equ PCINT4 = 4 ; Pin Change Enable Mask 4 498.equ PCINT5 = 5 ; Pin Change Enable Mask 5 499.equ PCINT6 = 6 ; Pin Change Enable Mask 6 500.equ PCINT7 = 7 ; Pin Change Enable Mask 7 501 502; PCIFR - Pin Change Interrupt Flag Register 503.equ PCIF0 = 0 ; Pin Change Interrupt Flag 0 504.equ PCIF1 = 1 ; Pin Change Interrupt Flag 1 505.equ PCIF2 = 2 ; Pin Change Interrupt Flag 2 506.equ PCIF3 = 3 ; Pin Change Interrupt Flag 3 507 508 509; ***** PORTC ************************ 510; PORTC - Port C Data Register 511.equ PORTC0 = 0 ; Port C Data Register bit 0 512.equ PC0 = 0 ; For compatibility 513.equ PORTC1 = 1 ; Port C Data Register bit 1 514.equ PC1 = 1 ; For compatibility 515.equ PORTC2 = 2 ; Port C Data Register bit 2 516.equ PC2 = 2 ; For compatibility 517.equ PORTC3 = 3 ; Port C Data Register bit 3 518.equ PC3 = 3 ; For compatibility 519.equ PORTC4 = 4 ; Port C Data Register bit 4 520.equ PC4 = 4 ; For compatibility 521.equ PORTC5 = 5 ; Port C Data Register bit 5 522.equ PC5 = 5 ; For compatibility 523.equ PORTC6 = 6 ; Port C Data Register bit 6 524.equ PC6 = 6 ; For compatibility 525.equ PORTC7 = 7 ; Port C Data Register bit 7 526.equ PC7 = 7 ; For compatibility 527 528; DDRC - Port C Data Direction Register 529.equ DDC0 = 0 ; Port C Data Direction Register bit 0 530.equ DDC1 = 1 ; Port C Data Direction Register bit 1 531.equ DDC2 = 2 ; Port C Data Direction Register bit 2 532.equ DDC3 = 3 ; Port C Data Direction Register bit 3 533.equ DDC4 = 4 ; Port C Data Direction Register bit 4 534.equ DDC5 = 5 ; Port C Data Direction Register bit 5 535.equ DDC6 = 6 ; Port C Data Direction Register bit 6 536.equ DDC7 = 7 ; Port C Data Direction Register bit 7 537 538; PINC - Port C Input Pins 539.equ PINC0 = 0 ; Port C Input Pins bit 0 540.equ PINC1 = 1 ; Port C Input Pins bit 1 541.equ PINC2 = 2 ; Port C Input Pins bit 2 542.equ PINC3 = 3 ; Port C Input Pins bit 3 543.equ PINC4 = 4 ; Port C Input Pins bit 4 544.equ PINC5 = 5 ; Port C Input Pins bit 5 545.equ PINC6 = 6 ; Port C Input Pins bit 6 546.equ PINC7 = 7 ; Port C Input Pins bit 7 547 548 549; ***** PORTA ************************ 550; PORTA - Port A Data Register 551.equ PORTA0 = 0 ; Port A Data Register bit 0 552.equ PA0 = 0 ; For compatibility 553.equ PORTA1 = 1 ; Port A Data Register bit 1 554.equ PA1 = 1 ; For compatibility 555.equ PORTA2 = 2 ; Port A Data Register bit 2 556.equ PA2 = 2 ; For compatibility 557.equ PORTA3 = 3 ; Port A Data Register bit 3 558.equ PA3 = 3 ; For compatibility 559 560; DDRA - Port A Data Direction Register 561.equ DDA0 = 0 ; Data Direction Register, Port A, bit 0 562.equ DDA1 = 1 ; Data Direction Register, Port A, bit 1 563.equ DDA2 = 2 ; Data Direction Register, Port A, bit 2 564.equ DDA3 = 3 ; Data Direction Register, Port A, bit 3 565 566; PINA - Port A Input Pins 567.equ PINA0 = 0 ; Input Pins, Port A bit 0 568.equ PINA1 = 1 ; Input Pins, Port A bit 1 569.equ PINA2 = 2 ; Input Pins, Port A bit 2 570.equ PINA3 = 3 ; Input Pins, Port A bit 3 571 572 573; ***** TIMER_COUNTER_0 ************** 574; TIMSK0 - Timer/Counter0 Interrupt Mask Register 575.equ TOIE0 = 0 ; Timer/Counter0 Overflow Interrupt Enable 576.equ OCIE0A = 1 ; Timer/Counter0 Output Compare Match A Interrupt Enable 577.equ OCIE0B = 2 ; Timer/Counter0 Output Compare Match B Interrupt Enable 578 579; TIFR0 - Timer/Counter0 Interrupt Flag register 580.equ TOV0 = 0 ; Timer/Counter0 Overflow Flag 581.equ OCF0A = 1 ; Timer/Counter0 Output Compare Flag 0A 582.equ OCF0B = 2 ; Timer/Counter0 Output Compare Flag 0B 583 584; TCCR0A - Timer/Counter Control Register A 585.equ CS00 = 0 ; Clock Select 586.equ CS01 = 1 ; Clock Select 587.equ CS02 = 2 ; Clock Select 588.equ CTC0 = 3 ; Clear Timer on Compare Match 589 590; TCNT0 - Timer/Counter0 591.equ TCNT0_0 = 0 ; 592.equ TCNT0_1 = 1 ; 593.equ TCNT0_2 = 2 ; 594.equ TCNT0_3 = 3 ; 595.equ TCNT0_4 = 4 ; 596.equ TCNT0_5 = 5 ; 597.equ TCNT0_6 = 6 ; 598.equ TCNT0_7 = 7 ; 599 600; OCR0A - Timer/Counter0 Output Compare Register 601.equ OCR0A_0 = 0 ; 602.equ OCR0A_1 = 1 ; 603.equ OCR0A_2 = 2 ; 604.equ OCR0A_3 = 3 ; 605.equ OCR0A_4 = 4 ; 606.equ OCR0A_5 = 5 ; 607.equ OCR0A_6 = 6 ; 608.equ OCR0A_7 = 7 ; 609 610; OCR0B - Timer/Counter0 Output Compare Register 611.equ OCR0B_0 = 0 ; 612.equ OCR0B_1 = 1 ; 613.equ OCR0B_2 = 2 ; 614.equ OCR0B_3 = 3 ; 615.equ OCR0B_4 = 4 ; 616.equ OCR0B_5 = 5 ; 617.equ OCR0B_6 = 6 ; 618.equ OCR0B_7 = 7 ; 619 620; GTCCR - General Timer/Counter Control Register 621;.equ PSRSYNC = 0 ; Prescaler Reset Timer/Counter1 and Timer/Counter0 622.equ PSR10 = PSRSYNC ; For compatibility 623;.equ TSM = 7 ; Timer/Counter Synchronization Mode 624 625 626; ***** CPU ************************** 627; SREG - Status Register 628.equ SREG_C = 0 ; Carry Flag 629.equ SREG_Z = 1 ; Zero Flag 630.equ SREG_N = 2 ; Negative Flag 631.equ SREG_V = 3 ; Two's Complement Overflow Flag 632.equ SREG_S = 4 ; Sign Bit 633.equ SREG_H = 5 ; Half Carry Flag 634.equ SREG_T = 6 ; Bit Copy Storage 635.equ SREG_I = 7 ; Global Interrupt Enable 636 637; SPH - Stack Pointe High 638.equ SP8 = 0 ; Stack pointer bit 8 639.equ SP9 = 1 ; Stack pointer bit 9 640 641; SPL - Stack Pointe Low 642.equ SP0 = 0 ; Stack pointer bit 0 643.equ SP1 = 1 ; Stack pointer bit 1 644.equ SP2 = 2 ; Stack pointer bit 2 645.equ SP3 = 3 ; Stack pointer bit 3 646.equ SP4 = 4 ; Stack pointer bit 4 647.equ SP5 = 5 ; Stack pointer bit 5 648.equ SP6 = 6 ; Stack pointer bit 6 649.equ SP7 = 7 ; Stack pointer bit 7 650 651; OSCCAL - Oscillator Calibration Value 652.equ CAL0 = 0 ; Oscillator Calibration Value Bit0 653.equ CAL1 = 1 ; Oscillator Calibration Value Bit1 654.equ CAL2 = 2 ; Oscillator Calibration Value Bit2 655.equ CAL3 = 3 ; Oscillator Calibration Value Bit3 656.equ CAL4 = 4 ; Oscillator Calibration Value Bit4 657.equ CAL5 = 5 ; Oscillator Calibration Value Bit5 658.equ CAL6 = 6 ; Oscillator Calibration Value Bit6 659.equ CAL7 = 7 ; Oscillator Calibration Value Bit7 660 661; CLKPR - Clock Prescale Register 662.equ CLKPS0 = 0 ; Clock Prescaler Select Bit 0 663.equ CLKPS1 = 1 ; Clock Prescaler Select Bit 1 664.equ CLKPS2 = 2 ; Clock Prescaler Select Bit 2 665.equ CLKPS3 = 3 ; Clock Prescaler Select Bit 3 666.equ CLKPCE = 7 ; Clock Prescaler Change Enable 667 668; SPMCSR - Store Program Memory Control Register 669.equ SELFPRGEN = 0 ; Self Programming Enable 670.equ PGERS = 1 ; Page Erase 671.equ PGWRT = 2 ; Page Write 672.equ RFLB = 3 ; Read Fuse and Lock Bits 673.equ CTPB = 4 ; Clear Temporary Page Buffer 674.equ RWWSB = 6 ; Read-While-Write Section Busy 675 676; MCUCR - MCU Control Register 677.equ PUD = 4 ; 678.equ BODSE = 5 ; BOD Sleep Enable 679.equ BODS = 6 ; BOD Sleep 680 681; MCUSR - MCU Status Register 682.equ PORF = 0 ; Power-on reset flag 683.equ EXTRF = 1 ; External Reset Flag 684.equ EXTREF = EXTRF ; For compatibility 685.equ BORF = 2 ; Brown-out Reset Flag 686.equ WDRF = 3 ; Watchdog Reset Flag 687 688; SMCR - 689.equ SE = 0 ; 690.equ SM0 = 1 ; 691.equ SM1 = 2 ; 692 693; GPIOR2 - General Purpose I/O Register 2 694.equ GPIOR20 = 0 ; 695.equ GPIOR21 = 1 ; 696.equ GPIOR22 = 2 ; 697.equ GPIOR23 = 3 ; 698.equ GPIOR24 = 4 ; 699.equ GPIOR25 = 5 ; 700.equ GPIOR26 = 6 ; 701.equ GPIOR27 = 7 ; 702 703; GPIOR1 - General Purpose I/O Register 1 704.equ GPIOR10 = 0 ; 705.equ GPIOR11 = 1 ; 706.equ GPIOR12 = 2 ; 707.equ GPIOR13 = 3 ; 708.equ GPIOR14 = 4 ; 709.equ GPIOR15 = 5 ; 710.equ GPIOR16 = 6 ; 711.equ GPIOR17 = 7 ; 712 713; GPIOR0 - General Purpose I/O Register 0 714.equ GPIOR00 = 0 ; 715.equ GPIOR01 = 1 ; 716.equ GPIOR02 = 2 ; 717.equ GPIOR03 = 3 ; 718.equ GPIOR04 = 4 ; 719.equ GPIOR05 = 5 ; 720.equ GPIOR06 = 6 ; 721.equ GPIOR07 = 7 ; 722 723; PRR - Power Reduction Register 724.equ PRADC = 0 ; Power Reduction ADC 725.equ PRSPI = 2 ; Power Reduction Serial Peripheral Interface 726.equ PRTIM1 = 3 ; Power Reduction Timer/Counter1 727.equ PRTIM0 = 5 ; Power Reduction Timer/Counter0 728.equ PRTWI = 7 ; Power Reduction TWI 729 730; PORTCR - Port Configuration Register 731.equ PUDA = 0 ; 732.equ PUDB = 1 ; 733.equ PUDC = 2 ; 734.equ PUDD = 3 ; 735.equ BBMA = 4 ; 736.equ BBMB = 5 ; 737.equ BBMC = 6 ; 738.equ BBMD = 7 ; 739 740 741; ***** EEPROM *********************** 742; EEARL - EEPROM Address Register Low Byte 743.equ EEAR0 = 0 ; EEPROM Read/Write Access Bit 0 744.equ EEAR1 = 1 ; EEPROM Read/Write Access Bit 1 745.equ EEAR2 = 2 ; EEPROM Read/Write Access Bit 2 746.equ EEAR3 = 3 ; EEPROM Read/Write Access Bit 3 747.equ EEAR4 = 4 ; EEPROM Read/Write Access Bit 4 748.equ EEAR5 = 5 ; EEPROM Read/Write Access Bit 5 749 750; EEDR - EEPROM Data Register 751.equ EEDR0 = 0 ; EEPROM Data Register bit 0 752.equ EEDR1 = 1 ; EEPROM Data Register bit 1 753.equ EEDR2 = 2 ; EEPROM Data Register bit 2 754.equ EEDR3 = 3 ; EEPROM Data Register bit 3 755.equ EEDR4 = 4 ; EEPROM Data Register bit 4 756.equ EEDR5 = 5 ; EEPROM Data Register bit 5 757.equ EEDR6 = 6 ; EEPROM Data Register bit 6 758.equ EEDR7 = 7 ; EEPROM Data Register bit 7 759 760; EECR - EEPROM Control Register 761.equ EERE = 0 ; EEPROM Read Enable 762.equ EEPE = 1 ; EEPROM Write Enable 763.equ EEWE = EEPE ; For compatibility 764.equ EEMPE = 2 ; EEPROM Master Write Enable 765.equ EEMWE = EEMPE ; For compatibility 766.equ EERIE = 3 ; EEPROM Ready Interrupt Enable 767.equ EEPM0 = 4 ; EEPROM Programming Mode Bit 0 768.equ EEPM1 = 5 ; EEPROM Programming Mode Bit 1 769 770 771 772; ***** LOCKSBITS ******************************************************** 773.equ LB1 = 0 ; Lockbit 774.equ LB2 = 1 ; Lockbit 775 776 777; ***** FUSES ************************************************************ 778; LOW fuse bits 779.equ CKSEL0 = 0 ; Select Clock Source 780.equ CKSEL1 = 1 ; Select Clock Source 781.equ SUT0 = 4 ; Select start-up time 782.equ SUT1 = 5 ; Select start-up time 783.equ CKOUT = 6 ; Clock output 784.equ CKDIV8 = 7 ; Divide clock by 8 785 786; HIGH fuse bits 787.equ BODLEVEL0 = 0 ; Brown-out Detector trigger level 788.equ BODLEVEL1 = 1 ; Brown-out Detector trigger level 789.equ BODLEVEL2 = 2 ; Brown-out Detector trigger level 790.equ EESAVE = 3 ; EEPROM memory is preserved through chip erase 791.equ WDTON = 4 ; Watchdog Timer Always On 792.equ SPIEN = 5 ; Enable Serial programming and Data Downloading 793.equ DWEN = 6 ; debugWIRE Enable 794.equ RSTDISBL = 7 ; External reset disable 795 796; EXTENDED fuse bits 797;.equ SELFPRGEN = 0 ; Self Programming Enable 798 799 800 801; ***** CPU REGISTER DEFINITIONS ***************************************** 802.def XH = r27 803.def XL = r26 804.def YH = r29 805.def YL = r28 806.def ZH = r31 807.def ZL = r30 808 809 810 811; ***** DATA MEMORY DECLARATIONS ***************************************** 812.equ FLASHEND = 0x0fff ; Note: Word address 813.equ IOEND = 0x00ff 814.equ SRAM_START = 0x0100 815.equ SRAM_SIZE = 512 816.equ RAMEND = 0x02ff 817.equ XRAMEND = 0x0000 818.equ E2END = 0x003f 819.equ EEPROMEND = 0x003f 820.equ EEADRBITS = 6 821#pragma AVRPART MEMORY PROG_FLASH 8192 822#pragma AVRPART MEMORY EEPROM 64 823#pragma AVRPART MEMORY INT_SRAM SIZE 512 824#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x100 825 826 827 828; ***** BOOTLOADER DECLARATIONS ****************************************** 829.equ NRWW_START_ADDR = 0x0 830.equ NRWW_STOP_ADDR = 0xfff 831.equ RWW_START_ADDR = 0x0 832.equ RWW_STOP_ADDR = 0x0 833.equ PAGESIZE = 32 834 835 836 837; ***** INTERRUPT VECTORS ************************************************ 838.equ INT0addr = 0x0001 ; External Interrupt Request 0 839.equ INT1addr = 0x0002 ; External Interrupt Request 1 840.equ PCI0addr = 0x0003 ; Pin Change Interrupt Request 0 841.equ PCI1addr = 0x0004 ; Pin Change Interrupt Request 1 842.equ PCI2addr = 0x0005 ; Pin Change Interrupt Request 2 843.equ PCI3addr = 0x0006 ; Pin Change Interrupt Request 3 844.equ WDTaddr = 0x0007 ; Watchdog Time-out Interrupt 845.equ ICP1addr = 0x0008 ; Timer/Counter1 Capture Event 846.equ OC1Aaddr = 0x0009 ; Timer/Counter1 Compare Match A 847.equ OC1Baddr = 0x000a ; Timer/Counter1 Compare Match B 848.equ OVF1addr = 0x000b ; Timer/Counter1 Overflow 849.equ OC0Aaddr = 0x000c ; TimerCounter0 Compare Match A 850.equ OC0Baddr = 0x000d ; TimerCounter0 Compare Match B 851.equ OVF0addr = 0x000e ; Timer/Couner0 Overflow 852.equ SPIaddr = 0x000f ; SPI Serial Transfer Complete 853.equ ADCCaddr = 0x0010 ; ADC Conversion Complete 854.equ ERDYaddr = 0x0011 ; EEPROM Ready 855.equ ACIaddr = 0x0012 ; Analog Comparator 856.equ TWIaddr = 0x0013 ; Two-wire Serial Interface 857 858.equ INT_VECTORS_SIZE = 20 ; size in words 859 860#endif /* _TN88DEF_INC_ */ 861 862; ***** END OF FILE ****************************************************** 863