1 /* aarch64-opc.h -- Header file for aarch64-opc.c and aarch64-opc-2.c.
2 Copyright (C) 2012-2021 Free Software Foundation, Inc.
3 Contributed by ARM Ltd.
4
5 This file is part of the GNU opcodes library.
6
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
11
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; see the file COPYING3. If not,
19 see <http://www.gnu.org/licenses/>. */
20
21 #ifndef OPCODES_AARCH64_OPC_H
22 #define OPCODES_AARCH64_OPC_H
23
24 #include <string.h>
25 #include "opcode/aarch64.h"
26
27 /* Instruction fields.
28 Keep synced with fields. */
29 enum aarch64_field_kind
30 {
31 FLD_NIL,
32 FLD_cond2,
33 FLD_nzcv,
34 FLD_defgh,
35 FLD_abc,
36 FLD_imm19,
37 FLD_immhi,
38 FLD_immlo,
39 FLD_size,
40 FLD_vldst_size,
41 FLD_op,
42 FLD_Q,
43 FLD_Rt,
44 FLD_Rd,
45 FLD_Rn,
46 FLD_Rt2,
47 FLD_Ra,
48 FLD_op2,
49 FLD_CRm,
50 FLD_CRn,
51 FLD_op1,
52 FLD_op0,
53 FLD_imm3,
54 FLD_cond,
55 FLD_opcode,
56 FLD_cmode,
57 FLD_asisdlso_opcode,
58 FLD_len,
59 FLD_Rm,
60 FLD_Rs,
61 FLD_option,
62 FLD_S,
63 FLD_hw,
64 FLD_opc,
65 FLD_opc1,
66 FLD_shift,
67 FLD_type,
68 FLD_ldst_size,
69 FLD_imm6,
70 FLD_imm6_2,
71 FLD_imm4,
72 FLD_imm4_2,
73 FLD_imm4_3,
74 FLD_imm5,
75 FLD_imm7,
76 FLD_imm8,
77 FLD_imm9,
78 FLD_imm12,
79 FLD_imm14,
80 FLD_imm16,
81 FLD_imm16_2,
82 FLD_imm26,
83 FLD_imms,
84 FLD_immr,
85 FLD_immb,
86 FLD_immh,
87 FLD_S_imm10,
88 FLD_N,
89 FLD_index,
90 FLD_index2,
91 FLD_sf,
92 FLD_lse_sz,
93 FLD_H,
94 FLD_L,
95 FLD_M,
96 FLD_b5,
97 FLD_b40,
98 FLD_scale,
99 FLD_SVE_M_4,
100 FLD_SVE_M_14,
101 FLD_SVE_M_16,
102 FLD_SVE_N,
103 FLD_SVE_Pd,
104 FLD_SVE_Pg3,
105 FLD_SVE_Pg4_5,
106 FLD_SVE_Pg4_10,
107 FLD_SVE_Pg4_16,
108 FLD_SVE_Pm,
109 FLD_SVE_Pn,
110 FLD_SVE_Pt,
111 FLD_SVE_Rm,
112 FLD_SVE_Rn,
113 FLD_SVE_Vd,
114 FLD_SVE_Vm,
115 FLD_SVE_Vn,
116 FLD_SVE_Za_5,
117 FLD_SVE_Za_16,
118 FLD_SVE_Zd,
119 FLD_SVE_Zm_5,
120 FLD_SVE_Zm_16,
121 FLD_SVE_Zn,
122 FLD_SVE_Zt,
123 FLD_SVE_i1,
124 FLD_SVE_i3h,
125 FLD_SVE_i3l,
126 FLD_SVE_i3h2,
127 FLD_SVE_i2h,
128 FLD_SVE_imm3,
129 FLD_SVE_imm4,
130 FLD_SVE_imm5,
131 FLD_SVE_imm5b,
132 FLD_SVE_imm6,
133 FLD_SVE_imm7,
134 FLD_SVE_imm8,
135 FLD_SVE_imm9,
136 FLD_SVE_immr,
137 FLD_SVE_imms,
138 FLD_SVE_msz,
139 FLD_SVE_pattern,
140 FLD_SVE_prfop,
141 FLD_SVE_rot1,
142 FLD_SVE_rot2,
143 FLD_SVE_rot3,
144 FLD_SVE_sz,
145 FLD_SVE_size,
146 FLD_SVE_sz2,
147 FLD_SVE_tsz,
148 FLD_SVE_tszh,
149 FLD_SVE_tszl_8,
150 FLD_SVE_tszl_19,
151 FLD_SVE_xs_14,
152 FLD_SVE_xs_22,
153 FLD_rotate1,
154 FLD_rotate2,
155 FLD_rotate3,
156 FLD_SM3_imm2,
157 FLD_sz,
158 FLD_CRm_dsb_nxs
159 };
160
161 /* Field description. */
162 struct aarch64_field
163 {
164 int lsb;
165 int width;
166 };
167
168 typedef struct aarch64_field aarch64_field;
169
170 extern const aarch64_field fields[];
171
172 /* Operand description. */
173
174 struct aarch64_operand
175 {
176 enum aarch64_operand_class op_class;
177
178 /* Name of the operand code; used mainly for the purpose of internal
179 debugging. */
180 const char *name;
181
182 unsigned int flags;
183
184 /* The associated instruction bit-fields; no operand has more than 4
185 bit-fields */
186 enum aarch64_field_kind fields[4];
187
188 /* Brief description */
189 const char *desc;
190 };
191
192 typedef struct aarch64_operand aarch64_operand;
193
194 extern const aarch64_operand aarch64_operands[];
195
196 enum err_type
197 verify_constraints (const struct aarch64_inst *, const aarch64_insn, bfd_vma,
198 bool, aarch64_operand_error *, aarch64_instr_sequence*);
199
200 /* Operand flags. */
201
202 #define OPD_F_HAS_INSERTER 0x00000001
203 #define OPD_F_HAS_EXTRACTOR 0x00000002
204 #define OPD_F_SEXT 0x00000004 /* Require sign-extension. */
205 #define OPD_F_SHIFT_BY_2 0x00000008 /* Need to left shift the field
206 value by 2 to get the value
207 of an immediate operand. */
208 #define OPD_F_MAYBE_SP 0x00000010 /* May potentially be SP. */
209 #define OPD_F_OD_MASK 0x000000e0 /* Operand-dependent data. */
210 #define OPD_F_OD_LSB 5
211 #define OPD_F_NO_ZR 0x00000100 /* ZR index not allowed. */
212 #define OPD_F_SHIFT_BY_4 0x00000200 /* Need to left shift the field
213 value by 4 to get the value
214 of an immediate operand. */
215
216
217 /* Register flags. */
218
219 #undef F_DEPRECATED
220 #define F_DEPRECATED (1 << 0) /* Deprecated system register. */
221
222 #undef F_ARCHEXT
223 #define F_ARCHEXT (1 << 1) /* Architecture dependent system register. */
224
225 #undef F_HASXT
226 #define F_HASXT (1 << 2) /* System instruction register <Xt>
227 operand. */
228
229 #undef F_REG_READ
230 #define F_REG_READ (1 << 3) /* Register can only be used to read values
231 out of. */
232
233 #undef F_REG_WRITE
234 #define F_REG_WRITE (1 << 4) /* Register can only be written to but not
235 read from. */
236
237 /* HINT operand flags. */
238 #define HINT_OPD_F_NOPRINT (1 << 0) /* Should not be printed. */
239
240 /* Encode 7-bit HINT #imm in the lower 8 bits. Use higher bits for flags. */
241 #define HINT_ENCODE(flag, val) ((flag << 8) | val)
242 #define HINT_FLAG(val) (val >> 8)
243 #define HINT_VAL(val) (val & 0xff)
244
245 static inline bool
operand_has_inserter(const aarch64_operand * operand)246 operand_has_inserter (const aarch64_operand *operand)
247 {
248 return (operand->flags & OPD_F_HAS_INSERTER) != 0;
249 }
250
251 static inline bool
operand_has_extractor(const aarch64_operand * operand)252 operand_has_extractor (const aarch64_operand *operand)
253 {
254 return (operand->flags & OPD_F_HAS_EXTRACTOR) != 0;
255 }
256
257 static inline bool
operand_need_sign_extension(const aarch64_operand * operand)258 operand_need_sign_extension (const aarch64_operand *operand)
259 {
260 return (operand->flags & OPD_F_SEXT) != 0;
261 }
262
263 static inline bool
operand_need_shift_by_two(const aarch64_operand * operand)264 operand_need_shift_by_two (const aarch64_operand *operand)
265 {
266 return (operand->flags & OPD_F_SHIFT_BY_2) != 0;
267 }
268
269 static inline bool
operand_need_shift_by_four(const aarch64_operand * operand)270 operand_need_shift_by_four (const aarch64_operand *operand)
271 {
272 return (operand->flags & OPD_F_SHIFT_BY_4) != 0;
273 }
274
275 static inline bool
operand_maybe_stack_pointer(const aarch64_operand * operand)276 operand_maybe_stack_pointer (const aarch64_operand *operand)
277 {
278 return (operand->flags & OPD_F_MAYBE_SP) != 0;
279 }
280
281 /* Return the value of the operand-specific data field (OPD_F_OD_MASK). */
282 static inline unsigned int
get_operand_specific_data(const aarch64_operand * operand)283 get_operand_specific_data (const aarch64_operand *operand)
284 {
285 return (operand->flags & OPD_F_OD_MASK) >> OPD_F_OD_LSB;
286 }
287
288 /* Return the width of field number N of operand *OPERAND. */
289 static inline unsigned
get_operand_field_width(const aarch64_operand * operand,unsigned n)290 get_operand_field_width (const aarch64_operand *operand, unsigned n)
291 {
292 assert (operand->fields[n] != FLD_NIL);
293 return fields[operand->fields[n]].width;
294 }
295
296 /* Return the total width of the operand *OPERAND. */
297 static inline unsigned
get_operand_fields_width(const aarch64_operand * operand)298 get_operand_fields_width (const aarch64_operand *operand)
299 {
300 int i = 0;
301 unsigned width = 0;
302 while (operand->fields[i] != FLD_NIL)
303 width += fields[operand->fields[i++]].width;
304 assert (width > 0 && width < 32);
305 return width;
306 }
307
308 static inline const aarch64_operand *
get_operand_from_code(enum aarch64_opnd code)309 get_operand_from_code (enum aarch64_opnd code)
310 {
311 return aarch64_operands + code;
312 }
313
314 /* Operand qualifier and operand constraint checking. */
315
316 int aarch64_match_operands_constraint (aarch64_inst *,
317 aarch64_operand_error *);
318
319 /* Operand qualifier related functions. */
320 const char* aarch64_get_qualifier_name (aarch64_opnd_qualifier_t);
321 unsigned char aarch64_get_qualifier_nelem (aarch64_opnd_qualifier_t);
322 aarch64_insn aarch64_get_qualifier_standard_value (aarch64_opnd_qualifier_t);
323 int aarch64_find_best_match (const aarch64_inst *,
324 const aarch64_opnd_qualifier_seq_t *,
325 int, aarch64_opnd_qualifier_t *);
326
327 static inline void
reset_operand_qualifier(aarch64_inst * inst,int idx)328 reset_operand_qualifier (aarch64_inst *inst, int idx)
329 {
330 assert (idx >=0 && idx < aarch64_num_of_operands (inst->opcode));
331 inst->operands[idx].qualifier = AARCH64_OPND_QLF_NIL;
332 }
333
334 /* Inline functions operating on instruction bit-field(s). */
335
336 /* Generate a mask that has WIDTH number of consecutive 1s. */
337
338 static inline aarch64_insn
gen_mask(int width)339 gen_mask (int width)
340 {
341 return ((aarch64_insn) 1 << width) - 1;
342 }
343
344 /* LSB_REL is the relative location of the lsb in the sub field, starting from 0. */
345 static inline int
gen_sub_field(enum aarch64_field_kind kind,int lsb_rel,int width,aarch64_field * ret)346 gen_sub_field (enum aarch64_field_kind kind, int lsb_rel, int width, aarch64_field *ret)
347 {
348 const aarch64_field *field = &fields[kind];
349 if (lsb_rel < 0 || width <= 0 || lsb_rel + width > field->width)
350 return 0;
351 ret->lsb = field->lsb + lsb_rel;
352 ret->width = width;
353 return 1;
354 }
355
356 /* Insert VALUE into FIELD of CODE. MASK can be zero or the base mask
357 of the opcode. */
358
359 static inline void
insert_field_2(const aarch64_field * field,aarch64_insn * code,aarch64_insn value,aarch64_insn mask)360 insert_field_2 (const aarch64_field *field, aarch64_insn *code,
361 aarch64_insn value, aarch64_insn mask)
362 {
363 assert (field->width < 32 && field->width >= 1 && field->lsb >= 0
364 && field->lsb + field->width <= 32);
365 value &= gen_mask (field->width);
366 value <<= field->lsb;
367 /* In some opcodes, field can be part of the base opcode, e.g. the size
368 field in FADD. The following helps avoid corrupt the base opcode. */
369 value &= ~mask;
370 *code |= value;
371 }
372
373 /* Extract FIELD of CODE and return the value. MASK can be zero or the base
374 mask of the opcode. */
375
376 static inline aarch64_insn
extract_field_2(const aarch64_field * field,aarch64_insn code,aarch64_insn mask)377 extract_field_2 (const aarch64_field *field, aarch64_insn code,
378 aarch64_insn mask)
379 {
380 aarch64_insn value;
381 /* Clear any bit that is a part of the base opcode. */
382 code &= ~mask;
383 value = (code >> field->lsb) & gen_mask (field->width);
384 return value;
385 }
386
387 /* Insert VALUE into field KIND of CODE. MASK can be zero or the base mask
388 of the opcode. */
389
390 static inline void
insert_field(enum aarch64_field_kind kind,aarch64_insn * code,aarch64_insn value,aarch64_insn mask)391 insert_field (enum aarch64_field_kind kind, aarch64_insn *code,
392 aarch64_insn value, aarch64_insn mask)
393 {
394 insert_field_2 (&fields[kind], code, value, mask);
395 }
396
397 /* Extract field KIND of CODE and return the value. MASK can be zero or the
398 base mask of the opcode. */
399
400 static inline aarch64_insn
extract_field(enum aarch64_field_kind kind,aarch64_insn code,aarch64_insn mask)401 extract_field (enum aarch64_field_kind kind, aarch64_insn code,
402 aarch64_insn mask)
403 {
404 return extract_field_2 (&fields[kind], code, mask);
405 }
406
407 extern aarch64_insn
408 extract_fields (aarch64_insn code, aarch64_insn mask, ...);
409
410 /* Inline functions selecting operand to do the encoding/decoding for a
411 certain instruction bit-field. */
412
413 /* Select the operand to do the encoding/decoding of the 'sf' field.
414 The heuristic-based rule is that the result operand is respected more. */
415
416 static inline int
select_operand_for_sf_field_coding(const aarch64_opcode * opcode)417 select_operand_for_sf_field_coding (const aarch64_opcode *opcode)
418 {
419 int idx = -1;
420 if (aarch64_get_operand_class (opcode->operands[0])
421 == AARCH64_OPND_CLASS_INT_REG)
422 /* normal case. */
423 idx = 0;
424 else if (aarch64_get_operand_class (opcode->operands[1])
425 == AARCH64_OPND_CLASS_INT_REG)
426 /* e.g. float2fix. */
427 idx = 1;
428 else
429 { assert (0); abort (); }
430 return idx;
431 }
432
433 /* Select the operand to do the encoding/decoding of the 'type' field in
434 the floating-point instructions.
435 The heuristic-based rule is that the source operand is respected more. */
436
437 static inline int
select_operand_for_fptype_field_coding(const aarch64_opcode * opcode)438 select_operand_for_fptype_field_coding (const aarch64_opcode *opcode)
439 {
440 int idx;
441 if (aarch64_get_operand_class (opcode->operands[1])
442 == AARCH64_OPND_CLASS_FP_REG)
443 /* normal case. */
444 idx = 1;
445 else if (aarch64_get_operand_class (opcode->operands[0])
446 == AARCH64_OPND_CLASS_FP_REG)
447 /* e.g. float2fix. */
448 idx = 0;
449 else
450 { assert (0); abort (); }
451 return idx;
452 }
453
454 /* Select the operand to do the encoding/decoding of the 'size' field in
455 the AdvSIMD scalar instructions.
456 The heuristic-based rule is that the destination operand is respected
457 more. */
458
459 static inline int
select_operand_for_scalar_size_field_coding(const aarch64_opcode * opcode)460 select_operand_for_scalar_size_field_coding (const aarch64_opcode *opcode)
461 {
462 int src_size = 0, dst_size = 0;
463 if (aarch64_get_operand_class (opcode->operands[0])
464 == AARCH64_OPND_CLASS_SISD_REG)
465 dst_size = aarch64_get_qualifier_esize (opcode->qualifiers_list[0][0]);
466 if (aarch64_get_operand_class (opcode->operands[1])
467 == AARCH64_OPND_CLASS_SISD_REG)
468 src_size = aarch64_get_qualifier_esize (opcode->qualifiers_list[0][1]);
469 if (src_size == dst_size && src_size == 0)
470 { assert (0); abort (); }
471 /* When the result is not a sisd register or it is a long operantion. */
472 if (dst_size == 0 || dst_size == src_size << 1)
473 return 1;
474 else
475 return 0;
476 }
477
478 /* Select the operand to do the encoding/decoding of the 'size:Q' fields in
479 the AdvSIMD instructions. */
480
481 int aarch64_select_operand_for_sizeq_field_coding (const aarch64_opcode *);
482
483 /* Miscellaneous. */
484
485 aarch64_insn aarch64_get_operand_modifier_value (enum aarch64_modifier_kind);
486 enum aarch64_modifier_kind
487 aarch64_get_operand_modifier_from_value (aarch64_insn, bool);
488
489
490 bool aarch64_wide_constant_p (uint64_t, int, unsigned int *);
491 bool aarch64_logical_immediate_p (uint64_t, int, aarch64_insn *);
492 int aarch64_shrink_expanded_imm8 (uint64_t);
493
494 /* Copy the content of INST->OPERANDS[SRC] to INST->OPERANDS[DST]. */
495 static inline void
copy_operand_info(aarch64_inst * inst,int dst,int src)496 copy_operand_info (aarch64_inst *inst, int dst, int src)
497 {
498 assert (dst >= 0 && src >= 0 && dst < AARCH64_MAX_OPND_NUM
499 && src < AARCH64_MAX_OPND_NUM);
500 memcpy (&inst->operands[dst], &inst->operands[src],
501 sizeof (aarch64_opnd_info));
502 inst->operands[dst].idx = dst;
503 }
504
505 /* A primitive log caculator. */
506
507 static inline unsigned int
get_logsz(unsigned int size)508 get_logsz (unsigned int size)
509 {
510 const unsigned char ls[16] =
511 {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
512 if (size > 16)
513 {
514 assert (0);
515 return -1;
516 }
517 assert (ls[size - 1] != (unsigned char)-1);
518 return ls[size - 1];
519 }
520
521 #endif /* OPCODES_AARCH64_OPC_H */
522