1#if defined(__has_feature) 2#if __has_feature(memory_sanitizer) && !defined(OPENSSL_NO_ASM) 3#define OPENSSL_NO_ASM 4#endif 5#endif 6 7#if defined(__arm__) && !defined(OPENSSL_NO_ASM) && !defined(__APPLE__) 8 9#pragma GCC diagnostic ignored "-Wlanguage-extension-token" 10 11#if defined(BORINGSSL_PREFIX) 12#include <boringssl_prefix_symbols_asm.h> 13#endif 14 15# This implementation was taken from the public domain, neon2 version in 16# SUPERCOP by D. J. Bernstein and Peter Schwabe. 17 18# qhasm: int32 input_0 19 20# qhasm: int32 input_1 21 22# qhasm: int32 input_2 23 24# qhasm: int32 input_3 25 26# qhasm: stack32 input_4 27 28# qhasm: stack32 input_5 29 30# qhasm: stack32 input_6 31 32# qhasm: stack32 input_7 33 34# qhasm: int32 caller_r4 35 36# qhasm: int32 caller_r5 37 38# qhasm: int32 caller_r6 39 40# qhasm: int32 caller_r7 41 42# qhasm: int32 caller_r8 43 44# qhasm: int32 caller_r9 45 46# qhasm: int32 caller_r10 47 48# qhasm: int32 caller_r11 49 50# qhasm: int32 caller_r12 51 52# qhasm: int32 caller_r14 53 54# qhasm: reg128 caller_q4 55 56# qhasm: reg128 caller_q5 57 58# qhasm: reg128 caller_q6 59 60# qhasm: reg128 caller_q7 61 62# qhasm: startcode 63.fpu neon 64.text 65 66# qhasm: reg128 r0 67 68# qhasm: reg128 r1 69 70# qhasm: reg128 r2 71 72# qhasm: reg128 r3 73 74# qhasm: reg128 r4 75 76# qhasm: reg128 x01 77 78# qhasm: reg128 x23 79 80# qhasm: reg128 x4 81 82# qhasm: reg128 y0 83 84# qhasm: reg128 y12 85 86# qhasm: reg128 y34 87 88# qhasm: reg128 5y12 89 90# qhasm: reg128 5y34 91 92# qhasm: stack128 y0_stack 93 94# qhasm: stack128 y12_stack 95 96# qhasm: stack128 y34_stack 97 98# qhasm: stack128 5y12_stack 99 100# qhasm: stack128 5y34_stack 101 102# qhasm: reg128 z0 103 104# qhasm: reg128 z12 105 106# qhasm: reg128 z34 107 108# qhasm: reg128 5z12 109 110# qhasm: reg128 5z34 111 112# qhasm: stack128 z0_stack 113 114# qhasm: stack128 z12_stack 115 116# qhasm: stack128 z34_stack 117 118# qhasm: stack128 5z12_stack 119 120# qhasm: stack128 5z34_stack 121 122# qhasm: stack128 two24 123 124# qhasm: int32 ptr 125 126# qhasm: reg128 c01 127 128# qhasm: reg128 c23 129 130# qhasm: reg128 d01 131 132# qhasm: reg128 d23 133 134# qhasm: reg128 t0 135 136# qhasm: reg128 t1 137 138# qhasm: reg128 t2 139 140# qhasm: reg128 t3 141 142# qhasm: reg128 t4 143 144# qhasm: reg128 mask 145 146# qhasm: reg128 u0 147 148# qhasm: reg128 u1 149 150# qhasm: reg128 u2 151 152# qhasm: reg128 u3 153 154# qhasm: reg128 u4 155 156# qhasm: reg128 v01 157 158# qhasm: reg128 mid 159 160# qhasm: reg128 v23 161 162# qhasm: reg128 v4 163 164# qhasm: int32 len 165 166# qhasm: qpushenter crypto_onetimeauth_poly1305_neon2_blocks 167.align 4 168.global GFp_poly1305_neon2_blocks 169.hidden GFp_poly1305_neon2_blocks 170.type GFp_poly1305_neon2_blocks STT_FUNC 171GFp_poly1305_neon2_blocks: 172vpush {q4,q5,q6,q7} 173mov r12,sp 174sub sp,sp,#192 175bic sp,sp,#31 176 177# qhasm: len = input_3 178# asm 1: mov >len=int32#4,<input_3=int32#4 179# asm 2: mov >len=r3,<input_3=r3 180mov r3,r3 181 182# qhasm: new y0 183 184# qhasm: y0 = mem64[input_1]y0[1]; input_1 += 8 185# asm 1: vld1.8 {<y0=reg128#1%bot},[<input_1=int32#2]! 186# asm 2: vld1.8 {<y0=d0},[<input_1=r1]! 187vld1.8 {d0},[r1]! 188 189# qhasm: y12 = mem128[input_1]; input_1 += 16 190# asm 1: vld1.8 {>y12=reg128#2%bot->y12=reg128#2%top},[<input_1=int32#2]! 191# asm 2: vld1.8 {>y12=d2->y12=d3},[<input_1=r1]! 192vld1.8 {d2-d3},[r1]! 193 194# qhasm: y34 = mem128[input_1]; input_1 += 16 195# asm 1: vld1.8 {>y34=reg128#3%bot->y34=reg128#3%top},[<input_1=int32#2]! 196# asm 2: vld1.8 {>y34=d4->y34=d5},[<input_1=r1]! 197vld1.8 {d4-d5},[r1]! 198 199# qhasm: input_1 += 8 200# asm 1: add >input_1=int32#2,<input_1=int32#2,#8 201# asm 2: add >input_1=r1,<input_1=r1,#8 202add r1,r1,#8 203 204# qhasm: new z0 205 206# qhasm: z0 = mem64[input_1]z0[1]; input_1 += 8 207# asm 1: vld1.8 {<z0=reg128#4%bot},[<input_1=int32#2]! 208# asm 2: vld1.8 {<z0=d6},[<input_1=r1]! 209vld1.8 {d6},[r1]! 210 211# qhasm: z12 = mem128[input_1]; input_1 += 16 212# asm 1: vld1.8 {>z12=reg128#5%bot->z12=reg128#5%top},[<input_1=int32#2]! 213# asm 2: vld1.8 {>z12=d8->z12=d9},[<input_1=r1]! 214vld1.8 {d8-d9},[r1]! 215 216# qhasm: z34 = mem128[input_1]; input_1 += 16 217# asm 1: vld1.8 {>z34=reg128#6%bot->z34=reg128#6%top},[<input_1=int32#2]! 218# asm 2: vld1.8 {>z34=d10->z34=d11},[<input_1=r1]! 219vld1.8 {d10-d11},[r1]! 220 221# qhasm: 2x mask = 0xffffffff 222# asm 1: vmov.i64 >mask=reg128#7,#0xffffffff 223# asm 2: vmov.i64 >mask=q6,#0xffffffff 224vmov.i64 q6,#0xffffffff 225 226# qhasm: 2x u4 = 0xff 227# asm 1: vmov.i64 >u4=reg128#8,#0xff 228# asm 2: vmov.i64 >u4=q7,#0xff 229vmov.i64 q7,#0xff 230 231# qhasm: x01 aligned= mem128[input_0];input_0+=16 232# asm 1: vld1.8 {>x01=reg128#9%bot->x01=reg128#9%top},[<input_0=int32#1,: 128]! 233# asm 2: vld1.8 {>x01=d16->x01=d17},[<input_0=r0,: 128]! 234vld1.8 {d16-d17},[r0,: 128]! 235 236# qhasm: x23 aligned= mem128[input_0];input_0+=16 237# asm 1: vld1.8 {>x23=reg128#10%bot->x23=reg128#10%top},[<input_0=int32#1,: 128]! 238# asm 2: vld1.8 {>x23=d18->x23=d19},[<input_0=r0,: 128]! 239vld1.8 {d18-d19},[r0,: 128]! 240 241# qhasm: x4 aligned= mem64[input_0]x4[1] 242# asm 1: vld1.8 {<x4=reg128#11%bot},[<input_0=int32#1,: 64] 243# asm 2: vld1.8 {<x4=d20},[<input_0=r0,: 64] 244vld1.8 {d20},[r0,: 64] 245 246# qhasm: input_0 -= 32 247# asm 1: sub >input_0=int32#1,<input_0=int32#1,#32 248# asm 2: sub >input_0=r0,<input_0=r0,#32 249sub r0,r0,#32 250 251# qhasm: 2x mask unsigned>>=6 252# asm 1: vshr.u64 >mask=reg128#7,<mask=reg128#7,#6 253# asm 2: vshr.u64 >mask=q6,<mask=q6,#6 254vshr.u64 q6,q6,#6 255 256# qhasm: 2x u4 unsigned>>= 7 257# asm 1: vshr.u64 >u4=reg128#8,<u4=reg128#8,#7 258# asm 2: vshr.u64 >u4=q7,<u4=q7,#7 259vshr.u64 q7,q7,#7 260 261# qhasm: 4x 5y12 = y12 << 2 262# asm 1: vshl.i32 >5y12=reg128#12,<y12=reg128#2,#2 263# asm 2: vshl.i32 >5y12=q11,<y12=q1,#2 264vshl.i32 q11,q1,#2 265 266# qhasm: 4x 5y34 = y34 << 2 267# asm 1: vshl.i32 >5y34=reg128#13,<y34=reg128#3,#2 268# asm 2: vshl.i32 >5y34=q12,<y34=q2,#2 269vshl.i32 q12,q2,#2 270 271# qhasm: 4x 5y12 += y12 272# asm 1: vadd.i32 >5y12=reg128#12,<5y12=reg128#12,<y12=reg128#2 273# asm 2: vadd.i32 >5y12=q11,<5y12=q11,<y12=q1 274vadd.i32 q11,q11,q1 275 276# qhasm: 4x 5y34 += y34 277# asm 1: vadd.i32 >5y34=reg128#13,<5y34=reg128#13,<y34=reg128#3 278# asm 2: vadd.i32 >5y34=q12,<5y34=q12,<y34=q2 279vadd.i32 q12,q12,q2 280 281# qhasm: 2x u4 <<= 24 282# asm 1: vshl.i64 >u4=reg128#8,<u4=reg128#8,#24 283# asm 2: vshl.i64 >u4=q7,<u4=q7,#24 284vshl.i64 q7,q7,#24 285 286# qhasm: 4x 5z12 = z12 << 2 287# asm 1: vshl.i32 >5z12=reg128#14,<z12=reg128#5,#2 288# asm 2: vshl.i32 >5z12=q13,<z12=q4,#2 289vshl.i32 q13,q4,#2 290 291# qhasm: 4x 5z34 = z34 << 2 292# asm 1: vshl.i32 >5z34=reg128#15,<z34=reg128#6,#2 293# asm 2: vshl.i32 >5z34=q14,<z34=q5,#2 294vshl.i32 q14,q5,#2 295 296# qhasm: 4x 5z12 += z12 297# asm 1: vadd.i32 >5z12=reg128#14,<5z12=reg128#14,<z12=reg128#5 298# asm 2: vadd.i32 >5z12=q13,<5z12=q13,<z12=q4 299vadd.i32 q13,q13,q4 300 301# qhasm: 4x 5z34 += z34 302# asm 1: vadd.i32 >5z34=reg128#15,<5z34=reg128#15,<z34=reg128#6 303# asm 2: vadd.i32 >5z34=q14,<5z34=q14,<z34=q5 304vadd.i32 q14,q14,q5 305 306# qhasm: new two24 307 308# qhasm: new y0_stack 309 310# qhasm: new y12_stack 311 312# qhasm: new y34_stack 313 314# qhasm: new 5y12_stack 315 316# qhasm: new 5y34_stack 317 318# qhasm: new z0_stack 319 320# qhasm: new z12_stack 321 322# qhasm: new z34_stack 323 324# qhasm: new 5z12_stack 325 326# qhasm: new 5z34_stack 327 328# qhasm: ptr = &two24 329# asm 1: lea >ptr=int32#2,<two24=stack128#1 330# asm 2: lea >ptr=r1,<two24=[sp,#0] 331add r1,sp,#0 332 333# qhasm: mem128[ptr] aligned= u4 334# asm 1: vst1.8 {<u4=reg128#8%bot-<u4=reg128#8%top},[<ptr=int32#2,: 128] 335# asm 2: vst1.8 {<u4=d14-<u4=d15},[<ptr=r1,: 128] 336vst1.8 {d14-d15},[r1,: 128] 337 338# qhasm: r4 = u4 339# asm 1: vmov >r4=reg128#16,<u4=reg128#8 340# asm 2: vmov >r4=q15,<u4=q7 341vmov q15,q7 342 343# qhasm: r0 = u4 344# asm 1: vmov >r0=reg128#8,<u4=reg128#8 345# asm 2: vmov >r0=q7,<u4=q7 346vmov q7,q7 347 348# qhasm: ptr = &y0_stack 349# asm 1: lea >ptr=int32#2,<y0_stack=stack128#2 350# asm 2: lea >ptr=r1,<y0_stack=[sp,#16] 351add r1,sp,#16 352 353# qhasm: mem128[ptr] aligned= y0 354# asm 1: vst1.8 {<y0=reg128#1%bot-<y0=reg128#1%top},[<ptr=int32#2,: 128] 355# asm 2: vst1.8 {<y0=d0-<y0=d1},[<ptr=r1,: 128] 356vst1.8 {d0-d1},[r1,: 128] 357 358# qhasm: ptr = &y12_stack 359# asm 1: lea >ptr=int32#2,<y12_stack=stack128#3 360# asm 2: lea >ptr=r1,<y12_stack=[sp,#32] 361add r1,sp,#32 362 363# qhasm: mem128[ptr] aligned= y12 364# asm 1: vst1.8 {<y12=reg128#2%bot-<y12=reg128#2%top},[<ptr=int32#2,: 128] 365# asm 2: vst1.8 {<y12=d2-<y12=d3},[<ptr=r1,: 128] 366vst1.8 {d2-d3},[r1,: 128] 367 368# qhasm: ptr = &y34_stack 369# asm 1: lea >ptr=int32#2,<y34_stack=stack128#4 370# asm 2: lea >ptr=r1,<y34_stack=[sp,#48] 371add r1,sp,#48 372 373# qhasm: mem128[ptr] aligned= y34 374# asm 1: vst1.8 {<y34=reg128#3%bot-<y34=reg128#3%top},[<ptr=int32#2,: 128] 375# asm 2: vst1.8 {<y34=d4-<y34=d5},[<ptr=r1,: 128] 376vst1.8 {d4-d5},[r1,: 128] 377 378# qhasm: ptr = &z0_stack 379# asm 1: lea >ptr=int32#2,<z0_stack=stack128#7 380# asm 2: lea >ptr=r1,<z0_stack=[sp,#96] 381add r1,sp,#96 382 383# qhasm: mem128[ptr] aligned= z0 384# asm 1: vst1.8 {<z0=reg128#4%bot-<z0=reg128#4%top},[<ptr=int32#2,: 128] 385# asm 2: vst1.8 {<z0=d6-<z0=d7},[<ptr=r1,: 128] 386vst1.8 {d6-d7},[r1,: 128] 387 388# qhasm: ptr = &z12_stack 389# asm 1: lea >ptr=int32#2,<z12_stack=stack128#8 390# asm 2: lea >ptr=r1,<z12_stack=[sp,#112] 391add r1,sp,#112 392 393# qhasm: mem128[ptr] aligned= z12 394# asm 1: vst1.8 {<z12=reg128#5%bot-<z12=reg128#5%top},[<ptr=int32#2,: 128] 395# asm 2: vst1.8 {<z12=d8-<z12=d9},[<ptr=r1,: 128] 396vst1.8 {d8-d9},[r1,: 128] 397 398# qhasm: ptr = &z34_stack 399# asm 1: lea >ptr=int32#2,<z34_stack=stack128#9 400# asm 2: lea >ptr=r1,<z34_stack=[sp,#128] 401add r1,sp,#128 402 403# qhasm: mem128[ptr] aligned= z34 404# asm 1: vst1.8 {<z34=reg128#6%bot-<z34=reg128#6%top},[<ptr=int32#2,: 128] 405# asm 2: vst1.8 {<z34=d10-<z34=d11},[<ptr=r1,: 128] 406vst1.8 {d10-d11},[r1,: 128] 407 408# qhasm: ptr = &5y12_stack 409# asm 1: lea >ptr=int32#2,<5y12_stack=stack128#5 410# asm 2: lea >ptr=r1,<5y12_stack=[sp,#64] 411add r1,sp,#64 412 413# qhasm: mem128[ptr] aligned= 5y12 414# asm 1: vst1.8 {<5y12=reg128#12%bot-<5y12=reg128#12%top},[<ptr=int32#2,: 128] 415# asm 2: vst1.8 {<5y12=d22-<5y12=d23},[<ptr=r1,: 128] 416vst1.8 {d22-d23},[r1,: 128] 417 418# qhasm: ptr = &5y34_stack 419# asm 1: lea >ptr=int32#2,<5y34_stack=stack128#6 420# asm 2: lea >ptr=r1,<5y34_stack=[sp,#80] 421add r1,sp,#80 422 423# qhasm: mem128[ptr] aligned= 5y34 424# asm 1: vst1.8 {<5y34=reg128#13%bot-<5y34=reg128#13%top},[<ptr=int32#2,: 128] 425# asm 2: vst1.8 {<5y34=d24-<5y34=d25},[<ptr=r1,: 128] 426vst1.8 {d24-d25},[r1,: 128] 427 428# qhasm: ptr = &5z12_stack 429# asm 1: lea >ptr=int32#2,<5z12_stack=stack128#10 430# asm 2: lea >ptr=r1,<5z12_stack=[sp,#144] 431add r1,sp,#144 432 433# qhasm: mem128[ptr] aligned= 5z12 434# asm 1: vst1.8 {<5z12=reg128#14%bot-<5z12=reg128#14%top},[<ptr=int32#2,: 128] 435# asm 2: vst1.8 {<5z12=d26-<5z12=d27},[<ptr=r1,: 128] 436vst1.8 {d26-d27},[r1,: 128] 437 438# qhasm: ptr = &5z34_stack 439# asm 1: lea >ptr=int32#2,<5z34_stack=stack128#11 440# asm 2: lea >ptr=r1,<5z34_stack=[sp,#160] 441add r1,sp,#160 442 443# qhasm: mem128[ptr] aligned= 5z34 444# asm 1: vst1.8 {<5z34=reg128#15%bot-<5z34=reg128#15%top},[<ptr=int32#2,: 128] 445# asm 2: vst1.8 {<5z34=d28-<5z34=d29},[<ptr=r1,: 128] 446vst1.8 {d28-d29},[r1,: 128] 447 448# qhasm: unsigned>? len - 64 449# asm 1: cmp <len=int32#4,#64 450# asm 2: cmp <len=r3,#64 451cmp r3,#64 452 453# qhasm: goto below64bytes if !unsigned> 454bls ._below64bytes 455 456# qhasm: input_2 += 32 457# asm 1: add >input_2=int32#2,<input_2=int32#3,#32 458# asm 2: add >input_2=r1,<input_2=r2,#32 459add r1,r2,#32 460 461# qhasm: mainloop2: 462._mainloop2: 463 464# qhasm: c01 = mem128[input_2];input_2+=16 465# asm 1: vld1.8 {>c01=reg128#1%bot->c01=reg128#1%top},[<input_2=int32#2]! 466# asm 2: vld1.8 {>c01=d0->c01=d1},[<input_2=r1]! 467vld1.8 {d0-d1},[r1]! 468 469# qhasm: c23 = mem128[input_2];input_2+=16 470# asm 1: vld1.8 {>c23=reg128#2%bot->c23=reg128#2%top},[<input_2=int32#2]! 471# asm 2: vld1.8 {>c23=d2->c23=d3},[<input_2=r1]! 472vld1.8 {d2-d3},[r1]! 473 474# qhasm: r4[0,1] += x01[0] unsigned* z34[2]; r4[2,3] += x01[1] unsigned* z34[3] 475# asm 1: vmlal.u32 <r4=reg128#16,<x01=reg128#9%bot,<z34=reg128#6%top 476# asm 2: vmlal.u32 <r4=q15,<x01=d16,<z34=d11 477vmlal.u32 q15,d16,d11 478 479# qhasm: ptr = &z12_stack 480# asm 1: lea >ptr=int32#3,<z12_stack=stack128#8 481# asm 2: lea >ptr=r2,<z12_stack=[sp,#112] 482add r2,sp,#112 483 484# qhasm: z12 aligned= mem128[ptr] 485# asm 1: vld1.8 {>z12=reg128#3%bot->z12=reg128#3%top},[<ptr=int32#3,: 128] 486# asm 2: vld1.8 {>z12=d4->z12=d5},[<ptr=r2,: 128] 487vld1.8 {d4-d5},[r2,: 128] 488 489# qhasm: r4[0,1] += x01[2] unsigned* z34[0]; r4[2,3] += x01[3] unsigned* z34[1] 490# asm 1: vmlal.u32 <r4=reg128#16,<x01=reg128#9%top,<z34=reg128#6%bot 491# asm 2: vmlal.u32 <r4=q15,<x01=d17,<z34=d10 492vmlal.u32 q15,d17,d10 493 494# qhasm: ptr = &z0_stack 495# asm 1: lea >ptr=int32#3,<z0_stack=stack128#7 496# asm 2: lea >ptr=r2,<z0_stack=[sp,#96] 497add r2,sp,#96 498 499# qhasm: z0 aligned= mem128[ptr] 500# asm 1: vld1.8 {>z0=reg128#4%bot->z0=reg128#4%top},[<ptr=int32#3,: 128] 501# asm 2: vld1.8 {>z0=d6->z0=d7},[<ptr=r2,: 128] 502vld1.8 {d6-d7},[r2,: 128] 503 504# qhasm: r4[0,1] += x23[0] unsigned* z12[2]; r4[2,3] += x23[1] unsigned* z12[3] 505# asm 1: vmlal.u32 <r4=reg128#16,<x23=reg128#10%bot,<z12=reg128#3%top 506# asm 2: vmlal.u32 <r4=q15,<x23=d18,<z12=d5 507vmlal.u32 q15,d18,d5 508 509# qhasm: c01 c23 = c01[0]c01[1]c01[2]c23[2]c23[0]c23[1]c01[3]c23[3] 510# asm 1: vtrn.32 <c01=reg128#1%top,<c23=reg128#2%top 511# asm 2: vtrn.32 <c01=d1,<c23=d3 512vtrn.32 d1,d3 513 514# qhasm: r4[0,1] += x23[2] unsigned* z12[0]; r4[2,3] += x23[3] unsigned* z12[1] 515# asm 1: vmlal.u32 <r4=reg128#16,<x23=reg128#10%top,<z12=reg128#3%bot 516# asm 2: vmlal.u32 <r4=q15,<x23=d19,<z12=d4 517vmlal.u32 q15,d19,d4 518 519# qhasm: r4[0,1] += x4[0] unsigned* z0[0]; r4[2,3] += x4[1] unsigned* z0[1] 520# asm 1: vmlal.u32 <r4=reg128#16,<x4=reg128#11%bot,<z0=reg128#4%bot 521# asm 2: vmlal.u32 <r4=q15,<x4=d20,<z0=d6 522vmlal.u32 q15,d20,d6 523 524# qhasm: r3[0,1] = c23[2]<<18; r3[2,3] = c23[3]<<18 525# asm 1: vshll.u32 >r3=reg128#5,<c23=reg128#2%top,#18 526# asm 2: vshll.u32 >r3=q4,<c23=d3,#18 527vshll.u32 q4,d3,#18 528 529# qhasm: c01 c23 = c01[0]c23[0]c01[2]c01[3]c01[1]c23[1]c23[2]c23[3] 530# asm 1: vtrn.32 <c01=reg128#1%bot,<c23=reg128#2%bot 531# asm 2: vtrn.32 <c01=d0,<c23=d2 532vtrn.32 d0,d2 533 534# qhasm: r3[0,1] += x01[0] unsigned* z34[0]; r3[2,3] += x01[1] unsigned* z34[1] 535# asm 1: vmlal.u32 <r3=reg128#5,<x01=reg128#9%bot,<z34=reg128#6%bot 536# asm 2: vmlal.u32 <r3=q4,<x01=d16,<z34=d10 537vmlal.u32 q4,d16,d10 538 539# qhasm: r3[0,1] += x01[2] unsigned* z12[2]; r3[2,3] += x01[3] unsigned* z12[3] 540# asm 1: vmlal.u32 <r3=reg128#5,<x01=reg128#9%top,<z12=reg128#3%top 541# asm 2: vmlal.u32 <r3=q4,<x01=d17,<z12=d5 542vmlal.u32 q4,d17,d5 543 544# qhasm: r0 = r0[1]c01[0]r0[2,3] 545# asm 1: vext.32 <r0=reg128#8%bot,<r0=reg128#8%bot,<c01=reg128#1%bot,#1 546# asm 2: vext.32 <r0=d14,<r0=d14,<c01=d0,#1 547vext.32 d14,d14,d0,#1 548 549# qhasm: r3[0,1] += x23[0] unsigned* z12[0]; r3[2,3] += x23[1] unsigned* z12[1] 550# asm 1: vmlal.u32 <r3=reg128#5,<x23=reg128#10%bot,<z12=reg128#3%bot 551# asm 2: vmlal.u32 <r3=q4,<x23=d18,<z12=d4 552vmlal.u32 q4,d18,d4 553 554# qhasm: input_2 -= 64 555# asm 1: sub >input_2=int32#2,<input_2=int32#2,#64 556# asm 2: sub >input_2=r1,<input_2=r1,#64 557sub r1,r1,#64 558 559# qhasm: r3[0,1] += x23[2] unsigned* z0[0]; r3[2,3] += x23[3] unsigned* z0[1] 560# asm 1: vmlal.u32 <r3=reg128#5,<x23=reg128#10%top,<z0=reg128#4%bot 561# asm 2: vmlal.u32 <r3=q4,<x23=d19,<z0=d6 562vmlal.u32 q4,d19,d6 563 564# qhasm: ptr = &5z34_stack 565# asm 1: lea >ptr=int32#3,<5z34_stack=stack128#11 566# asm 2: lea >ptr=r2,<5z34_stack=[sp,#160] 567add r2,sp,#160 568 569# qhasm: 5z34 aligned= mem128[ptr] 570# asm 1: vld1.8 {>5z34=reg128#6%bot->5z34=reg128#6%top},[<ptr=int32#3,: 128] 571# asm 2: vld1.8 {>5z34=d10->5z34=d11},[<ptr=r2,: 128] 572vld1.8 {d10-d11},[r2,: 128] 573 574# qhasm: r3[0,1] += x4[0] unsigned* 5z34[2]; r3[2,3] += x4[1] unsigned* 5z34[3] 575# asm 1: vmlal.u32 <r3=reg128#5,<x4=reg128#11%bot,<5z34=reg128#6%top 576# asm 2: vmlal.u32 <r3=q4,<x4=d20,<5z34=d11 577vmlal.u32 q4,d20,d11 578 579# qhasm: r0 = r0[1]r0[0]r0[3]r0[2] 580# asm 1: vrev64.i32 >r0=reg128#8,<r0=reg128#8 581# asm 2: vrev64.i32 >r0=q7,<r0=q7 582vrev64.i32 q7,q7 583 584# qhasm: r2[0,1] = c01[2]<<12; r2[2,3] = c01[3]<<12 585# asm 1: vshll.u32 >r2=reg128#14,<c01=reg128#1%top,#12 586# asm 2: vshll.u32 >r2=q13,<c01=d1,#12 587vshll.u32 q13,d1,#12 588 589# qhasm: d01 = mem128[input_2];input_2+=16 590# asm 1: vld1.8 {>d01=reg128#12%bot->d01=reg128#12%top},[<input_2=int32#2]! 591# asm 2: vld1.8 {>d01=d22->d01=d23},[<input_2=r1]! 592vld1.8 {d22-d23},[r1]! 593 594# qhasm: r2[0,1] += x01[0] unsigned* z12[2]; r2[2,3] += x01[1] unsigned* z12[3] 595# asm 1: vmlal.u32 <r2=reg128#14,<x01=reg128#9%bot,<z12=reg128#3%top 596# asm 2: vmlal.u32 <r2=q13,<x01=d16,<z12=d5 597vmlal.u32 q13,d16,d5 598 599# qhasm: r2[0,1] += x01[2] unsigned* z12[0]; r2[2,3] += x01[3] unsigned* z12[1] 600# asm 1: vmlal.u32 <r2=reg128#14,<x01=reg128#9%top,<z12=reg128#3%bot 601# asm 2: vmlal.u32 <r2=q13,<x01=d17,<z12=d4 602vmlal.u32 q13,d17,d4 603 604# qhasm: r2[0,1] += x23[0] unsigned* z0[0]; r2[2,3] += x23[1] unsigned* z0[1] 605# asm 1: vmlal.u32 <r2=reg128#14,<x23=reg128#10%bot,<z0=reg128#4%bot 606# asm 2: vmlal.u32 <r2=q13,<x23=d18,<z0=d6 607vmlal.u32 q13,d18,d6 608 609# qhasm: r2[0,1] += x23[2] unsigned* 5z34[2]; r2[2,3] += x23[3] unsigned* 5z34[3] 610# asm 1: vmlal.u32 <r2=reg128#14,<x23=reg128#10%top,<5z34=reg128#6%top 611# asm 2: vmlal.u32 <r2=q13,<x23=d19,<5z34=d11 612vmlal.u32 q13,d19,d11 613 614# qhasm: r2[0,1] += x4[0] unsigned* 5z34[0]; r2[2,3] += x4[1] unsigned* 5z34[1] 615# asm 1: vmlal.u32 <r2=reg128#14,<x4=reg128#11%bot,<5z34=reg128#6%bot 616# asm 2: vmlal.u32 <r2=q13,<x4=d20,<5z34=d10 617vmlal.u32 q13,d20,d10 618 619# qhasm: r0 = r0[0,1]c01[1]r0[2] 620# asm 1: vext.32 <r0=reg128#8%top,<c01=reg128#1%bot,<r0=reg128#8%top,#1 621# asm 2: vext.32 <r0=d15,<c01=d0,<r0=d15,#1 622vext.32 d15,d0,d15,#1 623 624# qhasm: r1[0,1] = c23[0]<<6; r1[2,3] = c23[1]<<6 625# asm 1: vshll.u32 >r1=reg128#15,<c23=reg128#2%bot,#6 626# asm 2: vshll.u32 >r1=q14,<c23=d2,#6 627vshll.u32 q14,d2,#6 628 629# qhasm: r1[0,1] += x01[0] unsigned* z12[0]; r1[2,3] += x01[1] unsigned* z12[1] 630# asm 1: vmlal.u32 <r1=reg128#15,<x01=reg128#9%bot,<z12=reg128#3%bot 631# asm 2: vmlal.u32 <r1=q14,<x01=d16,<z12=d4 632vmlal.u32 q14,d16,d4 633 634# qhasm: r1[0,1] += x01[2] unsigned* z0[0]; r1[2,3] += x01[3] unsigned* z0[1] 635# asm 1: vmlal.u32 <r1=reg128#15,<x01=reg128#9%top,<z0=reg128#4%bot 636# asm 2: vmlal.u32 <r1=q14,<x01=d17,<z0=d6 637vmlal.u32 q14,d17,d6 638 639# qhasm: r1[0,1] += x23[0] unsigned* 5z34[2]; r1[2,3] += x23[1] unsigned* 5z34[3] 640# asm 1: vmlal.u32 <r1=reg128#15,<x23=reg128#10%bot,<5z34=reg128#6%top 641# asm 2: vmlal.u32 <r1=q14,<x23=d18,<5z34=d11 642vmlal.u32 q14,d18,d11 643 644# qhasm: r1[0,1] += x23[2] unsigned* 5z34[0]; r1[2,3] += x23[3] unsigned* 5z34[1] 645# asm 1: vmlal.u32 <r1=reg128#15,<x23=reg128#10%top,<5z34=reg128#6%bot 646# asm 2: vmlal.u32 <r1=q14,<x23=d19,<5z34=d10 647vmlal.u32 q14,d19,d10 648 649# qhasm: ptr = &5z12_stack 650# asm 1: lea >ptr=int32#3,<5z12_stack=stack128#10 651# asm 2: lea >ptr=r2,<5z12_stack=[sp,#144] 652add r2,sp,#144 653 654# qhasm: 5z12 aligned= mem128[ptr] 655# asm 1: vld1.8 {>5z12=reg128#1%bot->5z12=reg128#1%top},[<ptr=int32#3,: 128] 656# asm 2: vld1.8 {>5z12=d0->5z12=d1},[<ptr=r2,: 128] 657vld1.8 {d0-d1},[r2,: 128] 658 659# qhasm: r1[0,1] += x4[0] unsigned* 5z12[2]; r1[2,3] += x4[1] unsigned* 5z12[3] 660# asm 1: vmlal.u32 <r1=reg128#15,<x4=reg128#11%bot,<5z12=reg128#1%top 661# asm 2: vmlal.u32 <r1=q14,<x4=d20,<5z12=d1 662vmlal.u32 q14,d20,d1 663 664# qhasm: d23 = mem128[input_2];input_2+=16 665# asm 1: vld1.8 {>d23=reg128#2%bot->d23=reg128#2%top},[<input_2=int32#2]! 666# asm 2: vld1.8 {>d23=d2->d23=d3},[<input_2=r1]! 667vld1.8 {d2-d3},[r1]! 668 669# qhasm: input_2 += 32 670# asm 1: add >input_2=int32#2,<input_2=int32#2,#32 671# asm 2: add >input_2=r1,<input_2=r1,#32 672add r1,r1,#32 673 674# qhasm: r0[0,1] += x4[0] unsigned* 5z12[0]; r0[2,3] += x4[1] unsigned* 5z12[1] 675# asm 1: vmlal.u32 <r0=reg128#8,<x4=reg128#11%bot,<5z12=reg128#1%bot 676# asm 2: vmlal.u32 <r0=q7,<x4=d20,<5z12=d0 677vmlal.u32 q7,d20,d0 678 679# qhasm: r0[0,1] += x23[0] unsigned* 5z34[0]; r0[2,3] += x23[1] unsigned* 5z34[1] 680# asm 1: vmlal.u32 <r0=reg128#8,<x23=reg128#10%bot,<5z34=reg128#6%bot 681# asm 2: vmlal.u32 <r0=q7,<x23=d18,<5z34=d10 682vmlal.u32 q7,d18,d10 683 684# qhasm: d01 d23 = d01[0] d23[0] d01[1] d23[1] 685# asm 1: vswp <d23=reg128#2%bot,<d01=reg128#12%top 686# asm 2: vswp <d23=d2,<d01=d23 687vswp d2,d23 688 689# qhasm: r0[0,1] += x23[2] unsigned* 5z12[2]; r0[2,3] += x23[3] unsigned* 5z12[3] 690# asm 1: vmlal.u32 <r0=reg128#8,<x23=reg128#10%top,<5z12=reg128#1%top 691# asm 2: vmlal.u32 <r0=q7,<x23=d19,<5z12=d1 692vmlal.u32 q7,d19,d1 693 694# qhasm: r0[0,1] += x01[0] unsigned* z0[0]; r0[2,3] += x01[1] unsigned* z0[1] 695# asm 1: vmlal.u32 <r0=reg128#8,<x01=reg128#9%bot,<z0=reg128#4%bot 696# asm 2: vmlal.u32 <r0=q7,<x01=d16,<z0=d6 697vmlal.u32 q7,d16,d6 698 699# qhasm: new mid 700 701# qhasm: 2x v4 = d23 unsigned>> 40 702# asm 1: vshr.u64 >v4=reg128#4,<d23=reg128#2,#40 703# asm 2: vshr.u64 >v4=q3,<d23=q1,#40 704vshr.u64 q3,q1,#40 705 706# qhasm: mid = d01[1]d23[0] mid[2,3] 707# asm 1: vext.32 <mid=reg128#1%bot,<d01=reg128#12%bot,<d23=reg128#2%bot,#1 708# asm 2: vext.32 <mid=d0,<d01=d22,<d23=d2,#1 709vext.32 d0,d22,d2,#1 710 711# qhasm: new v23 712 713# qhasm: v23[2] = d23[0,1] unsigned>> 14; v23[3] = d23[2,3] unsigned>> 14 714# asm 1: vshrn.u64 <v23=reg128#10%top,<d23=reg128#2,#14 715# asm 2: vshrn.u64 <v23=d19,<d23=q1,#14 716vshrn.u64 d19,q1,#14 717 718# qhasm: mid = mid[0,1] d01[3]d23[2] 719# asm 1: vext.32 <mid=reg128#1%top,<d01=reg128#12%top,<d23=reg128#2%top,#1 720# asm 2: vext.32 <mid=d1,<d01=d23,<d23=d3,#1 721vext.32 d1,d23,d3,#1 722 723# qhasm: new v01 724 725# qhasm: v01[2] = d01[0,1] unsigned>> 26; v01[3] = d01[2,3] unsigned>> 26 726# asm 1: vshrn.u64 <v01=reg128#11%top,<d01=reg128#12,#26 727# asm 2: vshrn.u64 <v01=d21,<d01=q11,#26 728vshrn.u64 d21,q11,#26 729 730# qhasm: v01 = d01[1]d01[0] v01[2,3] 731# asm 1: vext.32 <v01=reg128#11%bot,<d01=reg128#12%bot,<d01=reg128#12%bot,#1 732# asm 2: vext.32 <v01=d20,<d01=d22,<d01=d22,#1 733vext.32 d20,d22,d22,#1 734 735# qhasm: r0[0,1] += x01[2] unsigned* 5z34[2]; r0[2,3] += x01[3] unsigned* 5z34[3] 736# asm 1: vmlal.u32 <r0=reg128#8,<x01=reg128#9%top,<5z34=reg128#6%top 737# asm 2: vmlal.u32 <r0=q7,<x01=d17,<5z34=d11 738vmlal.u32 q7,d17,d11 739 740# qhasm: v01 = v01[1]d01[2] v01[2,3] 741# asm 1: vext.32 <v01=reg128#11%bot,<v01=reg128#11%bot,<d01=reg128#12%top,#1 742# asm 2: vext.32 <v01=d20,<v01=d20,<d01=d23,#1 743vext.32 d20,d20,d23,#1 744 745# qhasm: v23[0] = mid[0,1] unsigned>> 20; v23[1] = mid[2,3] unsigned>> 20 746# asm 1: vshrn.u64 <v23=reg128#10%bot,<mid=reg128#1,#20 747# asm 2: vshrn.u64 <v23=d18,<mid=q0,#20 748vshrn.u64 d18,q0,#20 749 750# qhasm: v4 = v4[0]v4[2]v4[1]v4[3] 751# asm 1: vtrn.32 <v4=reg128#4%bot,<v4=reg128#4%top 752# asm 2: vtrn.32 <v4=d6,<v4=d7 753vtrn.32 d6,d7 754 755# qhasm: 4x v01 &= 0x03ffffff 756# asm 1: vand.i32 <v01=reg128#11,#0x03ffffff 757# asm 2: vand.i32 <v01=q10,#0x03ffffff 758vand.i32 q10,#0x03ffffff 759 760# qhasm: ptr = &y34_stack 761# asm 1: lea >ptr=int32#3,<y34_stack=stack128#4 762# asm 2: lea >ptr=r2,<y34_stack=[sp,#48] 763add r2,sp,#48 764 765# qhasm: y34 aligned= mem128[ptr] 766# asm 1: vld1.8 {>y34=reg128#3%bot->y34=reg128#3%top},[<ptr=int32#3,: 128] 767# asm 2: vld1.8 {>y34=d4->y34=d5},[<ptr=r2,: 128] 768vld1.8 {d4-d5},[r2,: 128] 769 770# qhasm: 4x v23 &= 0x03ffffff 771# asm 1: vand.i32 <v23=reg128#10,#0x03ffffff 772# asm 2: vand.i32 <v23=q9,#0x03ffffff 773vand.i32 q9,#0x03ffffff 774 775# qhasm: ptr = &y12_stack 776# asm 1: lea >ptr=int32#3,<y12_stack=stack128#3 777# asm 2: lea >ptr=r2,<y12_stack=[sp,#32] 778add r2,sp,#32 779 780# qhasm: y12 aligned= mem128[ptr] 781# asm 1: vld1.8 {>y12=reg128#2%bot->y12=reg128#2%top},[<ptr=int32#3,: 128] 782# asm 2: vld1.8 {>y12=d2->y12=d3},[<ptr=r2,: 128] 783vld1.8 {d2-d3},[r2,: 128] 784 785# qhasm: 4x v4 |= 0x01000000 786# asm 1: vorr.i32 <v4=reg128#4,#0x01000000 787# asm 2: vorr.i32 <v4=q3,#0x01000000 788vorr.i32 q3,#0x01000000 789 790# qhasm: ptr = &y0_stack 791# asm 1: lea >ptr=int32#3,<y0_stack=stack128#2 792# asm 2: lea >ptr=r2,<y0_stack=[sp,#16] 793add r2,sp,#16 794 795# qhasm: y0 aligned= mem128[ptr] 796# asm 1: vld1.8 {>y0=reg128#1%bot->y0=reg128#1%top},[<ptr=int32#3,: 128] 797# asm 2: vld1.8 {>y0=d0->y0=d1},[<ptr=r2,: 128] 798vld1.8 {d0-d1},[r2,: 128] 799 800# qhasm: r4[0,1] += v01[0] unsigned* y34[2]; r4[2,3] += v01[1] unsigned* y34[3] 801# asm 1: vmlal.u32 <r4=reg128#16,<v01=reg128#11%bot,<y34=reg128#3%top 802# asm 2: vmlal.u32 <r4=q15,<v01=d20,<y34=d5 803vmlal.u32 q15,d20,d5 804 805# qhasm: r4[0,1] += v01[2] unsigned* y34[0]; r4[2,3] += v01[3] unsigned* y34[1] 806# asm 1: vmlal.u32 <r4=reg128#16,<v01=reg128#11%top,<y34=reg128#3%bot 807# asm 2: vmlal.u32 <r4=q15,<v01=d21,<y34=d4 808vmlal.u32 q15,d21,d4 809 810# qhasm: r4[0,1] += v23[0] unsigned* y12[2]; r4[2,3] += v23[1] unsigned* y12[3] 811# asm 1: vmlal.u32 <r4=reg128#16,<v23=reg128#10%bot,<y12=reg128#2%top 812# asm 2: vmlal.u32 <r4=q15,<v23=d18,<y12=d3 813vmlal.u32 q15,d18,d3 814 815# qhasm: r4[0,1] += v23[2] unsigned* y12[0]; r4[2,3] += v23[3] unsigned* y12[1] 816# asm 1: vmlal.u32 <r4=reg128#16,<v23=reg128#10%top,<y12=reg128#2%bot 817# asm 2: vmlal.u32 <r4=q15,<v23=d19,<y12=d2 818vmlal.u32 q15,d19,d2 819 820# qhasm: r4[0,1] += v4[0] unsigned* y0[0]; r4[2,3] += v4[1] unsigned* y0[1] 821# asm 1: vmlal.u32 <r4=reg128#16,<v4=reg128#4%bot,<y0=reg128#1%bot 822# asm 2: vmlal.u32 <r4=q15,<v4=d6,<y0=d0 823vmlal.u32 q15,d6,d0 824 825# qhasm: ptr = &5y34_stack 826# asm 1: lea >ptr=int32#3,<5y34_stack=stack128#6 827# asm 2: lea >ptr=r2,<5y34_stack=[sp,#80] 828add r2,sp,#80 829 830# qhasm: 5y34 aligned= mem128[ptr] 831# asm 1: vld1.8 {>5y34=reg128#13%bot->5y34=reg128#13%top},[<ptr=int32#3,: 128] 832# asm 2: vld1.8 {>5y34=d24->5y34=d25},[<ptr=r2,: 128] 833vld1.8 {d24-d25},[r2,: 128] 834 835# qhasm: r3[0,1] += v01[0] unsigned* y34[0]; r3[2,3] += v01[1] unsigned* y34[1] 836# asm 1: vmlal.u32 <r3=reg128#5,<v01=reg128#11%bot,<y34=reg128#3%bot 837# asm 2: vmlal.u32 <r3=q4,<v01=d20,<y34=d4 838vmlal.u32 q4,d20,d4 839 840# qhasm: r3[0,1] += v01[2] unsigned* y12[2]; r3[2,3] += v01[3] unsigned* y12[3] 841# asm 1: vmlal.u32 <r3=reg128#5,<v01=reg128#11%top,<y12=reg128#2%top 842# asm 2: vmlal.u32 <r3=q4,<v01=d21,<y12=d3 843vmlal.u32 q4,d21,d3 844 845# qhasm: r3[0,1] += v23[0] unsigned* y12[0]; r3[2,3] += v23[1] unsigned* y12[1] 846# asm 1: vmlal.u32 <r3=reg128#5,<v23=reg128#10%bot,<y12=reg128#2%bot 847# asm 2: vmlal.u32 <r3=q4,<v23=d18,<y12=d2 848vmlal.u32 q4,d18,d2 849 850# qhasm: r3[0,1] += v23[2] unsigned* y0[0]; r3[2,3] += v23[3] unsigned* y0[1] 851# asm 1: vmlal.u32 <r3=reg128#5,<v23=reg128#10%top,<y0=reg128#1%bot 852# asm 2: vmlal.u32 <r3=q4,<v23=d19,<y0=d0 853vmlal.u32 q4,d19,d0 854 855# qhasm: r3[0,1] += v4[0] unsigned* 5y34[2]; r3[2,3] += v4[1] unsigned* 5y34[3] 856# asm 1: vmlal.u32 <r3=reg128#5,<v4=reg128#4%bot,<5y34=reg128#13%top 857# asm 2: vmlal.u32 <r3=q4,<v4=d6,<5y34=d25 858vmlal.u32 q4,d6,d25 859 860# qhasm: ptr = &5y12_stack 861# asm 1: lea >ptr=int32#3,<5y12_stack=stack128#5 862# asm 2: lea >ptr=r2,<5y12_stack=[sp,#64] 863add r2,sp,#64 864 865# qhasm: 5y12 aligned= mem128[ptr] 866# asm 1: vld1.8 {>5y12=reg128#12%bot->5y12=reg128#12%top},[<ptr=int32#3,: 128] 867# asm 2: vld1.8 {>5y12=d22->5y12=d23},[<ptr=r2,: 128] 868vld1.8 {d22-d23},[r2,: 128] 869 870# qhasm: r0[0,1] += v4[0] unsigned* 5y12[0]; r0[2,3] += v4[1] unsigned* 5y12[1] 871# asm 1: vmlal.u32 <r0=reg128#8,<v4=reg128#4%bot,<5y12=reg128#12%bot 872# asm 2: vmlal.u32 <r0=q7,<v4=d6,<5y12=d22 873vmlal.u32 q7,d6,d22 874 875# qhasm: r0[0,1] += v23[0] unsigned* 5y34[0]; r0[2,3] += v23[1] unsigned* 5y34[1] 876# asm 1: vmlal.u32 <r0=reg128#8,<v23=reg128#10%bot,<5y34=reg128#13%bot 877# asm 2: vmlal.u32 <r0=q7,<v23=d18,<5y34=d24 878vmlal.u32 q7,d18,d24 879 880# qhasm: r0[0,1] += v23[2] unsigned* 5y12[2]; r0[2,3] += v23[3] unsigned* 5y12[3] 881# asm 1: vmlal.u32 <r0=reg128#8,<v23=reg128#10%top,<5y12=reg128#12%top 882# asm 2: vmlal.u32 <r0=q7,<v23=d19,<5y12=d23 883vmlal.u32 q7,d19,d23 884 885# qhasm: r0[0,1] += v01[0] unsigned* y0[0]; r0[2,3] += v01[1] unsigned* y0[1] 886# asm 1: vmlal.u32 <r0=reg128#8,<v01=reg128#11%bot,<y0=reg128#1%bot 887# asm 2: vmlal.u32 <r0=q7,<v01=d20,<y0=d0 888vmlal.u32 q7,d20,d0 889 890# qhasm: r0[0,1] += v01[2] unsigned* 5y34[2]; r0[2,3] += v01[3] unsigned* 5y34[3] 891# asm 1: vmlal.u32 <r0=reg128#8,<v01=reg128#11%top,<5y34=reg128#13%top 892# asm 2: vmlal.u32 <r0=q7,<v01=d21,<5y34=d25 893vmlal.u32 q7,d21,d25 894 895# qhasm: r1[0,1] += v01[0] unsigned* y12[0]; r1[2,3] += v01[1] unsigned* y12[1] 896# asm 1: vmlal.u32 <r1=reg128#15,<v01=reg128#11%bot,<y12=reg128#2%bot 897# asm 2: vmlal.u32 <r1=q14,<v01=d20,<y12=d2 898vmlal.u32 q14,d20,d2 899 900# qhasm: r1[0,1] += v01[2] unsigned* y0[0]; r1[2,3] += v01[3] unsigned* y0[1] 901# asm 1: vmlal.u32 <r1=reg128#15,<v01=reg128#11%top,<y0=reg128#1%bot 902# asm 2: vmlal.u32 <r1=q14,<v01=d21,<y0=d0 903vmlal.u32 q14,d21,d0 904 905# qhasm: r1[0,1] += v23[0] unsigned* 5y34[2]; r1[2,3] += v23[1] unsigned* 5y34[3] 906# asm 1: vmlal.u32 <r1=reg128#15,<v23=reg128#10%bot,<5y34=reg128#13%top 907# asm 2: vmlal.u32 <r1=q14,<v23=d18,<5y34=d25 908vmlal.u32 q14,d18,d25 909 910# qhasm: r1[0,1] += v23[2] unsigned* 5y34[0]; r1[2,3] += v23[3] unsigned* 5y34[1] 911# asm 1: vmlal.u32 <r1=reg128#15,<v23=reg128#10%top,<5y34=reg128#13%bot 912# asm 2: vmlal.u32 <r1=q14,<v23=d19,<5y34=d24 913vmlal.u32 q14,d19,d24 914 915# qhasm: r1[0,1] += v4[0] unsigned* 5y12[2]; r1[2,3] += v4[1] unsigned* 5y12[3] 916# asm 1: vmlal.u32 <r1=reg128#15,<v4=reg128#4%bot,<5y12=reg128#12%top 917# asm 2: vmlal.u32 <r1=q14,<v4=d6,<5y12=d23 918vmlal.u32 q14,d6,d23 919 920# qhasm: r2[0,1] += v01[0] unsigned* y12[2]; r2[2,3] += v01[1] unsigned* y12[3] 921# asm 1: vmlal.u32 <r2=reg128#14,<v01=reg128#11%bot,<y12=reg128#2%top 922# asm 2: vmlal.u32 <r2=q13,<v01=d20,<y12=d3 923vmlal.u32 q13,d20,d3 924 925# qhasm: r2[0,1] += v01[2] unsigned* y12[0]; r2[2,3] += v01[3] unsigned* y12[1] 926# asm 1: vmlal.u32 <r2=reg128#14,<v01=reg128#11%top,<y12=reg128#2%bot 927# asm 2: vmlal.u32 <r2=q13,<v01=d21,<y12=d2 928vmlal.u32 q13,d21,d2 929 930# qhasm: r2[0,1] += v23[0] unsigned* y0[0]; r2[2,3] += v23[1] unsigned* y0[1] 931# asm 1: vmlal.u32 <r2=reg128#14,<v23=reg128#10%bot,<y0=reg128#1%bot 932# asm 2: vmlal.u32 <r2=q13,<v23=d18,<y0=d0 933vmlal.u32 q13,d18,d0 934 935# qhasm: r2[0,1] += v23[2] unsigned* 5y34[2]; r2[2,3] += v23[3] unsigned* 5y34[3] 936# asm 1: vmlal.u32 <r2=reg128#14,<v23=reg128#10%top,<5y34=reg128#13%top 937# asm 2: vmlal.u32 <r2=q13,<v23=d19,<5y34=d25 938vmlal.u32 q13,d19,d25 939 940# qhasm: r2[0,1] += v4[0] unsigned* 5y34[0]; r2[2,3] += v4[1] unsigned* 5y34[1] 941# asm 1: vmlal.u32 <r2=reg128#14,<v4=reg128#4%bot,<5y34=reg128#13%bot 942# asm 2: vmlal.u32 <r2=q13,<v4=d6,<5y34=d24 943vmlal.u32 q13,d6,d24 944 945# qhasm: ptr = &two24 946# asm 1: lea >ptr=int32#3,<two24=stack128#1 947# asm 2: lea >ptr=r2,<two24=[sp,#0] 948add r2,sp,#0 949 950# qhasm: 2x t1 = r0 unsigned>> 26 951# asm 1: vshr.u64 >t1=reg128#4,<r0=reg128#8,#26 952# asm 2: vshr.u64 >t1=q3,<r0=q7,#26 953vshr.u64 q3,q7,#26 954 955# qhasm: len -= 64 956# asm 1: sub >len=int32#4,<len=int32#4,#64 957# asm 2: sub >len=r3,<len=r3,#64 958sub r3,r3,#64 959 960# qhasm: r0 &= mask 961# asm 1: vand >r0=reg128#6,<r0=reg128#8,<mask=reg128#7 962# asm 2: vand >r0=q5,<r0=q7,<mask=q6 963vand q5,q7,q6 964 965# qhasm: 2x r1 += t1 966# asm 1: vadd.i64 >r1=reg128#4,<r1=reg128#15,<t1=reg128#4 967# asm 2: vadd.i64 >r1=q3,<r1=q14,<t1=q3 968vadd.i64 q3,q14,q3 969 970# qhasm: 2x t4 = r3 unsigned>> 26 971# asm 1: vshr.u64 >t4=reg128#8,<r3=reg128#5,#26 972# asm 2: vshr.u64 >t4=q7,<r3=q4,#26 973vshr.u64 q7,q4,#26 974 975# qhasm: r3 &= mask 976# asm 1: vand >r3=reg128#5,<r3=reg128#5,<mask=reg128#7 977# asm 2: vand >r3=q4,<r3=q4,<mask=q6 978vand q4,q4,q6 979 980# qhasm: 2x x4 = r4 + t4 981# asm 1: vadd.i64 >x4=reg128#8,<r4=reg128#16,<t4=reg128#8 982# asm 2: vadd.i64 >x4=q7,<r4=q15,<t4=q7 983vadd.i64 q7,q15,q7 984 985# qhasm: r4 aligned= mem128[ptr] 986# asm 1: vld1.8 {>r4=reg128#16%bot->r4=reg128#16%top},[<ptr=int32#3,: 128] 987# asm 2: vld1.8 {>r4=d30->r4=d31},[<ptr=r2,: 128] 988vld1.8 {d30-d31},[r2,: 128] 989 990# qhasm: 2x t2 = r1 unsigned>> 26 991# asm 1: vshr.u64 >t2=reg128#9,<r1=reg128#4,#26 992# asm 2: vshr.u64 >t2=q8,<r1=q3,#26 993vshr.u64 q8,q3,#26 994 995# qhasm: r1 &= mask 996# asm 1: vand >r1=reg128#4,<r1=reg128#4,<mask=reg128#7 997# asm 2: vand >r1=q3,<r1=q3,<mask=q6 998vand q3,q3,q6 999 1000# qhasm: 2x t0 = x4 unsigned>> 26 1001# asm 1: vshr.u64 >t0=reg128#10,<x4=reg128#8,#26 1002# asm 2: vshr.u64 >t0=q9,<x4=q7,#26 1003vshr.u64 q9,q7,#26 1004 1005# qhasm: 2x r2 += t2 1006# asm 1: vadd.i64 >r2=reg128#9,<r2=reg128#14,<t2=reg128#9 1007# asm 2: vadd.i64 >r2=q8,<r2=q13,<t2=q8 1008vadd.i64 q8,q13,q8 1009 1010# qhasm: x4 &= mask 1011# asm 1: vand >x4=reg128#11,<x4=reg128#8,<mask=reg128#7 1012# asm 2: vand >x4=q10,<x4=q7,<mask=q6 1013vand q10,q7,q6 1014 1015# qhasm: 2x x01 = r0 + t0 1016# asm 1: vadd.i64 >x01=reg128#6,<r0=reg128#6,<t0=reg128#10 1017# asm 2: vadd.i64 >x01=q5,<r0=q5,<t0=q9 1018vadd.i64 q5,q5,q9 1019 1020# qhasm: r0 aligned= mem128[ptr] 1021# asm 1: vld1.8 {>r0=reg128#8%bot->r0=reg128#8%top},[<ptr=int32#3,: 128] 1022# asm 2: vld1.8 {>r0=d14->r0=d15},[<ptr=r2,: 128] 1023vld1.8 {d14-d15},[r2,: 128] 1024 1025# qhasm: ptr = &z34_stack 1026# asm 1: lea >ptr=int32#3,<z34_stack=stack128#9 1027# asm 2: lea >ptr=r2,<z34_stack=[sp,#128] 1028add r2,sp,#128 1029 1030# qhasm: 2x t0 <<= 2 1031# asm 1: vshl.i64 >t0=reg128#10,<t0=reg128#10,#2 1032# asm 2: vshl.i64 >t0=q9,<t0=q9,#2 1033vshl.i64 q9,q9,#2 1034 1035# qhasm: 2x t3 = r2 unsigned>> 26 1036# asm 1: vshr.u64 >t3=reg128#14,<r2=reg128#9,#26 1037# asm 2: vshr.u64 >t3=q13,<r2=q8,#26 1038vshr.u64 q13,q8,#26 1039 1040# qhasm: 2x x01 += t0 1041# asm 1: vadd.i64 >x01=reg128#15,<x01=reg128#6,<t0=reg128#10 1042# asm 2: vadd.i64 >x01=q14,<x01=q5,<t0=q9 1043vadd.i64 q14,q5,q9 1044 1045# qhasm: z34 aligned= mem128[ptr] 1046# asm 1: vld1.8 {>z34=reg128#6%bot->z34=reg128#6%top},[<ptr=int32#3,: 128] 1047# asm 2: vld1.8 {>z34=d10->z34=d11},[<ptr=r2,: 128] 1048vld1.8 {d10-d11},[r2,: 128] 1049 1050# qhasm: x23 = r2 & mask 1051# asm 1: vand >x23=reg128#10,<r2=reg128#9,<mask=reg128#7 1052# asm 2: vand >x23=q9,<r2=q8,<mask=q6 1053vand q9,q8,q6 1054 1055# qhasm: 2x r3 += t3 1056# asm 1: vadd.i64 >r3=reg128#5,<r3=reg128#5,<t3=reg128#14 1057# asm 2: vadd.i64 >r3=q4,<r3=q4,<t3=q13 1058vadd.i64 q4,q4,q13 1059 1060# qhasm: input_2 += 32 1061# asm 1: add >input_2=int32#2,<input_2=int32#2,#32 1062# asm 2: add >input_2=r1,<input_2=r1,#32 1063add r1,r1,#32 1064 1065# qhasm: 2x t1 = x01 unsigned>> 26 1066# asm 1: vshr.u64 >t1=reg128#14,<x01=reg128#15,#26 1067# asm 2: vshr.u64 >t1=q13,<x01=q14,#26 1068vshr.u64 q13,q14,#26 1069 1070# qhasm: x23 = x23[0,2,1,3] 1071# asm 1: vtrn.32 <x23=reg128#10%bot,<x23=reg128#10%top 1072# asm 2: vtrn.32 <x23=d18,<x23=d19 1073vtrn.32 d18,d19 1074 1075# qhasm: x01 = x01 & mask 1076# asm 1: vand >x01=reg128#9,<x01=reg128#15,<mask=reg128#7 1077# asm 2: vand >x01=q8,<x01=q14,<mask=q6 1078vand q8,q14,q6 1079 1080# qhasm: 2x r1 += t1 1081# asm 1: vadd.i64 >r1=reg128#4,<r1=reg128#4,<t1=reg128#14 1082# asm 2: vadd.i64 >r1=q3,<r1=q3,<t1=q13 1083vadd.i64 q3,q3,q13 1084 1085# qhasm: 2x t4 = r3 unsigned>> 26 1086# asm 1: vshr.u64 >t4=reg128#14,<r3=reg128#5,#26 1087# asm 2: vshr.u64 >t4=q13,<r3=q4,#26 1088vshr.u64 q13,q4,#26 1089 1090# qhasm: x01 = x01[0,2,1,3] 1091# asm 1: vtrn.32 <x01=reg128#9%bot,<x01=reg128#9%top 1092# asm 2: vtrn.32 <x01=d16,<x01=d17 1093vtrn.32 d16,d17 1094 1095# qhasm: r3 &= mask 1096# asm 1: vand >r3=reg128#5,<r3=reg128#5,<mask=reg128#7 1097# asm 2: vand >r3=q4,<r3=q4,<mask=q6 1098vand q4,q4,q6 1099 1100# qhasm: r1 = r1[0,2,1,3] 1101# asm 1: vtrn.32 <r1=reg128#4%bot,<r1=reg128#4%top 1102# asm 2: vtrn.32 <r1=d6,<r1=d7 1103vtrn.32 d6,d7 1104 1105# qhasm: 2x x4 += t4 1106# asm 1: vadd.i64 >x4=reg128#11,<x4=reg128#11,<t4=reg128#14 1107# asm 2: vadd.i64 >x4=q10,<x4=q10,<t4=q13 1108vadd.i64 q10,q10,q13 1109 1110# qhasm: r3 = r3[0,2,1,3] 1111# asm 1: vtrn.32 <r3=reg128#5%bot,<r3=reg128#5%top 1112# asm 2: vtrn.32 <r3=d8,<r3=d9 1113vtrn.32 d8,d9 1114 1115# qhasm: x01 = x01[0,1] r1[0,1] 1116# asm 1: vext.32 <x01=reg128#9%top,<r1=reg128#4%bot,<r1=reg128#4%bot,#0 1117# asm 2: vext.32 <x01=d17,<r1=d6,<r1=d6,#0 1118vext.32 d17,d6,d6,#0 1119 1120# qhasm: x23 = x23[0,1] r3[0,1] 1121# asm 1: vext.32 <x23=reg128#10%top,<r3=reg128#5%bot,<r3=reg128#5%bot,#0 1122# asm 2: vext.32 <x23=d19,<r3=d8,<r3=d8,#0 1123vext.32 d19,d8,d8,#0 1124 1125# qhasm: x4 = x4[0,2,1,3] 1126# asm 1: vtrn.32 <x4=reg128#11%bot,<x4=reg128#11%top 1127# asm 2: vtrn.32 <x4=d20,<x4=d21 1128vtrn.32 d20,d21 1129 1130# qhasm: unsigned>? len - 64 1131# asm 1: cmp <len=int32#4,#64 1132# asm 2: cmp <len=r3,#64 1133cmp r3,#64 1134 1135# qhasm: goto mainloop2 if unsigned> 1136bhi ._mainloop2 1137 1138# qhasm: input_2 -= 32 1139# asm 1: sub >input_2=int32#3,<input_2=int32#2,#32 1140# asm 2: sub >input_2=r2,<input_2=r1,#32 1141sub r2,r1,#32 1142 1143# qhasm: below64bytes: 1144._below64bytes: 1145 1146# qhasm: unsigned>? len - 32 1147# asm 1: cmp <len=int32#4,#32 1148# asm 2: cmp <len=r3,#32 1149cmp r3,#32 1150 1151# qhasm: goto end if !unsigned> 1152bls ._end 1153 1154# qhasm: mainloop: 1155._mainloop: 1156 1157# qhasm: new r0 1158 1159# qhasm: ptr = &two24 1160# asm 1: lea >ptr=int32#2,<two24=stack128#1 1161# asm 2: lea >ptr=r1,<two24=[sp,#0] 1162add r1,sp,#0 1163 1164# qhasm: r4 aligned= mem128[ptr] 1165# asm 1: vld1.8 {>r4=reg128#5%bot->r4=reg128#5%top},[<ptr=int32#2,: 128] 1166# asm 2: vld1.8 {>r4=d8->r4=d9},[<ptr=r1,: 128] 1167vld1.8 {d8-d9},[r1,: 128] 1168 1169# qhasm: u4 aligned= mem128[ptr] 1170# asm 1: vld1.8 {>u4=reg128#6%bot->u4=reg128#6%top},[<ptr=int32#2,: 128] 1171# asm 2: vld1.8 {>u4=d10->u4=d11},[<ptr=r1,: 128] 1172vld1.8 {d10-d11},[r1,: 128] 1173 1174# qhasm: c01 = mem128[input_2];input_2+=16 1175# asm 1: vld1.8 {>c01=reg128#8%bot->c01=reg128#8%top},[<input_2=int32#3]! 1176# asm 2: vld1.8 {>c01=d14->c01=d15},[<input_2=r2]! 1177vld1.8 {d14-d15},[r2]! 1178 1179# qhasm: r4[0,1] += x01[0] unsigned* y34[2]; r4[2,3] += x01[1] unsigned* y34[3] 1180# asm 1: vmlal.u32 <r4=reg128#5,<x01=reg128#9%bot,<y34=reg128#3%top 1181# asm 2: vmlal.u32 <r4=q4,<x01=d16,<y34=d5 1182vmlal.u32 q4,d16,d5 1183 1184# qhasm: c23 = mem128[input_2];input_2+=16 1185# asm 1: vld1.8 {>c23=reg128#14%bot->c23=reg128#14%top},[<input_2=int32#3]! 1186# asm 2: vld1.8 {>c23=d26->c23=d27},[<input_2=r2]! 1187vld1.8 {d26-d27},[r2]! 1188 1189# qhasm: r4[0,1] += x01[2] unsigned* y34[0]; r4[2,3] += x01[3] unsigned* y34[1] 1190# asm 1: vmlal.u32 <r4=reg128#5,<x01=reg128#9%top,<y34=reg128#3%bot 1191# asm 2: vmlal.u32 <r4=q4,<x01=d17,<y34=d4 1192vmlal.u32 q4,d17,d4 1193 1194# qhasm: r0 = u4[1]c01[0]r0[2,3] 1195# asm 1: vext.32 <r0=reg128#4%bot,<u4=reg128#6%bot,<c01=reg128#8%bot,#1 1196# asm 2: vext.32 <r0=d6,<u4=d10,<c01=d14,#1 1197vext.32 d6,d10,d14,#1 1198 1199# qhasm: r4[0,1] += x23[0] unsigned* y12[2]; r4[2,3] += x23[1] unsigned* y12[3] 1200# asm 1: vmlal.u32 <r4=reg128#5,<x23=reg128#10%bot,<y12=reg128#2%top 1201# asm 2: vmlal.u32 <r4=q4,<x23=d18,<y12=d3 1202vmlal.u32 q4,d18,d3 1203 1204# qhasm: r0 = r0[0,1]u4[1]c23[0] 1205# asm 1: vext.32 <r0=reg128#4%top,<u4=reg128#6%bot,<c23=reg128#14%bot,#1 1206# asm 2: vext.32 <r0=d7,<u4=d10,<c23=d26,#1 1207vext.32 d7,d10,d26,#1 1208 1209# qhasm: r4[0,1] += x23[2] unsigned* y12[0]; r4[2,3] += x23[3] unsigned* y12[1] 1210# asm 1: vmlal.u32 <r4=reg128#5,<x23=reg128#10%top,<y12=reg128#2%bot 1211# asm 2: vmlal.u32 <r4=q4,<x23=d19,<y12=d2 1212vmlal.u32 q4,d19,d2 1213 1214# qhasm: r0 = r0[1]r0[0]r0[3]r0[2] 1215# asm 1: vrev64.i32 >r0=reg128#4,<r0=reg128#4 1216# asm 2: vrev64.i32 >r0=q3,<r0=q3 1217vrev64.i32 q3,q3 1218 1219# qhasm: r4[0,1] += x4[0] unsigned* y0[0]; r4[2,3] += x4[1] unsigned* y0[1] 1220# asm 1: vmlal.u32 <r4=reg128#5,<x4=reg128#11%bot,<y0=reg128#1%bot 1221# asm 2: vmlal.u32 <r4=q4,<x4=d20,<y0=d0 1222vmlal.u32 q4,d20,d0 1223 1224# qhasm: r0[0,1] += x4[0] unsigned* 5y12[0]; r0[2,3] += x4[1] unsigned* 5y12[1] 1225# asm 1: vmlal.u32 <r0=reg128#4,<x4=reg128#11%bot,<5y12=reg128#12%bot 1226# asm 2: vmlal.u32 <r0=q3,<x4=d20,<5y12=d22 1227vmlal.u32 q3,d20,d22 1228 1229# qhasm: r0[0,1] += x23[0] unsigned* 5y34[0]; r0[2,3] += x23[1] unsigned* 5y34[1] 1230# asm 1: vmlal.u32 <r0=reg128#4,<x23=reg128#10%bot,<5y34=reg128#13%bot 1231# asm 2: vmlal.u32 <r0=q3,<x23=d18,<5y34=d24 1232vmlal.u32 q3,d18,d24 1233 1234# qhasm: r0[0,1] += x23[2] unsigned* 5y12[2]; r0[2,3] += x23[3] unsigned* 5y12[3] 1235# asm 1: vmlal.u32 <r0=reg128#4,<x23=reg128#10%top,<5y12=reg128#12%top 1236# asm 2: vmlal.u32 <r0=q3,<x23=d19,<5y12=d23 1237vmlal.u32 q3,d19,d23 1238 1239# qhasm: c01 c23 = c01[0]c23[0]c01[2]c23[2]c01[1]c23[1]c01[3]c23[3] 1240# asm 1: vtrn.32 <c01=reg128#8,<c23=reg128#14 1241# asm 2: vtrn.32 <c01=q7,<c23=q13 1242vtrn.32 q7,q13 1243 1244# qhasm: r0[0,1] += x01[0] unsigned* y0[0]; r0[2,3] += x01[1] unsigned* y0[1] 1245# asm 1: vmlal.u32 <r0=reg128#4,<x01=reg128#9%bot,<y0=reg128#1%bot 1246# asm 2: vmlal.u32 <r0=q3,<x01=d16,<y0=d0 1247vmlal.u32 q3,d16,d0 1248 1249# qhasm: r3[0,1] = c23[2]<<18; r3[2,3] = c23[3]<<18 1250# asm 1: vshll.u32 >r3=reg128#6,<c23=reg128#14%top,#18 1251# asm 2: vshll.u32 >r3=q5,<c23=d27,#18 1252vshll.u32 q5,d27,#18 1253 1254# qhasm: r0[0,1] += x01[2] unsigned* 5y34[2]; r0[2,3] += x01[3] unsigned* 5y34[3] 1255# asm 1: vmlal.u32 <r0=reg128#4,<x01=reg128#9%top,<5y34=reg128#13%top 1256# asm 2: vmlal.u32 <r0=q3,<x01=d17,<5y34=d25 1257vmlal.u32 q3,d17,d25 1258 1259# qhasm: r3[0,1] += x01[0] unsigned* y34[0]; r3[2,3] += x01[1] unsigned* y34[1] 1260# asm 1: vmlal.u32 <r3=reg128#6,<x01=reg128#9%bot,<y34=reg128#3%bot 1261# asm 2: vmlal.u32 <r3=q5,<x01=d16,<y34=d4 1262vmlal.u32 q5,d16,d4 1263 1264# qhasm: r3[0,1] += x01[2] unsigned* y12[2]; r3[2,3] += x01[3] unsigned* y12[3] 1265# asm 1: vmlal.u32 <r3=reg128#6,<x01=reg128#9%top,<y12=reg128#2%top 1266# asm 2: vmlal.u32 <r3=q5,<x01=d17,<y12=d3 1267vmlal.u32 q5,d17,d3 1268 1269# qhasm: r3[0,1] += x23[0] unsigned* y12[0]; r3[2,3] += x23[1] unsigned* y12[1] 1270# asm 1: vmlal.u32 <r3=reg128#6,<x23=reg128#10%bot,<y12=reg128#2%bot 1271# asm 2: vmlal.u32 <r3=q5,<x23=d18,<y12=d2 1272vmlal.u32 q5,d18,d2 1273 1274# qhasm: r3[0,1] += x23[2] unsigned* y0[0]; r3[2,3] += x23[3] unsigned* y0[1] 1275# asm 1: vmlal.u32 <r3=reg128#6,<x23=reg128#10%top,<y0=reg128#1%bot 1276# asm 2: vmlal.u32 <r3=q5,<x23=d19,<y0=d0 1277vmlal.u32 q5,d19,d0 1278 1279# qhasm: r1[0,1] = c23[0]<<6; r1[2,3] = c23[1]<<6 1280# asm 1: vshll.u32 >r1=reg128#14,<c23=reg128#14%bot,#6 1281# asm 2: vshll.u32 >r1=q13,<c23=d26,#6 1282vshll.u32 q13,d26,#6 1283 1284# qhasm: r3[0,1] += x4[0] unsigned* 5y34[2]; r3[2,3] += x4[1] unsigned* 5y34[3] 1285# asm 1: vmlal.u32 <r3=reg128#6,<x4=reg128#11%bot,<5y34=reg128#13%top 1286# asm 2: vmlal.u32 <r3=q5,<x4=d20,<5y34=d25 1287vmlal.u32 q5,d20,d25 1288 1289# qhasm: r1[0,1] += x01[0] unsigned* y12[0]; r1[2,3] += x01[1] unsigned* y12[1] 1290# asm 1: vmlal.u32 <r1=reg128#14,<x01=reg128#9%bot,<y12=reg128#2%bot 1291# asm 2: vmlal.u32 <r1=q13,<x01=d16,<y12=d2 1292vmlal.u32 q13,d16,d2 1293 1294# qhasm: r1[0,1] += x01[2] unsigned* y0[0]; r1[2,3] += x01[3] unsigned* y0[1] 1295# asm 1: vmlal.u32 <r1=reg128#14,<x01=reg128#9%top,<y0=reg128#1%bot 1296# asm 2: vmlal.u32 <r1=q13,<x01=d17,<y0=d0 1297vmlal.u32 q13,d17,d0 1298 1299# qhasm: r1[0,1] += x23[0] unsigned* 5y34[2]; r1[2,3] += x23[1] unsigned* 5y34[3] 1300# asm 1: vmlal.u32 <r1=reg128#14,<x23=reg128#10%bot,<5y34=reg128#13%top 1301# asm 2: vmlal.u32 <r1=q13,<x23=d18,<5y34=d25 1302vmlal.u32 q13,d18,d25 1303 1304# qhasm: r1[0,1] += x23[2] unsigned* 5y34[0]; r1[2,3] += x23[3] unsigned* 5y34[1] 1305# asm 1: vmlal.u32 <r1=reg128#14,<x23=reg128#10%top,<5y34=reg128#13%bot 1306# asm 2: vmlal.u32 <r1=q13,<x23=d19,<5y34=d24 1307vmlal.u32 q13,d19,d24 1308 1309# qhasm: r2[0,1] = c01[2]<<12; r2[2,3] = c01[3]<<12 1310# asm 1: vshll.u32 >r2=reg128#8,<c01=reg128#8%top,#12 1311# asm 2: vshll.u32 >r2=q7,<c01=d15,#12 1312vshll.u32 q7,d15,#12 1313 1314# qhasm: r1[0,1] += x4[0] unsigned* 5y12[2]; r1[2,3] += x4[1] unsigned* 5y12[3] 1315# asm 1: vmlal.u32 <r1=reg128#14,<x4=reg128#11%bot,<5y12=reg128#12%top 1316# asm 2: vmlal.u32 <r1=q13,<x4=d20,<5y12=d23 1317vmlal.u32 q13,d20,d23 1318 1319# qhasm: r2[0,1] += x01[0] unsigned* y12[2]; r2[2,3] += x01[1] unsigned* y12[3] 1320# asm 1: vmlal.u32 <r2=reg128#8,<x01=reg128#9%bot,<y12=reg128#2%top 1321# asm 2: vmlal.u32 <r2=q7,<x01=d16,<y12=d3 1322vmlal.u32 q7,d16,d3 1323 1324# qhasm: r2[0,1] += x01[2] unsigned* y12[0]; r2[2,3] += x01[3] unsigned* y12[1] 1325# asm 1: vmlal.u32 <r2=reg128#8,<x01=reg128#9%top,<y12=reg128#2%bot 1326# asm 2: vmlal.u32 <r2=q7,<x01=d17,<y12=d2 1327vmlal.u32 q7,d17,d2 1328 1329# qhasm: r2[0,1] += x23[0] unsigned* y0[0]; r2[2,3] += x23[1] unsigned* y0[1] 1330# asm 1: vmlal.u32 <r2=reg128#8,<x23=reg128#10%bot,<y0=reg128#1%bot 1331# asm 2: vmlal.u32 <r2=q7,<x23=d18,<y0=d0 1332vmlal.u32 q7,d18,d0 1333 1334# qhasm: r2[0,1] += x23[2] unsigned* 5y34[2]; r2[2,3] += x23[3] unsigned* 5y34[3] 1335# asm 1: vmlal.u32 <r2=reg128#8,<x23=reg128#10%top,<5y34=reg128#13%top 1336# asm 2: vmlal.u32 <r2=q7,<x23=d19,<5y34=d25 1337vmlal.u32 q7,d19,d25 1338 1339# qhasm: r2[0,1] += x4[0] unsigned* 5y34[0]; r2[2,3] += x4[1] unsigned* 5y34[1] 1340# asm 1: vmlal.u32 <r2=reg128#8,<x4=reg128#11%bot,<5y34=reg128#13%bot 1341# asm 2: vmlal.u32 <r2=q7,<x4=d20,<5y34=d24 1342vmlal.u32 q7,d20,d24 1343 1344# qhasm: 2x t1 = r0 unsigned>> 26 1345# asm 1: vshr.u64 >t1=reg128#9,<r0=reg128#4,#26 1346# asm 2: vshr.u64 >t1=q8,<r0=q3,#26 1347vshr.u64 q8,q3,#26 1348 1349# qhasm: r0 &= mask 1350# asm 1: vand >r0=reg128#4,<r0=reg128#4,<mask=reg128#7 1351# asm 2: vand >r0=q3,<r0=q3,<mask=q6 1352vand q3,q3,q6 1353 1354# qhasm: 2x r1 += t1 1355# asm 1: vadd.i64 >r1=reg128#9,<r1=reg128#14,<t1=reg128#9 1356# asm 2: vadd.i64 >r1=q8,<r1=q13,<t1=q8 1357vadd.i64 q8,q13,q8 1358 1359# qhasm: 2x t4 = r3 unsigned>> 26 1360# asm 1: vshr.u64 >t4=reg128#10,<r3=reg128#6,#26 1361# asm 2: vshr.u64 >t4=q9,<r3=q5,#26 1362vshr.u64 q9,q5,#26 1363 1364# qhasm: r3 &= mask 1365# asm 1: vand >r3=reg128#6,<r3=reg128#6,<mask=reg128#7 1366# asm 2: vand >r3=q5,<r3=q5,<mask=q6 1367vand q5,q5,q6 1368 1369# qhasm: 2x r4 += t4 1370# asm 1: vadd.i64 >r4=reg128#5,<r4=reg128#5,<t4=reg128#10 1371# asm 2: vadd.i64 >r4=q4,<r4=q4,<t4=q9 1372vadd.i64 q4,q4,q9 1373 1374# qhasm: 2x t2 = r1 unsigned>> 26 1375# asm 1: vshr.u64 >t2=reg128#10,<r1=reg128#9,#26 1376# asm 2: vshr.u64 >t2=q9,<r1=q8,#26 1377vshr.u64 q9,q8,#26 1378 1379# qhasm: r1 &= mask 1380# asm 1: vand >r1=reg128#11,<r1=reg128#9,<mask=reg128#7 1381# asm 2: vand >r1=q10,<r1=q8,<mask=q6 1382vand q10,q8,q6 1383 1384# qhasm: 2x t0 = r4 unsigned>> 26 1385# asm 1: vshr.u64 >t0=reg128#9,<r4=reg128#5,#26 1386# asm 2: vshr.u64 >t0=q8,<r4=q4,#26 1387vshr.u64 q8,q4,#26 1388 1389# qhasm: 2x r2 += t2 1390# asm 1: vadd.i64 >r2=reg128#8,<r2=reg128#8,<t2=reg128#10 1391# asm 2: vadd.i64 >r2=q7,<r2=q7,<t2=q9 1392vadd.i64 q7,q7,q9 1393 1394# qhasm: r4 &= mask 1395# asm 1: vand >r4=reg128#5,<r4=reg128#5,<mask=reg128#7 1396# asm 2: vand >r4=q4,<r4=q4,<mask=q6 1397vand q4,q4,q6 1398 1399# qhasm: 2x r0 += t0 1400# asm 1: vadd.i64 >r0=reg128#4,<r0=reg128#4,<t0=reg128#9 1401# asm 2: vadd.i64 >r0=q3,<r0=q3,<t0=q8 1402vadd.i64 q3,q3,q8 1403 1404# qhasm: 2x t0 <<= 2 1405# asm 1: vshl.i64 >t0=reg128#9,<t0=reg128#9,#2 1406# asm 2: vshl.i64 >t0=q8,<t0=q8,#2 1407vshl.i64 q8,q8,#2 1408 1409# qhasm: 2x t3 = r2 unsigned>> 26 1410# asm 1: vshr.u64 >t3=reg128#14,<r2=reg128#8,#26 1411# asm 2: vshr.u64 >t3=q13,<r2=q7,#26 1412vshr.u64 q13,q7,#26 1413 1414# qhasm: 2x r0 += t0 1415# asm 1: vadd.i64 >r0=reg128#4,<r0=reg128#4,<t0=reg128#9 1416# asm 2: vadd.i64 >r0=q3,<r0=q3,<t0=q8 1417vadd.i64 q3,q3,q8 1418 1419# qhasm: x23 = r2 & mask 1420# asm 1: vand >x23=reg128#10,<r2=reg128#8,<mask=reg128#7 1421# asm 2: vand >x23=q9,<r2=q7,<mask=q6 1422vand q9,q7,q6 1423 1424# qhasm: 2x r3 += t3 1425# asm 1: vadd.i64 >r3=reg128#6,<r3=reg128#6,<t3=reg128#14 1426# asm 2: vadd.i64 >r3=q5,<r3=q5,<t3=q13 1427vadd.i64 q5,q5,q13 1428 1429# qhasm: 2x t1 = r0 unsigned>> 26 1430# asm 1: vshr.u64 >t1=reg128#8,<r0=reg128#4,#26 1431# asm 2: vshr.u64 >t1=q7,<r0=q3,#26 1432vshr.u64 q7,q3,#26 1433 1434# qhasm: x01 = r0 & mask 1435# asm 1: vand >x01=reg128#9,<r0=reg128#4,<mask=reg128#7 1436# asm 2: vand >x01=q8,<r0=q3,<mask=q6 1437vand q8,q3,q6 1438 1439# qhasm: 2x r1 += t1 1440# asm 1: vadd.i64 >r1=reg128#4,<r1=reg128#11,<t1=reg128#8 1441# asm 2: vadd.i64 >r1=q3,<r1=q10,<t1=q7 1442vadd.i64 q3,q10,q7 1443 1444# qhasm: 2x t4 = r3 unsigned>> 26 1445# asm 1: vshr.u64 >t4=reg128#8,<r3=reg128#6,#26 1446# asm 2: vshr.u64 >t4=q7,<r3=q5,#26 1447vshr.u64 q7,q5,#26 1448 1449# qhasm: r3 &= mask 1450# asm 1: vand >r3=reg128#6,<r3=reg128#6,<mask=reg128#7 1451# asm 2: vand >r3=q5,<r3=q5,<mask=q6 1452vand q5,q5,q6 1453 1454# qhasm: 2x x4 = r4 + t4 1455# asm 1: vadd.i64 >x4=reg128#11,<r4=reg128#5,<t4=reg128#8 1456# asm 2: vadd.i64 >x4=q10,<r4=q4,<t4=q7 1457vadd.i64 q10,q4,q7 1458 1459# qhasm: len -= 32 1460# asm 1: sub >len=int32#4,<len=int32#4,#32 1461# asm 2: sub >len=r3,<len=r3,#32 1462sub r3,r3,#32 1463 1464# qhasm: x01 = x01[0,2,1,3] 1465# asm 1: vtrn.32 <x01=reg128#9%bot,<x01=reg128#9%top 1466# asm 2: vtrn.32 <x01=d16,<x01=d17 1467vtrn.32 d16,d17 1468 1469# qhasm: x23 = x23[0,2,1,3] 1470# asm 1: vtrn.32 <x23=reg128#10%bot,<x23=reg128#10%top 1471# asm 2: vtrn.32 <x23=d18,<x23=d19 1472vtrn.32 d18,d19 1473 1474# qhasm: r1 = r1[0,2,1,3] 1475# asm 1: vtrn.32 <r1=reg128#4%bot,<r1=reg128#4%top 1476# asm 2: vtrn.32 <r1=d6,<r1=d7 1477vtrn.32 d6,d7 1478 1479# qhasm: r3 = r3[0,2,1,3] 1480# asm 1: vtrn.32 <r3=reg128#6%bot,<r3=reg128#6%top 1481# asm 2: vtrn.32 <r3=d10,<r3=d11 1482vtrn.32 d10,d11 1483 1484# qhasm: x4 = x4[0,2,1,3] 1485# asm 1: vtrn.32 <x4=reg128#11%bot,<x4=reg128#11%top 1486# asm 2: vtrn.32 <x4=d20,<x4=d21 1487vtrn.32 d20,d21 1488 1489# qhasm: x01 = x01[0,1] r1[0,1] 1490# asm 1: vext.32 <x01=reg128#9%top,<r1=reg128#4%bot,<r1=reg128#4%bot,#0 1491# asm 2: vext.32 <x01=d17,<r1=d6,<r1=d6,#0 1492vext.32 d17,d6,d6,#0 1493 1494# qhasm: x23 = x23[0,1] r3[0,1] 1495# asm 1: vext.32 <x23=reg128#10%top,<r3=reg128#6%bot,<r3=reg128#6%bot,#0 1496# asm 2: vext.32 <x23=d19,<r3=d10,<r3=d10,#0 1497vext.32 d19,d10,d10,#0 1498 1499# qhasm: unsigned>? len - 32 1500# asm 1: cmp <len=int32#4,#32 1501# asm 2: cmp <len=r3,#32 1502cmp r3,#32 1503 1504# qhasm: goto mainloop if unsigned> 1505bhi ._mainloop 1506 1507# qhasm: end: 1508._end: 1509 1510# qhasm: mem128[input_0] = x01;input_0+=16 1511# asm 1: vst1.8 {<x01=reg128#9%bot-<x01=reg128#9%top},[<input_0=int32#1]! 1512# asm 2: vst1.8 {<x01=d16-<x01=d17},[<input_0=r0]! 1513vst1.8 {d16-d17},[r0]! 1514 1515# qhasm: mem128[input_0] = x23;input_0+=16 1516# asm 1: vst1.8 {<x23=reg128#10%bot-<x23=reg128#10%top},[<input_0=int32#1]! 1517# asm 2: vst1.8 {<x23=d18-<x23=d19},[<input_0=r0]! 1518vst1.8 {d18-d19},[r0]! 1519 1520# qhasm: mem64[input_0] = x4[0] 1521# asm 1: vst1.8 <x4=reg128#11%bot,[<input_0=int32#1] 1522# asm 2: vst1.8 <x4=d20,[<input_0=r0] 1523vst1.8 d20,[r0] 1524 1525# qhasm: len = len 1526# asm 1: mov >len=int32#1,<len=int32#4 1527# asm 2: mov >len=r0,<len=r3 1528mov r0,r3 1529 1530# qhasm: qpopreturn len 1531mov sp,r12 1532vpop {q4,q5,q6,q7} 1533bx lr 1534 1535# qhasm: int32 input_0 1536 1537# qhasm: int32 input_1 1538 1539# qhasm: int32 input_2 1540 1541# qhasm: int32 input_3 1542 1543# qhasm: stack32 input_4 1544 1545# qhasm: stack32 input_5 1546 1547# qhasm: stack32 input_6 1548 1549# qhasm: stack32 input_7 1550 1551# qhasm: int32 caller_r4 1552 1553# qhasm: int32 caller_r5 1554 1555# qhasm: int32 caller_r6 1556 1557# qhasm: int32 caller_r7 1558 1559# qhasm: int32 caller_r8 1560 1561# qhasm: int32 caller_r9 1562 1563# qhasm: int32 caller_r10 1564 1565# qhasm: int32 caller_r11 1566 1567# qhasm: int32 caller_r12 1568 1569# qhasm: int32 caller_r14 1570 1571# qhasm: reg128 caller_q4 1572 1573# qhasm: reg128 caller_q5 1574 1575# qhasm: reg128 caller_q6 1576 1577# qhasm: reg128 caller_q7 1578 1579# qhasm: reg128 r0 1580 1581# qhasm: reg128 r1 1582 1583# qhasm: reg128 r2 1584 1585# qhasm: reg128 r3 1586 1587# qhasm: reg128 r4 1588 1589# qhasm: reg128 x01 1590 1591# qhasm: reg128 x23 1592 1593# qhasm: reg128 x4 1594 1595# qhasm: reg128 y01 1596 1597# qhasm: reg128 y23 1598 1599# qhasm: reg128 y4 1600 1601# qhasm: reg128 _5y01 1602 1603# qhasm: reg128 _5y23 1604 1605# qhasm: reg128 _5y4 1606 1607# qhasm: reg128 c01 1608 1609# qhasm: reg128 c23 1610 1611# qhasm: reg128 c4 1612 1613# qhasm: reg128 t0 1614 1615# qhasm: reg128 t1 1616 1617# qhasm: reg128 t2 1618 1619# qhasm: reg128 t3 1620 1621# qhasm: reg128 t4 1622 1623# qhasm: reg128 mask 1624 1625# qhasm: enter crypto_onetimeauth_poly1305_neon2_addmulmod 1626.align 2 1627.global GFp_poly1305_neon2_addmulmod 1628.hidden GFp_poly1305_neon2_addmulmod 1629.type GFp_poly1305_neon2_addmulmod STT_FUNC 1630GFp_poly1305_neon2_addmulmod: 1631sub sp,sp,#0 1632 1633# qhasm: 2x mask = 0xffffffff 1634# asm 1: vmov.i64 >mask=reg128#1,#0xffffffff 1635# asm 2: vmov.i64 >mask=q0,#0xffffffff 1636vmov.i64 q0,#0xffffffff 1637 1638# qhasm: y01 aligned= mem128[input_2];input_2+=16 1639# asm 1: vld1.8 {>y01=reg128#2%bot->y01=reg128#2%top},[<input_2=int32#3,: 128]! 1640# asm 2: vld1.8 {>y01=d2->y01=d3},[<input_2=r2,: 128]! 1641vld1.8 {d2-d3},[r2,: 128]! 1642 1643# qhasm: 4x _5y01 = y01 << 2 1644# asm 1: vshl.i32 >_5y01=reg128#3,<y01=reg128#2,#2 1645# asm 2: vshl.i32 >_5y01=q2,<y01=q1,#2 1646vshl.i32 q2,q1,#2 1647 1648# qhasm: y23 aligned= mem128[input_2];input_2+=16 1649# asm 1: vld1.8 {>y23=reg128#4%bot->y23=reg128#4%top},[<input_2=int32#3,: 128]! 1650# asm 2: vld1.8 {>y23=d6->y23=d7},[<input_2=r2,: 128]! 1651vld1.8 {d6-d7},[r2,: 128]! 1652 1653# qhasm: 4x _5y23 = y23 << 2 1654# asm 1: vshl.i32 >_5y23=reg128#9,<y23=reg128#4,#2 1655# asm 2: vshl.i32 >_5y23=q8,<y23=q3,#2 1656vshl.i32 q8,q3,#2 1657 1658# qhasm: y4 aligned= mem64[input_2]y4[1] 1659# asm 1: vld1.8 {<y4=reg128#10%bot},[<input_2=int32#3,: 64] 1660# asm 2: vld1.8 {<y4=d18},[<input_2=r2,: 64] 1661vld1.8 {d18},[r2,: 64] 1662 1663# qhasm: 4x _5y4 = y4 << 2 1664# asm 1: vshl.i32 >_5y4=reg128#11,<y4=reg128#10,#2 1665# asm 2: vshl.i32 >_5y4=q10,<y4=q9,#2 1666vshl.i32 q10,q9,#2 1667 1668# qhasm: x01 aligned= mem128[input_1];input_1+=16 1669# asm 1: vld1.8 {>x01=reg128#12%bot->x01=reg128#12%top},[<input_1=int32#2,: 128]! 1670# asm 2: vld1.8 {>x01=d22->x01=d23},[<input_1=r1,: 128]! 1671vld1.8 {d22-d23},[r1,: 128]! 1672 1673# qhasm: 4x _5y01 += y01 1674# asm 1: vadd.i32 >_5y01=reg128#3,<_5y01=reg128#3,<y01=reg128#2 1675# asm 2: vadd.i32 >_5y01=q2,<_5y01=q2,<y01=q1 1676vadd.i32 q2,q2,q1 1677 1678# qhasm: x23 aligned= mem128[input_1];input_1+=16 1679# asm 1: vld1.8 {>x23=reg128#13%bot->x23=reg128#13%top},[<input_1=int32#2,: 128]! 1680# asm 2: vld1.8 {>x23=d24->x23=d25},[<input_1=r1,: 128]! 1681vld1.8 {d24-d25},[r1,: 128]! 1682 1683# qhasm: 4x _5y23 += y23 1684# asm 1: vadd.i32 >_5y23=reg128#9,<_5y23=reg128#9,<y23=reg128#4 1685# asm 2: vadd.i32 >_5y23=q8,<_5y23=q8,<y23=q3 1686vadd.i32 q8,q8,q3 1687 1688# qhasm: 4x _5y4 += y4 1689# asm 1: vadd.i32 >_5y4=reg128#11,<_5y4=reg128#11,<y4=reg128#10 1690# asm 2: vadd.i32 >_5y4=q10,<_5y4=q10,<y4=q9 1691vadd.i32 q10,q10,q9 1692 1693# qhasm: c01 aligned= mem128[input_3];input_3+=16 1694# asm 1: vld1.8 {>c01=reg128#14%bot->c01=reg128#14%top},[<input_3=int32#4,: 128]! 1695# asm 2: vld1.8 {>c01=d26->c01=d27},[<input_3=r3,: 128]! 1696vld1.8 {d26-d27},[r3,: 128]! 1697 1698# qhasm: 4x x01 += c01 1699# asm 1: vadd.i32 >x01=reg128#12,<x01=reg128#12,<c01=reg128#14 1700# asm 2: vadd.i32 >x01=q11,<x01=q11,<c01=q13 1701vadd.i32 q11,q11,q13 1702 1703# qhasm: c23 aligned= mem128[input_3];input_3+=16 1704# asm 1: vld1.8 {>c23=reg128#14%bot->c23=reg128#14%top},[<input_3=int32#4,: 128]! 1705# asm 2: vld1.8 {>c23=d26->c23=d27},[<input_3=r3,: 128]! 1706vld1.8 {d26-d27},[r3,: 128]! 1707 1708# qhasm: 4x x23 += c23 1709# asm 1: vadd.i32 >x23=reg128#13,<x23=reg128#13,<c23=reg128#14 1710# asm 2: vadd.i32 >x23=q12,<x23=q12,<c23=q13 1711vadd.i32 q12,q12,q13 1712 1713# qhasm: x4 aligned= mem64[input_1]x4[1] 1714# asm 1: vld1.8 {<x4=reg128#14%bot},[<input_1=int32#2,: 64] 1715# asm 2: vld1.8 {<x4=d26},[<input_1=r1,: 64] 1716vld1.8 {d26},[r1,: 64] 1717 1718# qhasm: 2x mask unsigned>>=6 1719# asm 1: vshr.u64 >mask=reg128#1,<mask=reg128#1,#6 1720# asm 2: vshr.u64 >mask=q0,<mask=q0,#6 1721vshr.u64 q0,q0,#6 1722 1723# qhasm: c4 aligned= mem64[input_3]c4[1] 1724# asm 1: vld1.8 {<c4=reg128#15%bot},[<input_3=int32#4,: 64] 1725# asm 2: vld1.8 {<c4=d28},[<input_3=r3,: 64] 1726vld1.8 {d28},[r3,: 64] 1727 1728# qhasm: 4x x4 += c4 1729# asm 1: vadd.i32 >x4=reg128#14,<x4=reg128#14,<c4=reg128#15 1730# asm 2: vadd.i32 >x4=q13,<x4=q13,<c4=q14 1731vadd.i32 q13,q13,q14 1732 1733# qhasm: r0[0,1] = x01[0] unsigned* y01[0]; r0[2,3] = x01[1] unsigned* y01[1] 1734# asm 1: vmull.u32 >r0=reg128#15,<x01=reg128#12%bot,<y01=reg128#2%bot 1735# asm 2: vmull.u32 >r0=q14,<x01=d22,<y01=d2 1736vmull.u32 q14,d22,d2 1737 1738# qhasm: r0[0,1] += x01[2] unsigned* _5y4[0]; r0[2,3] += x01[3] unsigned* _5y4[1] 1739# asm 1: vmlal.u32 <r0=reg128#15,<x01=reg128#12%top,<_5y4=reg128#11%bot 1740# asm 2: vmlal.u32 <r0=q14,<x01=d23,<_5y4=d20 1741vmlal.u32 q14,d23,d20 1742 1743# qhasm: r0[0,1] += x23[0] unsigned* _5y23[2]; r0[2,3] += x23[1] unsigned* _5y23[3] 1744# asm 1: vmlal.u32 <r0=reg128#15,<x23=reg128#13%bot,<_5y23=reg128#9%top 1745# asm 2: vmlal.u32 <r0=q14,<x23=d24,<_5y23=d17 1746vmlal.u32 q14,d24,d17 1747 1748# qhasm: r0[0,1] += x23[2] unsigned* _5y23[0]; r0[2,3] += x23[3] unsigned* _5y23[1] 1749# asm 1: vmlal.u32 <r0=reg128#15,<x23=reg128#13%top,<_5y23=reg128#9%bot 1750# asm 2: vmlal.u32 <r0=q14,<x23=d25,<_5y23=d16 1751vmlal.u32 q14,d25,d16 1752 1753# qhasm: r0[0,1] += x4[0] unsigned* _5y01[2]; r0[2,3] += x4[1] unsigned* _5y01[3] 1754# asm 1: vmlal.u32 <r0=reg128#15,<x4=reg128#14%bot,<_5y01=reg128#3%top 1755# asm 2: vmlal.u32 <r0=q14,<x4=d26,<_5y01=d5 1756vmlal.u32 q14,d26,d5 1757 1758# qhasm: r1[0,1] = x01[0] unsigned* y01[2]; r1[2,3] = x01[1] unsigned* y01[3] 1759# asm 1: vmull.u32 >r1=reg128#3,<x01=reg128#12%bot,<y01=reg128#2%top 1760# asm 2: vmull.u32 >r1=q2,<x01=d22,<y01=d3 1761vmull.u32 q2,d22,d3 1762 1763# qhasm: r1[0,1] += x01[2] unsigned* y01[0]; r1[2,3] += x01[3] unsigned* y01[1] 1764# asm 1: vmlal.u32 <r1=reg128#3,<x01=reg128#12%top,<y01=reg128#2%bot 1765# asm 2: vmlal.u32 <r1=q2,<x01=d23,<y01=d2 1766vmlal.u32 q2,d23,d2 1767 1768# qhasm: r1[0,1] += x23[0] unsigned* _5y4[0]; r1[2,3] += x23[1] unsigned* _5y4[1] 1769# asm 1: vmlal.u32 <r1=reg128#3,<x23=reg128#13%bot,<_5y4=reg128#11%bot 1770# asm 2: vmlal.u32 <r1=q2,<x23=d24,<_5y4=d20 1771vmlal.u32 q2,d24,d20 1772 1773# qhasm: r1[0,1] += x23[2] unsigned* _5y23[2]; r1[2,3] += x23[3] unsigned* _5y23[3] 1774# asm 1: vmlal.u32 <r1=reg128#3,<x23=reg128#13%top,<_5y23=reg128#9%top 1775# asm 2: vmlal.u32 <r1=q2,<x23=d25,<_5y23=d17 1776vmlal.u32 q2,d25,d17 1777 1778# qhasm: r1[0,1] += x4[0] unsigned* _5y23[0]; r1[2,3] += x4[1] unsigned* _5y23[1] 1779# asm 1: vmlal.u32 <r1=reg128#3,<x4=reg128#14%bot,<_5y23=reg128#9%bot 1780# asm 2: vmlal.u32 <r1=q2,<x4=d26,<_5y23=d16 1781vmlal.u32 q2,d26,d16 1782 1783# qhasm: r2[0,1] = x01[0] unsigned* y23[0]; r2[2,3] = x01[1] unsigned* y23[1] 1784# asm 1: vmull.u32 >r2=reg128#16,<x01=reg128#12%bot,<y23=reg128#4%bot 1785# asm 2: vmull.u32 >r2=q15,<x01=d22,<y23=d6 1786vmull.u32 q15,d22,d6 1787 1788# qhasm: r2[0,1] += x01[2] unsigned* y01[2]; r2[2,3] += x01[3] unsigned* y01[3] 1789# asm 1: vmlal.u32 <r2=reg128#16,<x01=reg128#12%top,<y01=reg128#2%top 1790# asm 2: vmlal.u32 <r2=q15,<x01=d23,<y01=d3 1791vmlal.u32 q15,d23,d3 1792 1793# qhasm: r2[0,1] += x23[0] unsigned* y01[0]; r2[2,3] += x23[1] unsigned* y01[1] 1794# asm 1: vmlal.u32 <r2=reg128#16,<x23=reg128#13%bot,<y01=reg128#2%bot 1795# asm 2: vmlal.u32 <r2=q15,<x23=d24,<y01=d2 1796vmlal.u32 q15,d24,d2 1797 1798# qhasm: r2[0,1] += x23[2] unsigned* _5y4[0]; r2[2,3] += x23[3] unsigned* _5y4[1] 1799# asm 1: vmlal.u32 <r2=reg128#16,<x23=reg128#13%top,<_5y4=reg128#11%bot 1800# asm 2: vmlal.u32 <r2=q15,<x23=d25,<_5y4=d20 1801vmlal.u32 q15,d25,d20 1802 1803# qhasm: r2[0,1] += x4[0] unsigned* _5y23[2]; r2[2,3] += x4[1] unsigned* _5y23[3] 1804# asm 1: vmlal.u32 <r2=reg128#16,<x4=reg128#14%bot,<_5y23=reg128#9%top 1805# asm 2: vmlal.u32 <r2=q15,<x4=d26,<_5y23=d17 1806vmlal.u32 q15,d26,d17 1807 1808# qhasm: r3[0,1] = x01[0] unsigned* y23[2]; r3[2,3] = x01[1] unsigned* y23[3] 1809# asm 1: vmull.u32 >r3=reg128#9,<x01=reg128#12%bot,<y23=reg128#4%top 1810# asm 2: vmull.u32 >r3=q8,<x01=d22,<y23=d7 1811vmull.u32 q8,d22,d7 1812 1813# qhasm: r3[0,1] += x01[2] unsigned* y23[0]; r3[2,3] += x01[3] unsigned* y23[1] 1814# asm 1: vmlal.u32 <r3=reg128#9,<x01=reg128#12%top,<y23=reg128#4%bot 1815# asm 2: vmlal.u32 <r3=q8,<x01=d23,<y23=d6 1816vmlal.u32 q8,d23,d6 1817 1818# qhasm: r3[0,1] += x23[0] unsigned* y01[2]; r3[2,3] += x23[1] unsigned* y01[3] 1819# asm 1: vmlal.u32 <r3=reg128#9,<x23=reg128#13%bot,<y01=reg128#2%top 1820# asm 2: vmlal.u32 <r3=q8,<x23=d24,<y01=d3 1821vmlal.u32 q8,d24,d3 1822 1823# qhasm: r3[0,1] += x23[2] unsigned* y01[0]; r3[2,3] += x23[3] unsigned* y01[1] 1824# asm 1: vmlal.u32 <r3=reg128#9,<x23=reg128#13%top,<y01=reg128#2%bot 1825# asm 2: vmlal.u32 <r3=q8,<x23=d25,<y01=d2 1826vmlal.u32 q8,d25,d2 1827 1828# qhasm: r3[0,1] += x4[0] unsigned* _5y4[0]; r3[2,3] += x4[1] unsigned* _5y4[1] 1829# asm 1: vmlal.u32 <r3=reg128#9,<x4=reg128#14%bot,<_5y4=reg128#11%bot 1830# asm 2: vmlal.u32 <r3=q8,<x4=d26,<_5y4=d20 1831vmlal.u32 q8,d26,d20 1832 1833# qhasm: r4[0,1] = x01[0] unsigned* y4[0]; r4[2,3] = x01[1] unsigned* y4[1] 1834# asm 1: vmull.u32 >r4=reg128#10,<x01=reg128#12%bot,<y4=reg128#10%bot 1835# asm 2: vmull.u32 >r4=q9,<x01=d22,<y4=d18 1836vmull.u32 q9,d22,d18 1837 1838# qhasm: r4[0,1] += x01[2] unsigned* y23[2]; r4[2,3] += x01[3] unsigned* y23[3] 1839# asm 1: vmlal.u32 <r4=reg128#10,<x01=reg128#12%top,<y23=reg128#4%top 1840# asm 2: vmlal.u32 <r4=q9,<x01=d23,<y23=d7 1841vmlal.u32 q9,d23,d7 1842 1843# qhasm: r4[0,1] += x23[0] unsigned* y23[0]; r4[2,3] += x23[1] unsigned* y23[1] 1844# asm 1: vmlal.u32 <r4=reg128#10,<x23=reg128#13%bot,<y23=reg128#4%bot 1845# asm 2: vmlal.u32 <r4=q9,<x23=d24,<y23=d6 1846vmlal.u32 q9,d24,d6 1847 1848# qhasm: r4[0,1] += x23[2] unsigned* y01[2]; r4[2,3] += x23[3] unsigned* y01[3] 1849# asm 1: vmlal.u32 <r4=reg128#10,<x23=reg128#13%top,<y01=reg128#2%top 1850# asm 2: vmlal.u32 <r4=q9,<x23=d25,<y01=d3 1851vmlal.u32 q9,d25,d3 1852 1853# qhasm: r4[0,1] += x4[0] unsigned* y01[0]; r4[2,3] += x4[1] unsigned* y01[1] 1854# asm 1: vmlal.u32 <r4=reg128#10,<x4=reg128#14%bot,<y01=reg128#2%bot 1855# asm 2: vmlal.u32 <r4=q9,<x4=d26,<y01=d2 1856vmlal.u32 q9,d26,d2 1857 1858# qhasm: 2x t1 = r0 unsigned>> 26 1859# asm 1: vshr.u64 >t1=reg128#2,<r0=reg128#15,#26 1860# asm 2: vshr.u64 >t1=q1,<r0=q14,#26 1861vshr.u64 q1,q14,#26 1862 1863# qhasm: r0 &= mask 1864# asm 1: vand >r0=reg128#4,<r0=reg128#15,<mask=reg128#1 1865# asm 2: vand >r0=q3,<r0=q14,<mask=q0 1866vand q3,q14,q0 1867 1868# qhasm: 2x r1 += t1 1869# asm 1: vadd.i64 >r1=reg128#2,<r1=reg128#3,<t1=reg128#2 1870# asm 2: vadd.i64 >r1=q1,<r1=q2,<t1=q1 1871vadd.i64 q1,q2,q1 1872 1873# qhasm: 2x t4 = r3 unsigned>> 26 1874# asm 1: vshr.u64 >t4=reg128#3,<r3=reg128#9,#26 1875# asm 2: vshr.u64 >t4=q2,<r3=q8,#26 1876vshr.u64 q2,q8,#26 1877 1878# qhasm: r3 &= mask 1879# asm 1: vand >r3=reg128#9,<r3=reg128#9,<mask=reg128#1 1880# asm 2: vand >r3=q8,<r3=q8,<mask=q0 1881vand q8,q8,q0 1882 1883# qhasm: 2x r4 += t4 1884# asm 1: vadd.i64 >r4=reg128#3,<r4=reg128#10,<t4=reg128#3 1885# asm 2: vadd.i64 >r4=q2,<r4=q9,<t4=q2 1886vadd.i64 q2,q9,q2 1887 1888# qhasm: 2x t2 = r1 unsigned>> 26 1889# asm 1: vshr.u64 >t2=reg128#10,<r1=reg128#2,#26 1890# asm 2: vshr.u64 >t2=q9,<r1=q1,#26 1891vshr.u64 q9,q1,#26 1892 1893# qhasm: r1 &= mask 1894# asm 1: vand >r1=reg128#2,<r1=reg128#2,<mask=reg128#1 1895# asm 2: vand >r1=q1,<r1=q1,<mask=q0 1896vand q1,q1,q0 1897 1898# qhasm: 2x t0 = r4 unsigned>> 26 1899# asm 1: vshr.u64 >t0=reg128#11,<r4=reg128#3,#26 1900# asm 2: vshr.u64 >t0=q10,<r4=q2,#26 1901vshr.u64 q10,q2,#26 1902 1903# qhasm: 2x r2 += t2 1904# asm 1: vadd.i64 >r2=reg128#10,<r2=reg128#16,<t2=reg128#10 1905# asm 2: vadd.i64 >r2=q9,<r2=q15,<t2=q9 1906vadd.i64 q9,q15,q9 1907 1908# qhasm: r4 &= mask 1909# asm 1: vand >r4=reg128#3,<r4=reg128#3,<mask=reg128#1 1910# asm 2: vand >r4=q2,<r4=q2,<mask=q0 1911vand q2,q2,q0 1912 1913# qhasm: 2x r0 += t0 1914# asm 1: vadd.i64 >r0=reg128#4,<r0=reg128#4,<t0=reg128#11 1915# asm 2: vadd.i64 >r0=q3,<r0=q3,<t0=q10 1916vadd.i64 q3,q3,q10 1917 1918# qhasm: 2x t0 <<= 2 1919# asm 1: vshl.i64 >t0=reg128#11,<t0=reg128#11,#2 1920# asm 2: vshl.i64 >t0=q10,<t0=q10,#2 1921vshl.i64 q10,q10,#2 1922 1923# qhasm: 2x t3 = r2 unsigned>> 26 1924# asm 1: vshr.u64 >t3=reg128#12,<r2=reg128#10,#26 1925# asm 2: vshr.u64 >t3=q11,<r2=q9,#26 1926vshr.u64 q11,q9,#26 1927 1928# qhasm: 2x r0 += t0 1929# asm 1: vadd.i64 >r0=reg128#4,<r0=reg128#4,<t0=reg128#11 1930# asm 2: vadd.i64 >r0=q3,<r0=q3,<t0=q10 1931vadd.i64 q3,q3,q10 1932 1933# qhasm: x23 = r2 & mask 1934# asm 1: vand >x23=reg128#10,<r2=reg128#10,<mask=reg128#1 1935# asm 2: vand >x23=q9,<r2=q9,<mask=q0 1936vand q9,q9,q0 1937 1938# qhasm: 2x r3 += t3 1939# asm 1: vadd.i64 >r3=reg128#9,<r3=reg128#9,<t3=reg128#12 1940# asm 2: vadd.i64 >r3=q8,<r3=q8,<t3=q11 1941vadd.i64 q8,q8,q11 1942 1943# qhasm: 2x t1 = r0 unsigned>> 26 1944# asm 1: vshr.u64 >t1=reg128#11,<r0=reg128#4,#26 1945# asm 2: vshr.u64 >t1=q10,<r0=q3,#26 1946vshr.u64 q10,q3,#26 1947 1948# qhasm: x23 = x23[0,2,1,3] 1949# asm 1: vtrn.32 <x23=reg128#10%bot,<x23=reg128#10%top 1950# asm 2: vtrn.32 <x23=d18,<x23=d19 1951vtrn.32 d18,d19 1952 1953# qhasm: x01 = r0 & mask 1954# asm 1: vand >x01=reg128#4,<r0=reg128#4,<mask=reg128#1 1955# asm 2: vand >x01=q3,<r0=q3,<mask=q0 1956vand q3,q3,q0 1957 1958# qhasm: 2x r1 += t1 1959# asm 1: vadd.i64 >r1=reg128#2,<r1=reg128#2,<t1=reg128#11 1960# asm 2: vadd.i64 >r1=q1,<r1=q1,<t1=q10 1961vadd.i64 q1,q1,q10 1962 1963# qhasm: 2x t4 = r3 unsigned>> 26 1964# asm 1: vshr.u64 >t4=reg128#11,<r3=reg128#9,#26 1965# asm 2: vshr.u64 >t4=q10,<r3=q8,#26 1966vshr.u64 q10,q8,#26 1967 1968# qhasm: x01 = x01[0,2,1,3] 1969# asm 1: vtrn.32 <x01=reg128#4%bot,<x01=reg128#4%top 1970# asm 2: vtrn.32 <x01=d6,<x01=d7 1971vtrn.32 d6,d7 1972 1973# qhasm: r3 &= mask 1974# asm 1: vand >r3=reg128#1,<r3=reg128#9,<mask=reg128#1 1975# asm 2: vand >r3=q0,<r3=q8,<mask=q0 1976vand q0,q8,q0 1977 1978# qhasm: r1 = r1[0,2,1,3] 1979# asm 1: vtrn.32 <r1=reg128#2%bot,<r1=reg128#2%top 1980# asm 2: vtrn.32 <r1=d2,<r1=d3 1981vtrn.32 d2,d3 1982 1983# qhasm: 2x x4 = r4 + t4 1984# asm 1: vadd.i64 >x4=reg128#3,<r4=reg128#3,<t4=reg128#11 1985# asm 2: vadd.i64 >x4=q2,<r4=q2,<t4=q10 1986vadd.i64 q2,q2,q10 1987 1988# qhasm: r3 = r3[0,2,1,3] 1989# asm 1: vtrn.32 <r3=reg128#1%bot,<r3=reg128#1%top 1990# asm 2: vtrn.32 <r3=d0,<r3=d1 1991vtrn.32 d0,d1 1992 1993# qhasm: x01 = x01[0,1] r1[0,1] 1994# asm 1: vext.32 <x01=reg128#4%top,<r1=reg128#2%bot,<r1=reg128#2%bot,#0 1995# asm 2: vext.32 <x01=d7,<r1=d2,<r1=d2,#0 1996vext.32 d7,d2,d2,#0 1997 1998# qhasm: x23 = x23[0,1] r3[0,1] 1999# asm 1: vext.32 <x23=reg128#10%top,<r3=reg128#1%bot,<r3=reg128#1%bot,#0 2000# asm 2: vext.32 <x23=d19,<r3=d0,<r3=d0,#0 2001vext.32 d19,d0,d0,#0 2002 2003# qhasm: x4 = x4[0,2,1,3] 2004# asm 1: vtrn.32 <x4=reg128#3%bot,<x4=reg128#3%top 2005# asm 2: vtrn.32 <x4=d4,<x4=d5 2006vtrn.32 d4,d5 2007 2008# qhasm: mem128[input_0] aligned= x01;input_0+=16 2009# asm 1: vst1.8 {<x01=reg128#4%bot-<x01=reg128#4%top},[<input_0=int32#1,: 128]! 2010# asm 2: vst1.8 {<x01=d6-<x01=d7},[<input_0=r0,: 128]! 2011vst1.8 {d6-d7},[r0,: 128]! 2012 2013# qhasm: mem128[input_0] aligned= x23;input_0+=16 2014# asm 1: vst1.8 {<x23=reg128#10%bot-<x23=reg128#10%top},[<input_0=int32#1,: 128]! 2015# asm 2: vst1.8 {<x23=d18-<x23=d19},[<input_0=r0,: 128]! 2016vst1.8 {d18-d19},[r0,: 128]! 2017 2018# qhasm: mem64[input_0] aligned= x4[0] 2019# asm 1: vst1.8 <x4=reg128#3%bot,[<input_0=int32#1,: 64] 2020# asm 2: vst1.8 <x4=d4,[<input_0=r0,: 64] 2021vst1.8 d4,[r0,: 64] 2022 2023# qhasm: return 2024add sp,sp,#0 2025bx lr 2026 2027#endif /* __arm__ && !OPENSSL_NO_ASM && !__APPLE__ */ 2028 2029#if defined(__ELF__) 2030.section .note.GNU-stack,"",%progbits 2031#endif 2032